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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
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1 | 2 | /* |
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2 | 3 | * Renesas R-Car Gen2 PHY driver |
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3 | 4 | * |
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4 | 5 | * Copyright (C) 2014 Renesas Solutions Corp. |
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5 | 6 | * Copyright (C) 2014 Cogent Embedded, Inc. |
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6 | | - * |
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7 | | - * This program is free software; you can redistribute it and/or modify |
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8 | | - * it under the terms of the GNU General Public License version 2 as |
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9 | | - * published by the Free Software Foundation. |
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| 7 | + * Copyright (C) 2019 Renesas Electronics Corp. |
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10 | 8 | */ |
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11 | 9 | |
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12 | 10 | #include <linux/clk.h> |
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.. | .. |
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18 | 16 | #include <linux/platform_device.h> |
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19 | 17 | #include <linux/spinlock.h> |
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20 | 18 | #include <linux/atomic.h> |
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| 19 | +#include <linux/of_device.h> |
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21 | 20 | |
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22 | 21 | #define USBHS_LPSTS 0x02 |
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23 | 22 | #define USBHS_UGCTRL 0x80 |
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.. | .. |
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38 | 37 | #define USBHS_UGCTRL2_USB0SEL 0x00000030 |
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39 | 38 | #define USBHS_UGCTRL2_USB0SEL_PCI 0x00000010 |
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40 | 39 | #define USBHS_UGCTRL2_USB0SEL_HS_USB 0x00000030 |
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| 40 | +#define USBHS_UGCTRL2_USB0SEL_USB20 0x00000010 |
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| 41 | +#define USBHS_UGCTRL2_USB0SEL_HS_USB20 0x00000020 |
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41 | 42 | |
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42 | 43 | /* USB General status register (UGSTS) */ |
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43 | 44 | #define USBHS_UGSTS_LOCK 0x00000100 /* From technical update */ |
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.. | .. |
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65 | 66 | spinlock_t lock; |
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66 | 67 | int num_channels; |
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67 | 68 | struct rcar_gen2_channel *channels; |
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| 69 | +}; |
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| 70 | + |
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| 71 | +struct rcar_gen2_phy_data { |
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| 72 | + const struct phy_ops *gen2_phy_ops; |
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| 73 | + const u32 (*select_value)[PHYS_PER_CHANNEL]; |
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| 74 | + const u32 num_channels; |
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68 | 75 | }; |
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69 | 76 | |
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70 | 77 | static int rcar_gen2_phy_init(struct phy *p) |
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.. | .. |
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183 | 190 | return 0; |
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184 | 191 | } |
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185 | 192 | |
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| 193 | +static int rz_g1c_phy_power_on(struct phy *p) |
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| 194 | +{ |
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| 195 | + struct rcar_gen2_phy *phy = phy_get_drvdata(p); |
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| 196 | + struct rcar_gen2_phy_driver *drv = phy->channel->drv; |
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| 197 | + void __iomem *base = drv->base; |
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| 198 | + unsigned long flags; |
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| 199 | + u32 value; |
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| 200 | + |
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| 201 | + spin_lock_irqsave(&drv->lock, flags); |
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| 202 | + |
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| 203 | + /* Power on USBHS PHY */ |
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| 204 | + value = readl(base + USBHS_UGCTRL); |
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| 205 | + value &= ~USBHS_UGCTRL_PLLRESET; |
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| 206 | + writel(value, base + USBHS_UGCTRL); |
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| 207 | + |
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| 208 | + /* As per the data sheet wait 340 micro sec for power stable */ |
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| 209 | + udelay(340); |
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| 210 | + |
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| 211 | + if (phy->select_value == USBHS_UGCTRL2_USB0SEL_HS_USB20) { |
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| 212 | + value = readw(base + USBHS_LPSTS); |
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| 213 | + value |= USBHS_LPSTS_SUSPM; |
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| 214 | + writew(value, base + USBHS_LPSTS); |
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| 215 | + } |
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| 216 | + |
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| 217 | + spin_unlock_irqrestore(&drv->lock, flags); |
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| 218 | + |
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| 219 | + return 0; |
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| 220 | +} |
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| 221 | + |
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| 222 | +static int rz_g1c_phy_power_off(struct phy *p) |
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| 223 | +{ |
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| 224 | + struct rcar_gen2_phy *phy = phy_get_drvdata(p); |
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| 225 | + struct rcar_gen2_phy_driver *drv = phy->channel->drv; |
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| 226 | + void __iomem *base = drv->base; |
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| 227 | + unsigned long flags; |
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| 228 | + u32 value; |
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| 229 | + |
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| 230 | + spin_lock_irqsave(&drv->lock, flags); |
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| 231 | + /* Power off USBHS PHY */ |
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| 232 | + if (phy->select_value == USBHS_UGCTRL2_USB0SEL_HS_USB20) { |
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| 233 | + value = readw(base + USBHS_LPSTS); |
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| 234 | + value &= ~USBHS_LPSTS_SUSPM; |
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| 235 | + writew(value, base + USBHS_LPSTS); |
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| 236 | + } |
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| 237 | + |
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| 238 | + value = readl(base + USBHS_UGCTRL); |
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| 239 | + value |= USBHS_UGCTRL_PLLRESET; |
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| 240 | + writel(value, base + USBHS_UGCTRL); |
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| 241 | + |
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| 242 | + spin_unlock_irqrestore(&drv->lock, flags); |
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| 243 | + |
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| 244 | + return 0; |
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| 245 | +} |
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| 246 | + |
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186 | 247 | static const struct phy_ops rcar_gen2_phy_ops = { |
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187 | 248 | .init = rcar_gen2_phy_init, |
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188 | 249 | .exit = rcar_gen2_phy_exit, |
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.. | .. |
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191 | 252 | .owner = THIS_MODULE, |
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192 | 253 | }; |
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193 | 254 | |
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| 255 | +static const struct phy_ops rz_g1c_phy_ops = { |
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| 256 | + .init = rcar_gen2_phy_init, |
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| 257 | + .exit = rcar_gen2_phy_exit, |
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| 258 | + .power_on = rz_g1c_phy_power_on, |
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| 259 | + .power_off = rz_g1c_phy_power_off, |
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| 260 | + .owner = THIS_MODULE, |
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| 261 | +}; |
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| 262 | + |
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| 263 | +static const u32 pci_select_value[][PHYS_PER_CHANNEL] = { |
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| 264 | + [0] = { USBHS_UGCTRL2_USB0SEL_PCI, USBHS_UGCTRL2_USB0SEL_HS_USB }, |
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| 265 | + [2] = { USBHS_UGCTRL2_USB2SEL_PCI, USBHS_UGCTRL2_USB2SEL_USB30 }, |
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| 266 | +}; |
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| 267 | + |
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| 268 | +static const u32 usb20_select_value[][PHYS_PER_CHANNEL] = { |
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| 269 | + { USBHS_UGCTRL2_USB0SEL_USB20, USBHS_UGCTRL2_USB0SEL_HS_USB20 }, |
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| 270 | +}; |
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| 271 | + |
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| 272 | +static const struct rcar_gen2_phy_data rcar_gen2_usb_phy_data = { |
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| 273 | + .gen2_phy_ops = &rcar_gen2_phy_ops, |
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| 274 | + .select_value = pci_select_value, |
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| 275 | + .num_channels = ARRAY_SIZE(pci_select_value), |
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| 276 | +}; |
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| 277 | + |
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| 278 | +static const struct rcar_gen2_phy_data rz_g1c_usb_phy_data = { |
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| 279 | + .gen2_phy_ops = &rz_g1c_phy_ops, |
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| 280 | + .select_value = usb20_select_value, |
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| 281 | + .num_channels = ARRAY_SIZE(usb20_select_value), |
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| 282 | +}; |
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| 283 | + |
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194 | 284 | static const struct of_device_id rcar_gen2_phy_match_table[] = { |
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195 | | - { .compatible = "renesas,usb-phy-r8a7790" }, |
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196 | | - { .compatible = "renesas,usb-phy-r8a7791" }, |
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197 | | - { .compatible = "renesas,usb-phy-r8a7794" }, |
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198 | | - { .compatible = "renesas,rcar-gen2-usb-phy" }, |
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199 | | - { } |
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| 285 | + { |
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| 286 | + .compatible = "renesas,usb-phy-r8a77470", |
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| 287 | + .data = &rz_g1c_usb_phy_data, |
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| 288 | + }, |
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| 289 | + { |
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| 290 | + .compatible = "renesas,usb-phy-r8a7790", |
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| 291 | + .data = &rcar_gen2_usb_phy_data, |
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| 292 | + }, |
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| 293 | + { |
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| 294 | + .compatible = "renesas,usb-phy-r8a7791", |
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| 295 | + .data = &rcar_gen2_usb_phy_data, |
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| 296 | + }, |
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| 297 | + { |
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| 298 | + .compatible = "renesas,usb-phy-r8a7794", |
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| 299 | + .data = &rcar_gen2_usb_phy_data, |
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| 300 | + }, |
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| 301 | + { |
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| 302 | + .compatible = "renesas,rcar-gen2-usb-phy", |
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| 303 | + .data = &rcar_gen2_usb_phy_data, |
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| 304 | + }, |
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| 305 | + { /* sentinel */ }, |
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200 | 306 | }; |
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201 | 307 | MODULE_DEVICE_TABLE(of, rcar_gen2_phy_match_table); |
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202 | 308 | |
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.. | .. |
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227 | 333 | [2] = USBHS_UGCTRL2_USB2SEL, |
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228 | 334 | }; |
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229 | 335 | |
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230 | | -static const u32 select_value[][PHYS_PER_CHANNEL] = { |
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231 | | - [0] = { USBHS_UGCTRL2_USB0SEL_PCI, USBHS_UGCTRL2_USB0SEL_HS_USB }, |
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232 | | - [2] = { USBHS_UGCTRL2_USB2SEL_PCI, USBHS_UGCTRL2_USB2SEL_USB30 }, |
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233 | | -}; |
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234 | | - |
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235 | 336 | static int rcar_gen2_phy_probe(struct platform_device *pdev) |
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236 | 337 | { |
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237 | 338 | struct device *dev = &pdev->dev; |
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.. | .. |
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241 | 342 | struct resource *res; |
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242 | 343 | void __iomem *base; |
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243 | 344 | struct clk *clk; |
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| 345 | + const struct rcar_gen2_phy_data *data; |
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244 | 346 | int i = 0; |
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245 | 347 | |
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246 | 348 | if (!dev->of_node) { |
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.. | .. |
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269 | 371 | drv->clk = clk; |
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270 | 372 | drv->base = base; |
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271 | 373 | |
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| 374 | + data = of_device_get_match_data(dev); |
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| 375 | + if (!data) |
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| 376 | + return -EINVAL; |
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| 377 | + |
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272 | 378 | drv->num_channels = of_get_child_count(dev->of_node); |
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273 | 379 | drv->channels = devm_kcalloc(dev, drv->num_channels, |
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274 | 380 | sizeof(struct rcar_gen2_channel), |
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.. | .. |
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286 | 392 | channel->selected_phy = -1; |
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287 | 393 | |
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288 | 394 | error = of_property_read_u32(np, "reg", &channel_num); |
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289 | | - if (error || channel_num > 2) { |
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| 395 | + if (error || channel_num >= data->num_channels) { |
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290 | 396 | dev_err(dev, "Invalid \"reg\" property\n"); |
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291 | 397 | of_node_put(np); |
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292 | 398 | return error; |
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.. | .. |
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298 | 404 | |
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299 | 405 | phy->channel = channel; |
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300 | 406 | phy->number = n; |
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301 | | - phy->select_value = select_value[channel_num][n]; |
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| 407 | + phy->select_value = data->select_value[channel_num][n]; |
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302 | 408 | |
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303 | 409 | phy->phy = devm_phy_create(dev, NULL, |
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304 | | - &rcar_gen2_phy_ops); |
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| 410 | + data->gen2_phy_ops); |
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305 | 411 | if (IS_ERR(phy->phy)) { |
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306 | 412 | dev_err(dev, "Failed to create PHY\n"); |
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307 | 413 | of_node_put(np); |
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