| .. | .. |
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| 5 | 5 | * |
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| 6 | 6 | * GPL LICENSE SUMMARY |
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| 7 | 7 | * |
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| 8 | | - * Copyright(c) 2018 Intel Corporation |
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| 8 | + * Copyright(c) 2018 - 2021 Intel Corporation |
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| 9 | 9 | * |
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| 10 | 10 | * This program is free software; you can redistribute it and/or modify |
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| 11 | 11 | * it under the terms of version 2 of the GNU General Public License as |
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| .. | .. |
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| 18 | 18 | * |
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| 19 | 19 | * BSD LICENSE |
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| 20 | 20 | * |
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| 21 | | - * Copyright(c) 2018 Intel Corporation |
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| 21 | + * Copyright(c) 2018 - 2020 Intel Corporation |
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| 22 | 22 | * All rights reserved. |
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| 23 | 23 | * |
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| 24 | 24 | * Redistribution and use in source and binary forms, with or without |
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| .. | .. |
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| 55 | 55 | #include "internal.h" |
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| 56 | 56 | #include "iwl-prph.h" |
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| 57 | 57 | |
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| 58 | +static void |
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| 59 | +iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans, |
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| 60 | + struct iwl_prph_scratch_hwm_cfg *dbg_cfg, |
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| 61 | + u32 *control_flags) |
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| 62 | +{ |
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| 63 | + enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; |
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| 64 | + struct iwl_fw_ini_allocation_tlv *fw_mon_cfg; |
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| 65 | + u32 dbg_flags = 0; |
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| 66 | + |
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| 67 | + if (!iwl_trans_dbg_ini_valid(trans)) { |
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| 68 | + struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; |
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| 69 | + |
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| 70 | + iwl_pcie_alloc_fw_monitor(trans, 0); |
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| 71 | + |
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| 72 | + if (fw_mon->size) { |
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| 73 | + dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; |
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| 74 | + |
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| 75 | + IWL_DEBUG_FW(trans, |
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| 76 | + "WRT: Applying DRAM buffer destination\n"); |
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| 77 | + |
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| 78 | + dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); |
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| 79 | + dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); |
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| 80 | + } |
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| 81 | + |
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| 82 | + goto out; |
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| 83 | + } |
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| 84 | + |
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| 85 | + fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; |
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| 86 | + |
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| 87 | + switch (le32_to_cpu(fw_mon_cfg->buf_location)) { |
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| 88 | + case IWL_FW_INI_LOCATION_SRAM_PATH: |
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| 89 | + dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL; |
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| 90 | + IWL_DEBUG_FW(trans, |
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| 91 | + "WRT: Applying SMEM buffer destination\n"); |
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| 92 | + break; |
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| 93 | + |
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| 94 | + case IWL_FW_INI_LOCATION_NPK_PATH: |
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| 95 | + dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF; |
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| 96 | + IWL_DEBUG_FW(trans, |
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| 97 | + "WRT: Applying NPK buffer destination\n"); |
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| 98 | + break; |
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| 99 | + |
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| 100 | + case IWL_FW_INI_LOCATION_DRAM_PATH: |
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| 101 | + if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { |
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| 102 | + struct iwl_dram_data *frag = |
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| 103 | + &trans->dbg.fw_mon_ini[alloc_id].frags[0]; |
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| 104 | + dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; |
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| 105 | + dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); |
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| 106 | + dbg_cfg->hwm_size = cpu_to_le32(frag->size); |
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| 107 | + IWL_DEBUG_FW(trans, |
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| 108 | + "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n", |
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| 109 | + alloc_id, |
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| 110 | + trans->dbg.fw_mon_ini[alloc_id].num_frags); |
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| 111 | + } |
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| 112 | + break; |
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| 113 | + default: |
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| 114 | + IWL_ERR(trans, "WRT: Invalid buffer destination\n"); |
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| 115 | + } |
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| 116 | +out: |
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| 117 | + if (dbg_flags) |
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| 118 | + *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags; |
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| 119 | +} |
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| 120 | + |
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| 58 | 121 | int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans, |
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| 59 | 122 | const struct fw_img *fw) |
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| 60 | 123 | { |
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| .. | .. |
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| 65 | 128 | struct iwl_prph_info *prph_info; |
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| 66 | 129 | u32 control_flags = 0; |
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| 67 | 130 | int ret; |
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| 131 | + int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE, |
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| 132 | + trans->cfg->min_txq_size); |
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| 133 | + |
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| 134 | + switch (trans_pcie->rx_buf_size) { |
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| 135 | + case IWL_AMSDU_DEF: |
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| 136 | + return -EINVAL; |
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| 137 | + case IWL_AMSDU_2K: |
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| 138 | + break; |
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| 139 | + case IWL_AMSDU_4K: |
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| 140 | + control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; |
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| 141 | + break; |
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| 142 | + case IWL_AMSDU_8K: |
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| 143 | + control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; |
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| 144 | + /* if firmware supports the ext size, tell it */ |
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| 145 | + control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K; |
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| 146 | + break; |
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| 147 | + case IWL_AMSDU_12K: |
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| 148 | + control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K; |
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| 149 | + /* if firmware supports the ext size, tell it */ |
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| 150 | + control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K; |
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| 151 | + break; |
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| 152 | + } |
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| 68 | 153 | |
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| 69 | 154 | /* Allocate prph scratch */ |
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| 70 | 155 | prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), |
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| .. | .. |
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| 80 | 165 | cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV)); |
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| 81 | 166 | prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); |
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| 82 | 167 | |
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| 83 | | - control_flags = IWL_PRPH_SCRATCH_RB_SIZE_4K | |
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| 84 | | - IWL_PRPH_SCRATCH_MTR_MODE | |
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| 85 | | - (IWL_PRPH_MTR_FORMAT_256B & |
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| 86 | | - IWL_PRPH_SCRATCH_MTR_FORMAT) | |
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| 87 | | - IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | |
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| 88 | | - IWL_PRPH_SCRATCH_EDBG_DEST_DRAM; |
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| 89 | | - prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); |
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| 168 | + control_flags |= IWL_PRPH_SCRATCH_MTR_MODE; |
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| 169 | + control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT; |
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| 90 | 170 | |
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| 91 | 171 | /* initialize RX default queue */ |
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| 92 | 172 | prph_sc_ctrl->rbd_cfg.free_rbd_addr = |
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| 93 | 173 | cpu_to_le64(trans_pcie->rxq->bd_dma); |
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| 94 | 174 | |
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| 95 | | - /* Configure debug, for integration */ |
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| 96 | | - iwl_pcie_alloc_fw_monitor(trans, 0); |
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| 97 | | - prph_sc_ctrl->hwm_cfg.hwm_base_addr = |
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| 98 | | - cpu_to_le64(trans_pcie->fw_mon_phys); |
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| 99 | | - prph_sc_ctrl->hwm_cfg.hwm_size = |
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| 100 | | - cpu_to_le32(trans_pcie->fw_mon_size); |
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| 175 | + iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, |
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| 176 | + &control_flags); |
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| 177 | + prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); |
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| 101 | 178 | |
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| 102 | 179 | /* allocate ucode sections in dram and set addresses */ |
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| 103 | 180 | ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram); |
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| .. | .. |
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| 143 | 220 | ctxt_info_gen3->tr_idx_arr_size = |
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| 144 | 221 | cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS); |
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| 145 | 222 | ctxt_info_gen3->mtr_base_addr = |
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| 146 | | - cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr); |
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| 223 | + cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr); |
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| 147 | 224 | ctxt_info_gen3->mcr_base_addr = |
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| 148 | 225 | cpu_to_le64(trans_pcie->rxq->used_bd_dma); |
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| 149 | 226 | ctxt_info_gen3->mtr_size = |
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| 150 | | - cpu_to_le16(TFD_QUEUE_CB_SIZE(TFD_CMD_SLOTS)); |
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| 227 | + cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size)); |
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| 151 | 228 | ctxt_info_gen3->mcr_size = |
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| 152 | | - cpu_to_le16(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE)); |
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| 229 | + cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds)); |
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| 153 | 230 | |
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| 154 | 231 | trans_pcie->ctxt_info_gen3 = ctxt_info_gen3; |
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| 155 | 232 | trans_pcie->prph_info = prph_info; |
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| .. | .. |
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| 174 | 251 | iwl_write64(trans, CSR_IML_DATA_ADDR, |
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| 175 | 252 | trans_pcie->iml_dma_addr); |
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| 176 | 253 | iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len); |
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| 177 | | - iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, CSR_AUTO_FUNC_BOOT_ENA); |
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| 178 | | - iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT); |
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| 254 | + |
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| 255 | + iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, |
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| 256 | + CSR_AUTO_FUNC_BOOT_ENA); |
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| 179 | 257 | |
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| 180 | 258 | return 0; |
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| 181 | 259 | |
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| .. | .. |
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| 231 | 309 | trans_pcie->prph_info_dma_addr = 0; |
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| 232 | 310 | trans_pcie->prph_info = NULL; |
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| 233 | 311 | } |
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| 312 | + |
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| 313 | +int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans, |
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| 314 | + const void *data, u32 len) |
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| 315 | +{ |
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| 316 | + struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
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| 317 | + struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl = |
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| 318 | + &trans_pcie->prph_scratch->ctrl_cfg; |
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| 319 | + int ret; |
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| 320 | + |
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| 321 | + if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) |
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| 322 | + return 0; |
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| 323 | + |
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| 324 | + /* only allocate the DRAM if not allocated yet */ |
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| 325 | + if (!trans->pnvm_loaded) { |
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| 326 | + if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) |
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| 327 | + return -EBUSY; |
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| 328 | + |
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| 329 | + ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len, |
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| 330 | + &trans_pcie->pnvm_dram); |
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| 331 | + if (ret < 0) { |
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| 332 | + IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n", |
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| 333 | + ret); |
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| 334 | + return ret; |
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| 335 | + } |
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| 336 | + } |
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| 337 | + |
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| 338 | + prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = |
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| 339 | + cpu_to_le64(trans_pcie->pnvm_dram.physical); |
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| 340 | + prph_sc_ctrl->pnvm_cfg.pnvm_size = |
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| 341 | + cpu_to_le32(trans_pcie->pnvm_dram.size); |
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| 342 | + |
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| 343 | + return 0; |
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| 344 | +} |
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