add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/net/wireless/intel/iwlwifi/iwl-csr.h
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@@ -8,7 +8,7 @@
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  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
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  * Copyright(c) 2016        Intel Deutschland GmbH
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- * Copyright(c) 2018 Intel Corporation
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+ * Copyright(c) 2018 - 2019 Intel Corporation
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  *
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  * This program is free software; you can redistribute it and/or modify
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  * it under the terms of version 2 of the GNU General Public License as
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@@ -18,11 +18,6 @@
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  * WITHOUT ANY WARRANTY; without even the implied warranty of
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  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  * General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, write to the Free Software
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- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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- * USA
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  *
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  * The full GNU General Public License is included in this distribution
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  * in the file called COPYING.
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@@ -35,7 +30,7 @@
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  *
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  * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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  * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
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- * Copyright(c) 2018 Intel Corporation
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+ * Copyright(c) 2018 - 2019 Intel Corporation
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  * All rights reserved.
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  *
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  * Redistribution and use in source and binary forms, with or without
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@@ -152,6 +147,16 @@
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 #define CSR_MAC_SHADOW_REG_CTL2		(CSR_BASE + 0x0AC)
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 #define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE	0xFFFF
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+/* LTR control (since IWL_DEVICE_FAMILY_22000) */
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+#define CSR_LTR_LONG_VAL_AD			(CSR_BASE + 0x0D4)
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+#define CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ	0x80000000
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+#define CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE	0x1c000000
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+#define CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL	0x03ff0000
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+#define CSR_LTR_LONG_VAL_AD_SNOOP_REQ		0x00008000
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+#define CSR_LTR_LONG_VAL_AD_SNOOP_SCALE		0x00001c00
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+#define CSR_LTR_LONG_VAL_AD_SNOOP_VAL		0x000003ff
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+#define CSR_LTR_LONG_VAL_AD_SCALE_USEC		2
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+
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 /* GIO Chicken Bits (PCI Express bus link power management) */
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 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
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@@ -185,9 +190,11 @@
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 /* Bits for CSR_HW_IF_CONFIG_REG */
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 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH	(0x00000003)
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 #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP	(0x0000000C)
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+#define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM	(0x00000080)
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 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER	(0x000000C0)
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 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI		(0x00000100)
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 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI	(0x00000200)
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+#define CSR_HW_IF_CONFIG_REG_D3_DEBUG		(0x00000200)
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 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE	(0x00000C00)
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 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH	(0x00003000)
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 #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP	(0x0000C000)
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@@ -259,6 +266,7 @@
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 /* RESET */
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 #define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
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 #define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
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+#define CSR_RESET_REG_FLAG_SW_RESET		     (0x00000080)
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 #define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
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 #define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
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 #define CSR_RESET_LINK_PWR_MGMT_DISABLED             (0x80000000)
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@@ -281,9 +289,34 @@
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  *     4:  GOING_TO_SLEEP
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  *         Indicates MAC is entering a power-saving sleep power-down.
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  *         Not a good time to access device-internal resources.
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+ *     3:  MAC_ACCESS_REQ
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+ *         Host sets this to request and maintain MAC wakeup, to allow host
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+ *         access to device-internal resources.  Host must wait for
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+ *         MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
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+ *         device registers.
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+ *     2:  INIT_DONE
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+ *         Host sets this to put device into fully operational D0 power mode.
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+ *         Host resets this after SW_RESET to put device into low power mode.
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+ *     0:  MAC_CLOCK_READY
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+ *         Indicates MAC (ucode processor, etc.) is powered up and can run.
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+ *         Internal resources are accessible.
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+ *         NOTE:  This does not indicate that the processor is actually running.
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+ *         NOTE:  This does not indicate that device has completed
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+ *                init or post-power-down restore of internal SRAM memory.
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+ *                Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
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+ *                SRAM is restored and uCode is in normal operation mode.
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+ *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
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+ *                do not need to save/restore it.
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+ *         NOTE:  After device reset, this bit remains "0" until host sets
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+ *                INIT_DONE
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  */
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-#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP         (0x00000010)
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+#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY	     (0x00000001)
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+#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE		     (0x00000004)
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+#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ	     (0x00000008)
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+#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP	     (0x00000010)
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 #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON		     (0x00000400)
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+
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+#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN	     (0x00000001)
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 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
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 #define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN     (0x04000000)
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@@ -293,6 +326,7 @@
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 /* HW REV */
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 #define CSR_HW_REV_DASH(_val)          (((_val) & 0x0000003) >> 0)
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 #define CSR_HW_REV_STEP(_val)          (((_val) & 0x000000C) >> 2)
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+#define CSR_HW_REV_TYPE(_val)          (((_val) & 0x000FFF0) >> 4)
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 /* HW RFID */
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 #define CSR_HW_RFID_FLAVOR(_val)       (((_val) & 0x000000F) >> 0)
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@@ -329,12 +363,21 @@
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 #define CSR_HW_REV_TYPE_7265D		(0x0000210)
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 #define CSR_HW_REV_TYPE_NONE		(0x00001F0)
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 #define CSR_HW_REV_TYPE_QNJ		(0x0000360)
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+#define CSR_HW_REV_TYPE_QNJ_B0		(0x0000364)
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+#define CSR_HW_REV_TYPE_QU_B0		(0x0000334)
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+#define CSR_HW_REV_TYPE_QU_C0		(0x0000338)
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+#define CSR_HW_REV_TYPE_QUZ		(0x0000354)
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 #define CSR_HW_REV_TYPE_HR_CDB		(0x0000340)
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+#define CSR_HW_REV_TYPE_SO		(0x0000370)
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+#define CSR_HW_REV_TYPE_TY		(0x0000420)
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 /* RF_ID value */
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 #define CSR_HW_RF_ID_TYPE_JF		(0x00105100)
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 #define CSR_HW_RF_ID_TYPE_HR		(0x0010A000)
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+#define CSR_HW_RF_ID_TYPE_HR1		(0x0010c100)
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 #define CSR_HW_RF_ID_TYPE_HRCDB		(0x00109F00)
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+#define CSR_HW_RF_ID_TYPE_GF		(0x0010D000)
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+#define CSR_HW_RF_ID_TYPE_GF4		(0x0010E000)
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 /* HW_RF CHIP ID  */
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 #define CSR_HW_RF_ID_TYPE_CHIP_ID(_val) (((_val) >> 12) & 0xFFF)
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@@ -371,7 +414,7 @@
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 /* CSR GIO */
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-#define CSR_GIO_REG_VAL_L0S_ENABLED	(0x00000002)
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+#define CSR_GIO_REG_VAL_L0S_DISABLED	(0x00000002)
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 /*
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  * UCODE-DRIVER GP (general purpose) mailbox register 1
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@@ -595,8 +638,7 @@
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 enum msix_hw_int_causes {
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 	MSIX_HW_INT_CAUSES_REG_ALIVE		= BIT(0),
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 	MSIX_HW_INT_CAUSES_REG_WAKEUP		= BIT(1),
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-	MSIX_HW_INT_CAUSES_REG_IPC		= BIT(1),
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-	MSIX_HW_INT_CAUSES_REG_SW_ERR_V2	= BIT(5),
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+	MSIX_HW_INT_CAUSES_REG_IML              = BIT(2),
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 	MSIX_HW_INT_CAUSES_REG_CT_KILL		= BIT(6),
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 	MSIX_HW_INT_CAUSES_REG_RF_KILL		= BIT(7),
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 	MSIX_HW_INT_CAUSES_REG_PERIODIC		= BIT(8),