.. | .. |
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459 | 459 | {0x0000a3e0, 0x000001ce}, |
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460 | 460 | }; |
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461 | 461 | |
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462 | | -static const u32 ar5416Bank0[][2] = { |
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463 | | - /* Addr allmodes */ |
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464 | | - {0x000098b0, 0x1e5795e5}, |
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465 | | - {0x000098e0, 0x02008020}, |
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466 | | -}; |
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467 | | - |
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468 | 462 | static const u32 ar5416BB_RfGain[][3] = { |
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469 | 463 | /* Addr 5G 2G */ |
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470 | 464 | {0x00009a00, 0x00000000, 0x00000000}, |
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.. | .. |
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533 | 527 | {0x00009afc, 0x000000f9, 0x000000f9}, |
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534 | 528 | }; |
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535 | 529 | |
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536 | | -static const u32 ar5416Bank1[][2] = { |
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537 | | - /* Addr allmodes */ |
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538 | | - {0x000098b0, 0x02108421}, |
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539 | | - {0x000098ec, 0x00000008}, |
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540 | | -}; |
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541 | | - |
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542 | | -static const u32 ar5416Bank2[][2] = { |
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543 | | - /* Addr allmodes */ |
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544 | | - {0x000098b0, 0x0e73ff17}, |
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545 | | - {0x000098e0, 0x00000420}, |
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546 | | -}; |
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547 | | - |
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548 | | -static const u32 ar5416Bank3[][3] = { |
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549 | | - /* Addr 5G 2G */ |
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550 | | - {0x000098f0, 0x01400018, 0x01c00018}, |
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551 | | -}; |
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552 | | - |
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553 | | -static const u32 ar5416Bank6[][3] = { |
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554 | | - /* Addr 5G 2G */ |
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555 | | - {0x0000989c, 0x00000000, 0x00000000}, |
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556 | | - {0x0000989c, 0x00000000, 0x00000000}, |
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557 | | - {0x0000989c, 0x00000000, 0x00000000}, |
---|
558 | | - {0x0000989c, 0x00e00000, 0x00e00000}, |
---|
559 | | - {0x0000989c, 0x005e0000, 0x005e0000}, |
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560 | | - {0x0000989c, 0x00120000, 0x00120000}, |
---|
561 | | - {0x0000989c, 0x00620000, 0x00620000}, |
---|
562 | | - {0x0000989c, 0x00020000, 0x00020000}, |
---|
563 | | - {0x0000989c, 0x00ff0000, 0x00ff0000}, |
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564 | | - {0x0000989c, 0x00ff0000, 0x00ff0000}, |
---|
565 | | - {0x0000989c, 0x00ff0000, 0x00ff0000}, |
---|
566 | | - {0x0000989c, 0x40ff0000, 0x40ff0000}, |
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567 | | - {0x0000989c, 0x005f0000, 0x005f0000}, |
---|
568 | | - {0x0000989c, 0x00870000, 0x00870000}, |
---|
569 | | - {0x0000989c, 0x00f90000, 0x00f90000}, |
---|
570 | | - {0x0000989c, 0x007b0000, 0x007b0000}, |
---|
571 | | - {0x0000989c, 0x00ff0000, 0x00ff0000}, |
---|
572 | | - {0x0000989c, 0x00f50000, 0x00f50000}, |
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573 | | - {0x0000989c, 0x00dc0000, 0x00dc0000}, |
---|
574 | | - {0x0000989c, 0x00110000, 0x00110000}, |
---|
575 | | - {0x0000989c, 0x006100a8, 0x006100a8}, |
---|
576 | | - {0x0000989c, 0x004210a2, 0x004210a2}, |
---|
577 | | - {0x0000989c, 0x0014008f, 0x0014008f}, |
---|
578 | | - {0x0000989c, 0x00c40003, 0x00c40003}, |
---|
579 | | - {0x0000989c, 0x003000f2, 0x003000f2}, |
---|
580 | | - {0x0000989c, 0x00440016, 0x00440016}, |
---|
581 | | - {0x0000989c, 0x00410040, 0x00410040}, |
---|
582 | | - {0x0000989c, 0x0001805e, 0x0001805e}, |
---|
583 | | - {0x0000989c, 0x0000c0ab, 0x0000c0ab}, |
---|
584 | | - {0x0000989c, 0x000000f1, 0x000000f1}, |
---|
585 | | - {0x0000989c, 0x00002081, 0x00002081}, |
---|
586 | | - {0x0000989c, 0x000000d4, 0x000000d4}, |
---|
587 | | - {0x000098d0, 0x0000000f, 0x0010000f}, |
---|
588 | | -}; |
---|
589 | | - |
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590 | 530 | static const u32 ar5416Bank6TPC[][3] = { |
---|
591 | 531 | /* Addr 5G 2G */ |
---|
592 | 532 | {0x0000989c, 0x00000000, 0x00000000}, |
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.. | .. |
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622 | 562 | {0x0000989c, 0x00007081, 0x00007081}, |
---|
623 | 563 | {0x0000989c, 0x000000d4, 0x000000d4}, |
---|
624 | 564 | {0x000098d0, 0x0000000f, 0x0010000f}, |
---|
625 | | -}; |
---|
626 | | - |
---|
627 | | -static const u32 ar5416Bank7[][2] = { |
---|
628 | | - /* Addr allmodes */ |
---|
629 | | - {0x0000989c, 0x00000500}, |
---|
630 | | - {0x0000989c, 0x00000800}, |
---|
631 | | - {0x000098cc, 0x0000000e}, |
---|
632 | 565 | }; |
---|
633 | 566 | |
---|
634 | 567 | static const u32 ar5416Addac[][2] = { |
---|
.. | .. |
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671 | 604 | {0x0000989c, 0x00000000}, |
---|
672 | 605 | {0x000098c4, 0x00000000}, |
---|
673 | 606 | }; |
---|
674 | | - |
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