add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/net/dsa/mv88e6xxx/port.h
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@@ -1,3 +1,4 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  * Marvell 88E6xxx Switch Port Registers support
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  *
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@@ -5,11 +6,6 @@
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  *
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  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
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  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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  */
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 #ifndef _MV88E6XXX_PORT_H
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@@ -23,6 +19,16 @@
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 #define MV88E6XXX_PORT_STS_MY_PAUSE		0x4000
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 #define MV88E6XXX_PORT_STS_HD_FLOW		0x2000
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 #define MV88E6XXX_PORT_STS_PHY_DETECT		0x1000
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+#define MV88E6250_PORT_STS_LINK				0x1000
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+#define MV88E6250_PORT_STS_PORTMODE_MASK		0x0f00
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+#define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF		0x0800
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+#define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF	0x0900
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+#define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL		0x0a00
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+#define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL	0x0b00
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+#define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF		0x0c00
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+#define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF	0x0d00
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+#define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL		0x0e00
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+#define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL	0x0f00
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 #define MV88E6XXX_PORT_STS_LINK			0x0800
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 #define MV88E6XXX_PORT_STS_DUPLEX		0x0400
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 #define MV88E6XXX_PORT_STS_SPEED_MASK		0x0300
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@@ -36,8 +42,9 @@
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 #define MV88E6XXX_PORT_STS_TX_PAUSED		0x0020
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 #define MV88E6XXX_PORT_STS_FLOW_CTL		0x0010
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 #define MV88E6XXX_PORT_STS_CMODE_MASK		0x000f
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-#define MV88E6XXX_PORT_STS_CMODE_100BASE_X	0x0008
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-#define MV88E6XXX_PORT_STS_CMODE_1000BASE_X	0x0009
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+#define MV88E6XXX_PORT_STS_CMODE_RGMII		0x0007
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+#define MV88E6XXX_PORT_STS_CMODE_100BASEX	0x0008
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+#define MV88E6XXX_PORT_STS_CMODE_1000BASEX	0x0009
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 #define MV88E6XXX_PORT_STS_CMODE_SGMII		0x000a
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 #define MV88E6XXX_PORT_STS_CMODE_2500BASEX	0x000b
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 #define MV88E6XXX_PORT_STS_CMODE_XAUI		0x000c
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@@ -52,7 +59,6 @@
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 #define MV88E6185_PORT_STS_CMODE_1000BASE_X	0x0005
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 #define MV88E6185_PORT_STS_CMODE_PHY		0x0006
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 #define MV88E6185_PORT_STS_CMODE_DISABLED	0x0007
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-#define MV88E6XXX_PORT_STS_CMODE_INVALID	0xff
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 /* Offset 0x01: MAC (or PCS or Physical) Control Register */
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 #define MV88E6XXX_PORT_MAC_CTL				0x01
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@@ -112,7 +118,9 @@
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 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190	0x1900
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 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191	0x1910
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 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185	0x1a70
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+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6220	0x2200
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 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240	0x2400
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+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6250	0x2500
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 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290	0x2900
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 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321	0x3100
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 #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141	0x3400
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@@ -214,7 +222,19 @@
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 #define MV88E6XXX_PORT_PRI_OVERRIDE	0x0d
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 /* Offset 0x0E: Policy Control Register */
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-#define MV88E6XXX_PORT_POLICY_CTL	0x0e
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+#define MV88E6XXX_PORT_POLICY_CTL		0x0e
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+#define MV88E6XXX_PORT_POLICY_CTL_DA_MASK	0xc000
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+#define MV88E6XXX_PORT_POLICY_CTL_SA_MASK	0x3000
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+#define MV88E6XXX_PORT_POLICY_CTL_VTU_MASK	0x0c00
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+#define MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK	0x0300
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+#define MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK	0x00c0
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+#define MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK	0x0030
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+#define MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK	0x000c
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+#define MV88E6XXX_PORT_POLICY_CTL_UDP_MASK	0x0003
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+#define MV88E6XXX_PORT_POLICY_CTL_NORMAL	0x0000
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+#define MV88E6XXX_PORT_POLICY_CTL_MIRROR	0x0001
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+#define MV88E6XXX_PORT_POLICY_CTL_TRAP		0x0002
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+#define MV88E6XXX_PORT_POLICY_CTL_DISCARD	0x0003
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 /* Offset 0x0F: Port Special Ether Type */
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 #define MV88E6XXX_PORT_ETH_TYPE		0x0f
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@@ -253,14 +273,16 @@
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 #define MV88E6095_PORT_IEEE_PRIO_REMAP_4567	0x19
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 /* Offset 0x1a: Magic undocumented errata register */
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-#define PORT_RESERVED_1A			0x1a
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-#define PORT_RESERVED_1A_BUSY			BIT(15)
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-#define PORT_RESERVED_1A_WRITE			BIT(14)
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-#define PORT_RESERVED_1A_READ			0
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-#define PORT_RESERVED_1A_PORT_SHIFT		5
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-#define PORT_RESERVED_1A_BLOCK			(0xf << 10)
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-#define PORT_RESERVED_1A_CTRL_PORT		4
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-#define PORT_RESERVED_1A_DATA_PORT		5
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+#define MV88E6XXX_PORT_RESERVED_1A		0x1a
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+#define MV88E6XXX_PORT_RESERVED_1A_BUSY		0x8000
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+#define MV88E6XXX_PORT_RESERVED_1A_WRITE	0x4000
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+#define MV88E6XXX_PORT_RESERVED_1A_READ		0x0000
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+#define MV88E6XXX_PORT_RESERVED_1A_PORT_SHIFT	5
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+#define MV88E6XXX_PORT_RESERVED_1A_BLOCK_SHIFT	10
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+#define MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT	0x04
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+#define MV88E6XXX_PORT_RESERVED_1A_DATA_PORT	0x05
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+#define MV88E6341_PORT_RESERVED_1A_FORCE_CMODE	0x8000
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+#define MV88E6341_PORT_RESERVED_1A_SGMII_AN	0x2000
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 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
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 			u16 *val);
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@@ -276,14 +298,24 @@
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 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);
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-int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup);
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+int mv88e6065_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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+				    int speed, int duplex);
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+int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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+				    int speed, int duplex);
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+int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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+				    int speed, int duplex);
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+int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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+				    int speed, int duplex);
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+int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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+				    int speed, int duplex);
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+int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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+				    int speed, int duplex);
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+int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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+				     int speed, int duplex);
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-int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
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-int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
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-int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
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-int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
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-int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
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-int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
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+phy_interface_t mv88e6341_port_max_speed_mode(int port);
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+phy_interface_t mv88e6390_port_max_speed_mode(int port);
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+phy_interface_t mv88e6390x_port_max_speed_mode(int port);
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 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
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@@ -309,6 +341,9 @@
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 				     bool unicast, bool multicast);
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 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
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 				     bool unicast, bool multicast);
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+int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
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+			      enum mv88e6xxx_policy_mapping mapping,
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+			      enum mv88e6xxx_policy_action action);
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 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
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 				  u16 etype);
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 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
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 			       u8 out);
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 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
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 			       u8 out);
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+int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
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+			     phy_interface_t mode);
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+int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
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+			     phy_interface_t mode);
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 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
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 			      phy_interface_t mode);
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 int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
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 int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
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-int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
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-			      struct phylink_link_state *state);
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-int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
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-			      struct phylink_link_state *state);
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 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port);
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 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
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 				     int upstream_port);
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+int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
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+			      enum mv88e6xxx_egress_direction direction,
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+			      bool mirror);
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 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);
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 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);
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+int mv88e6xxx_port_hidden_write(struct mv88e6xxx_chip *chip, int block,
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+				int port, int reg, u16 val);
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+int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip);
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+int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port,
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+			       int reg, u16 *val);
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+
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 #endif /* _MV88E6XXX_PORT_H */