~ljy/RK356X_SDK_RELEASE.git

..	..	@@ -1,24 +1,23 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
3		- *
4		- * This program is free software; you can redistribute it and/or modify
5		- * it under the terms of the GNU General Public License version 2 as
6		- * published by the Free Software Foundation.
7	4	*/
8	5
9	6	#include <linux/io.h>
10	7	#include <linux/module.h>
11	8	#include <linux/mod_devicetable.h>
	9	+#include <linux/of_device.h>
12	10	#include <linux/platform_device.h>
13	11
	12	+#if defined(CONFIG_ARCH_TEGRA_186_SOC)
14	13	#include <dt-bindings/memory/tegra186-mc.h>
	14	+#endif
15	15
16		-struct tegra_mc {
17		- struct device *dev;
18		- void __iomem *regs;
19		-};
	16	+#if defined(CONFIG_ARCH_TEGRA_194_SOC)
	17	+#include <dt-bindings/memory/tegra194-mc.h>
	18	+#endif
20	19
21		-struct tegra_mc_client {
	20	+struct tegra186_mc_client {
22	21	const char *name;
23	22	unsigned int sid;
24	23	struct {
..	..	@@ -27,7 +26,46 @@
27	26	} regs;
28	27	};
29	28
30		-static const struct tegra_mc_client tegra186_mc_clients[] = {
	29	+struct tegra186_mc_soc {
	30	+ const struct tegra186_mc_client *clients;
	31	+ unsigned int num_clients;
	32	+};
	33	+
	34	+struct tegra186_mc {
	35	+ struct device *dev;
	36	+ void __iomem *regs;
	37	+
	38	+ const struct tegra186_mc_soc *soc;
	39	+};
	40	+
	41	+static void tegra186_mc_program_sid(struct tegra186_mc *mc)
	42	+{
	43	+ unsigned int i;
	44	+
	45	+ for (i = 0; i < mc->soc->num_clients; i++) {
	46	+ const struct tegra186_mc_client *client = &mc->soc->clients[i];
	47	+ u32 override, security;
	48	+
	49	+ override = readl(mc->regs + client->regs.override);
	50	+ security = readl(mc->regs + client->regs.security);
	51	+
	52	+ dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
	53	+ client->name, override, security);
	54	+
	55	+ dev_dbg(mc->dev, "setting SID %u for %s\n", client->sid,
	56	+ client->name);
	57	+ writel(client->sid, mc->regs + client->regs.override);
	58	+
	59	+ override = readl(mc->regs + client->regs.override);
	60	+ security = readl(mc->regs + client->regs.security);
	61	+
	62	+ dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
	63	+ client->name, override, security);
	64	+ }
	65	+}
	66	+
	67	+#if defined(CONFIG_ARCH_TEGRA_186_SOC)
	68	+static const struct tegra186_mc_client tegra186_mc_clients[] = {
31	69	{
32	70	.name = "ptcr",
33	71	.sid = TEGRA186_SID_PASSTHROUGH,
..	..	@@ -535,16 +573,965 @@
535	573	},
536	574	};
537	575
	576	+static const struct tegra186_mc_soc tegra186_mc_soc = {
	577	+ .num_clients = ARRAY_SIZE(tegra186_mc_clients),
	578	+ .clients = tegra186_mc_clients,
	579	+};
	580	+#endif
	581	+
	582	+#if defined(CONFIG_ARCH_TEGRA_194_SOC)
	583	+static const struct tegra186_mc_client tegra194_mc_clients[] = {
	584	+ {
	585	+ .name = "ptcr",
	586	+ .sid = TEGRA194_SID_PASSTHROUGH,
	587	+ .regs = {
	588	+ .override = 0x000,
	589	+ .security = 0x004,
	590	+ },
	591	+ }, {
	592	+ .name = "miu7r",
	593	+ .sid = TEGRA194_SID_MIU,
	594	+ .regs = {
	595	+ .override = 0x008,
	596	+ .security = 0x00c,
	597	+ },
	598	+ }, {
	599	+ .name = "miu7w",
	600	+ .sid = TEGRA194_SID_MIU,
	601	+ .regs = {
	602	+ .override = 0x010,
	603	+ .security = 0x014,
	604	+ },
	605	+ }, {
	606	+ .name = "hdar",
	607	+ .sid = TEGRA194_SID_HDA,
	608	+ .regs = {
	609	+ .override = 0x0a8,
	610	+ .security = 0x0ac,
	611	+ },
	612	+ }, {
	613	+ .name = "host1xdmar",
	614	+ .sid = TEGRA194_SID_HOST1X,
	615	+ .regs = {
	616	+ .override = 0x0b0,
	617	+ .security = 0x0b4,
	618	+ },
	619	+ }, {
	620	+ .name = "nvencsrd",
	621	+ .sid = TEGRA194_SID_NVENC,
	622	+ .regs = {
	623	+ .override = 0x0e0,
	624	+ .security = 0x0e4,
	625	+ },
	626	+ }, {
	627	+ .name = "satar",
	628	+ .sid = TEGRA194_SID_SATA,
	629	+ .regs = {
	630	+ .override = 0x0f8,
	631	+ .security = 0x0fc,
	632	+ },
	633	+ }, {
	634	+ .name = "mpcorer",
	635	+ .sid = TEGRA194_SID_PASSTHROUGH,
	636	+ .regs = {
	637	+ .override = 0x138,
	638	+ .security = 0x13c,
	639	+ },
	640	+ }, {
	641	+ .name = "nvencswr",
	642	+ .sid = TEGRA194_SID_NVENC,
	643	+ .regs = {
	644	+ .override = 0x158,
	645	+ .security = 0x15c,
	646	+ },
	647	+ }, {
	648	+ .name = "hdaw",
	649	+ .sid = TEGRA194_SID_HDA,
	650	+ .regs = {
	651	+ .override = 0x1a8,
	652	+ .security = 0x1ac,
	653	+ },
	654	+ }, {
	655	+ .name = "mpcorew",
	656	+ .sid = TEGRA194_SID_PASSTHROUGH,
	657	+ .regs = {
	658	+ .override = 0x1c8,
	659	+ .security = 0x1cc,
	660	+ },
	661	+ }, {
	662	+ .name = "sataw",
	663	+ .sid = TEGRA194_SID_SATA,
	664	+ .regs = {
	665	+ .override = 0x1e8,
	666	+ .security = 0x1ec,
	667	+ },
	668	+ }, {
	669	+ .name = "ispra",
	670	+ .sid = TEGRA194_SID_ISP,
	671	+ .regs = {
	672	+ .override = 0x220,
	673	+ .security = 0x224,
	674	+ },
	675	+ }, {
	676	+ .name = "ispfalr",
	677	+ .sid = TEGRA194_SID_ISP_FALCON,
	678	+ .regs = {
	679	+ .override = 0x228,
	680	+ .security = 0x22c,
	681	+ },
	682	+ }, {
	683	+ .name = "ispwa",
	684	+ .sid = TEGRA194_SID_ISP,
	685	+ .regs = {
	686	+ .override = 0x230,
	687	+ .security = 0x234,
	688	+ },
	689	+ }, {
	690	+ .name = "ispwb",
	691	+ .sid = TEGRA194_SID_ISP,
	692	+ .regs = {
	693	+ .override = 0x238,
	694	+ .security = 0x23c,
	695	+ },
	696	+ }, {
	697	+ .name = "xusb_hostr",
	698	+ .sid = TEGRA194_SID_XUSB_HOST,
	699	+ .regs = {
	700	+ .override = 0x250,
	701	+ .security = 0x254,
	702	+ },
	703	+ }, {
	704	+ .name = "xusb_hostw",
	705	+ .sid = TEGRA194_SID_XUSB_HOST,
	706	+ .regs = {
	707	+ .override = 0x258,
	708	+ .security = 0x25c,
	709	+ },
	710	+ }, {
	711	+ .name = "xusb_devr",
	712	+ .sid = TEGRA194_SID_XUSB_DEV,
	713	+ .regs = {
	714	+ .override = 0x260,
	715	+ .security = 0x264,
	716	+ },
	717	+ }, {
	718	+ .name = "xusb_devw",
	719	+ .sid = TEGRA194_SID_XUSB_DEV,
	720	+ .regs = {
	721	+ .override = 0x268,
	722	+ .security = 0x26c,
	723	+ },
	724	+ }, {
	725	+ .name = "sdmmcra",
	726	+ .sid = TEGRA194_SID_SDMMC1,
	727	+ .regs = {
	728	+ .override = 0x300,
	729	+ .security = 0x304,
	730	+ },
	731	+ }, {
	732	+ .name = "sdmmcr",
	733	+ .sid = TEGRA194_SID_SDMMC3,
	734	+ .regs = {
	735	+ .override = 0x310,
	736	+ .security = 0x314,
	737	+ },
	738	+ }, {
	739	+ .name = "sdmmcrab",
	740	+ .sid = TEGRA194_SID_SDMMC4,
	741	+ .regs = {
	742	+ .override = 0x318,
	743	+ .security = 0x31c,
	744	+ },
	745	+ }, {
	746	+ .name = "sdmmcwa",
	747	+ .sid = TEGRA194_SID_SDMMC1,
	748	+ .regs = {
	749	+ .override = 0x320,
	750	+ .security = 0x324,
	751	+ },
	752	+ }, {
	753	+ .name = "sdmmcw",
	754	+ .sid = TEGRA194_SID_SDMMC3,
	755	+ .regs = {
	756	+ .override = 0x330,
	757	+ .security = 0x334,
	758	+ },
	759	+ }, {
	760	+ .name = "sdmmcwab",
	761	+ .sid = TEGRA194_SID_SDMMC4,
	762	+ .regs = {
	763	+ .override = 0x338,
	764	+ .security = 0x33c,
	765	+ },
	766	+ }, {
	767	+ .name = "vicsrd",
	768	+ .sid = TEGRA194_SID_VIC,
	769	+ .regs = {
	770	+ .override = 0x360,
	771	+ .security = 0x364,
	772	+ },
	773	+ }, {
	774	+ .name = "vicswr",
	775	+ .sid = TEGRA194_SID_VIC,
	776	+ .regs = {
	777	+ .override = 0x368,
	778	+ .security = 0x36c,
	779	+ },
	780	+ }, {
	781	+ .name = "viw",
	782	+ .sid = TEGRA194_SID_VI,
	783	+ .regs = {
	784	+ .override = 0x390,
	785	+ .security = 0x394,
	786	+ },
	787	+ }, {
	788	+ .name = "nvdecsrd",
	789	+ .sid = TEGRA194_SID_NVDEC,
	790	+ .regs = {
	791	+ .override = 0x3c0,
	792	+ .security = 0x3c4,
	793	+ },
	794	+ }, {
	795	+ .name = "nvdecswr",
	796	+ .sid = TEGRA194_SID_NVDEC,
	797	+ .regs = {
	798	+ .override = 0x3c8,
	799	+ .security = 0x3cc,
	800	+ },
	801	+ }, {
	802	+ .name = "aper",
	803	+ .sid = TEGRA194_SID_APE,
	804	+ .regs = {
	805	+ .override = 0x3c0,
	806	+ .security = 0x3c4,
	807	+ },
	808	+ }, {
	809	+ .name = "apew",
	810	+ .sid = TEGRA194_SID_APE,
	811	+ .regs = {
	812	+ .override = 0x3d0,
	813	+ .security = 0x3d4,
	814	+ },
	815	+ }, {
	816	+ .name = "nvjpgsrd",
	817	+ .sid = TEGRA194_SID_NVJPG,
	818	+ .regs = {
	819	+ .override = 0x3f0,
	820	+ .security = 0x3f4,
	821	+ },
	822	+ }, {
	823	+ .name = "nvjpgswr",
	824	+ .sid = TEGRA194_SID_NVJPG,
	825	+ .regs = {
	826	+ .override = 0x3f0,
	827	+ .security = 0x3f4,
	828	+ },
	829	+ }, {
	830	+ .name = "axiapr",
	831	+ .sid = TEGRA194_SID_PASSTHROUGH,
	832	+ .regs = {
	833	+ .override = 0x410,
	834	+ .security = 0x414,
	835	+ },
	836	+ }, {
	837	+ .name = "axiapw",
	838	+ .sid = TEGRA194_SID_PASSTHROUGH,
	839	+ .regs = {
	840	+ .override = 0x418,
	841	+ .security = 0x41c,
	842	+ },
	843	+ }, {
	844	+ .name = "etrr",
	845	+ .sid = TEGRA194_SID_ETR,
	846	+ .regs = {
	847	+ .override = 0x420,
	848	+ .security = 0x424,
	849	+ },
	850	+ }, {
	851	+ .name = "etrw",
	852	+ .sid = TEGRA194_SID_ETR,
	853	+ .regs = {
	854	+ .override = 0x428,
	855	+ .security = 0x42c,
	856	+ },
	857	+ }, {
	858	+ .name = "axisr",
	859	+ .sid = TEGRA194_SID_PASSTHROUGH,
	860	+ .regs = {
	861	+ .override = 0x460,
	862	+ .security = 0x464,
	863	+ },
	864	+ }, {
	865	+ .name = "axisw",
	866	+ .sid = TEGRA194_SID_PASSTHROUGH,
	867	+ .regs = {
	868	+ .override = 0x468,
	869	+ .security = 0x46c,
	870	+ },
	871	+ }, {
	872	+ .name = "eqosr",
	873	+ .sid = TEGRA194_SID_EQOS,
	874	+ .regs = {
	875	+ .override = 0x470,
	876	+ .security = 0x474,
	877	+ },
	878	+ }, {
	879	+ .name = "eqosw",
	880	+ .sid = TEGRA194_SID_EQOS,
	881	+ .regs = {
	882	+ .override = 0x478,
	883	+ .security = 0x47c,
	884	+ },
	885	+ }, {
	886	+ .name = "ufshcr",
	887	+ .sid = TEGRA194_SID_UFSHC,
	888	+ .regs = {
	889	+ .override = 0x480,
	890	+ .security = 0x484,
	891	+ },
	892	+ }, {
	893	+ .name = "ufshcw",
	894	+ .sid = TEGRA194_SID_UFSHC,
	895	+ .regs = {
	896	+ .override = 0x488,
	897	+ .security = 0x48c,
	898	+ },
	899	+ }, {
	900	+ .name = "nvdisplayr",
	901	+ .sid = TEGRA194_SID_NVDISPLAY,
	902	+ .regs = {
	903	+ .override = 0x490,
	904	+ .security = 0x494,
	905	+ },
	906	+ }, {
	907	+ .name = "bpmpr",
	908	+ .sid = TEGRA194_SID_BPMP,
	909	+ .regs = {
	910	+ .override = 0x498,
	911	+ .security = 0x49c,
	912	+ },
	913	+ }, {
	914	+ .name = "bpmpw",
	915	+ .sid = TEGRA194_SID_BPMP,
	916	+ .regs = {
	917	+ .override = 0x4a0,
	918	+ .security = 0x4a4,
	919	+ },
	920	+ }, {
	921	+ .name = "bpmpdmar",
	922	+ .sid = TEGRA194_SID_BPMP,
	923	+ .regs = {
	924	+ .override = 0x4a8,
	925	+ .security = 0x4ac,
	926	+ },
	927	+ }, {
	928	+ .name = "bpmpdmaw",
	929	+ .sid = TEGRA194_SID_BPMP,
	930	+ .regs = {
	931	+ .override = 0x4b0,
	932	+ .security = 0x4b4,
	933	+ },
	934	+ }, {
	935	+ .name = "aonr",
	936	+ .sid = TEGRA194_SID_AON,
	937	+ .regs = {
	938	+ .override = 0x4b8,
	939	+ .security = 0x4bc,
	940	+ },
	941	+ }, {
	942	+ .name = "aonw",
	943	+ .sid = TEGRA194_SID_AON,
	944	+ .regs = {
	945	+ .override = 0x4c0,
	946	+ .security = 0x4c4,
	947	+ },
	948	+ }, {
	949	+ .name = "aondmar",
	950	+ .sid = TEGRA194_SID_AON,
	951	+ .regs = {
	952	+ .override = 0x4c8,
	953	+ .security = 0x4cc,
	954	+ },
	955	+ }, {
	956	+ .name = "aondmaw",
	957	+ .sid = TEGRA194_SID_AON,
	958	+ .regs = {
	959	+ .override = 0x4d0,
	960	+ .security = 0x4d4,
	961	+ },
	962	+ }, {
	963	+ .name = "scer",
	964	+ .sid = TEGRA194_SID_SCE,
	965	+ .regs = {
	966	+ .override = 0x4d8,
	967	+ .security = 0x4dc,
	968	+ },
	969	+ }, {
	970	+ .name = "scew",
	971	+ .sid = TEGRA194_SID_SCE,
	972	+ .regs = {
	973	+ .override = 0x4e0,
	974	+ .security = 0x4e4,
	975	+ },
	976	+ }, {
	977	+ .name = "scedmar",
	978	+ .sid = TEGRA194_SID_SCE,
	979	+ .regs = {
	980	+ .override = 0x4e8,
	981	+ .security = 0x4ec,
	982	+ },
	983	+ }, {
	984	+ .name = "scedmaw",
	985	+ .sid = TEGRA194_SID_SCE,
	986	+ .regs = {
	987	+ .override = 0x4f0,
	988	+ .security = 0x4f4,
	989	+ },
	990	+ }, {
	991	+ .name = "apedmar",
	992	+ .sid = TEGRA194_SID_APE,
	993	+ .regs = {
	994	+ .override = 0x4f8,
	995	+ .security = 0x4fc,
	996	+ },
	997	+ }, {
	998	+ .name = "apedmaw",
	999	+ .sid = TEGRA194_SID_APE,
	1000	+ .regs = {
	1001	+ .override = 0x500,
	1002	+ .security = 0x504,
	1003	+ },
	1004	+ }, {
	1005	+ .name = "nvdisplayr1",
	1006	+ .sid = TEGRA194_SID_NVDISPLAY,
	1007	+ .regs = {
	1008	+ .override = 0x508,
	1009	+ .security = 0x50c,
	1010	+ },
	1011	+ }, {
	1012	+ .name = "vicsrd1",
	1013	+ .sid = TEGRA194_SID_VIC,
	1014	+ .regs = {
	1015	+ .override = 0x510,
	1016	+ .security = 0x514,
	1017	+ },
	1018	+ }, {
	1019	+ .name = "nvdecsrd1",
	1020	+ .sid = TEGRA194_SID_NVDEC,
	1021	+ .regs = {
	1022	+ .override = 0x518,
	1023	+ .security = 0x51c,
	1024	+ },
	1025	+ }, {
	1026	+ .name = "miu0r",
	1027	+ .sid = TEGRA194_SID_MIU,
	1028	+ .regs = {
	1029	+ .override = 0x530,
	1030	+ .security = 0x534,
	1031	+ },
	1032	+ }, {
	1033	+ .name = "miu0w",
	1034	+ .sid = TEGRA194_SID_MIU,
	1035	+ .regs = {
	1036	+ .override = 0x538,
	1037	+ .security = 0x53c,
	1038	+ },
	1039	+ }, {
	1040	+ .name = "miu1r",
	1041	+ .sid = TEGRA194_SID_MIU,
	1042	+ .regs = {
	1043	+ .override = 0x540,
	1044	+ .security = 0x544,
	1045	+ },
	1046	+ }, {
	1047	+ .name = "miu1w",
	1048	+ .sid = TEGRA194_SID_MIU,
	1049	+ .regs = {
	1050	+ .override = 0x548,
	1051	+ .security = 0x54c,
	1052	+ },
	1053	+ }, {
	1054	+ .name = "miu2r",
	1055	+ .sid = TEGRA194_SID_MIU,
	1056	+ .regs = {
	1057	+ .override = 0x570,
	1058	+ .security = 0x574,
	1059	+ },
	1060	+ }, {
	1061	+ .name = "miu2w",
	1062	+ .sid = TEGRA194_SID_MIU,
	1063	+ .regs = {
	1064	+ .override = 0x578,
	1065	+ .security = 0x57c,
	1066	+ },
	1067	+ }, {
	1068	+ .name = "miu3r",
	1069	+ .sid = TEGRA194_SID_MIU,
	1070	+ .regs = {
	1071	+ .override = 0x580,
	1072	+ .security = 0x584,
	1073	+ },
	1074	+ }, {
	1075	+ .name = "miu3w",
	1076	+ .sid = TEGRA194_SID_MIU,
	1077	+ .regs = {
	1078	+ .override = 0x588,
	1079	+ .security = 0x58c,
	1080	+ },
	1081	+ }, {
	1082	+ .name = "miu4r",
	1083	+ .sid = TEGRA194_SID_MIU,
	1084	+ .regs = {
	1085	+ .override = 0x590,
	1086	+ .security = 0x594,
	1087	+ },
	1088	+ }, {
	1089	+ .name = "miu4w",
	1090	+ .sid = TEGRA194_SID_MIU,
	1091	+ .regs = {
	1092	+ .override = 0x598,
	1093	+ .security = 0x59c,
	1094	+ },
	1095	+ }, {
	1096	+ .name = "dpmur",
	1097	+ .sid = TEGRA194_SID_PASSTHROUGH,
	1098	+ .regs = {
	1099	+ .override = 0x598,
	1100	+ .security = 0x59c,
	1101	+ },
	1102	+ }, {
	1103	+ .name = "vifalr",
	1104	+ .sid = TEGRA194_SID_VI_FALCON,
	1105	+ .regs = {
	1106	+ .override = 0x5e0,
	1107	+ .security = 0x5e4,
	1108	+ },
	1109	+ }, {
	1110	+ .name = "vifalw",
	1111	+ .sid = TEGRA194_SID_VI_FALCON,
	1112	+ .regs = {
	1113	+ .override = 0x5e8,
	1114	+ .security = 0x5ec,
	1115	+ },
	1116	+ }, {
	1117	+ .name = "dla0rda",
	1118	+ .sid = TEGRA194_SID_NVDLA0,
	1119	+ .regs = {
	1120	+ .override = 0x5f0,
	1121	+ .security = 0x5f4,
	1122	+ },
	1123	+ }, {
	1124	+ .name = "dla0falrdb",
	1125	+ .sid = TEGRA194_SID_NVDLA0,
	1126	+ .regs = {
	1127	+ .override = 0x5f8,
	1128	+ .security = 0x5fc,
	1129	+ },
	1130	+ }, {
	1131	+ .name = "dla0wra",
	1132	+ .sid = TEGRA194_SID_NVDLA0,
	1133	+ .regs = {
	1134	+ .override = 0x600,
	1135	+ .security = 0x604,
	1136	+ },
	1137	+ }, {
	1138	+ .name = "dla0falwrb",
	1139	+ .sid = TEGRA194_SID_NVDLA0,
	1140	+ .regs = {
	1141	+ .override = 0x608,
	1142	+ .security = 0x60c,
	1143	+ },
	1144	+ }, {
	1145	+ .name = "dla1rda",
	1146	+ .sid = TEGRA194_SID_NVDLA1,
	1147	+ .regs = {
	1148	+ .override = 0x610,
	1149	+ .security = 0x614,
	1150	+ },
	1151	+ }, {
	1152	+ .name = "dla1falrdb",
	1153	+ .sid = TEGRA194_SID_NVDLA1,
	1154	+ .regs = {
	1155	+ .override = 0x618,
	1156	+ .security = 0x61c,
	1157	+ },
	1158	+ }, {
	1159	+ .name = "dla1wra",
	1160	+ .sid = TEGRA194_SID_NVDLA1,
	1161	+ .regs = {
	1162	+ .override = 0x620,
	1163	+ .security = 0x624,
	1164	+ },
	1165	+ }, {
	1166	+ .name = "dla1falwrb",
	1167	+ .sid = TEGRA194_SID_NVDLA1,
	1168	+ .regs = {
	1169	+ .override = 0x628,
	1170	+ .security = 0x62c,
	1171	+ },
	1172	+ }, {
	1173	+ .name = "pva0rda",
	1174	+ .sid = TEGRA194_SID_PVA0,
	1175	+ .regs = {
	1176	+ .override = 0x630,
	1177	+ .security = 0x634,
	1178	+ },
	1179	+ }, {
	1180	+ .name = "pva0rdb",
	1181	+ .sid = TEGRA194_SID_PVA0,
	1182	+ .regs = {
	1183	+ .override = 0x638,
	1184	+ .security = 0x63c,
	1185	+ },
	1186	+ }, {
	1187	+ .name = "pva0rdc",
	1188	+ .sid = TEGRA194_SID_PVA0,
	1189	+ .regs = {
	1190	+ .override = 0x640,
	1191	+ .security = 0x644,
	1192	+ },
	1193	+ }, {
	1194	+ .name = "pva0wra",
	1195	+ .sid = TEGRA194_SID_PVA0,
	1196	+ .regs = {
	1197	+ .override = 0x648,
	1198	+ .security = 0x64c,
	1199	+ },
	1200	+ }, {
	1201	+ .name = "pva0wrb",
	1202	+ .sid = TEGRA194_SID_PVA0,
	1203	+ .regs = {
	1204	+ .override = 0x650,
	1205	+ .security = 0x654,
	1206	+ },
	1207	+ }, {
	1208	+ .name = "pva0wrc",
	1209	+ .sid = TEGRA194_SID_PVA0,
	1210	+ .regs = {
	1211	+ .override = 0x658,
	1212	+ .security = 0x65c,
	1213	+ },
	1214	+ }, {
	1215	+ .name = "pva1rda",
	1216	+ .sid = TEGRA194_SID_PVA1,
	1217	+ .regs = {
	1218	+ .override = 0x660,
	1219	+ .security = 0x664,
	1220	+ },
	1221	+ }, {
	1222	+ .name = "pva1rdb",
	1223	+ .sid = TEGRA194_SID_PVA1,
	1224	+ .regs = {
	1225	+ .override = 0x668,
	1226	+ .security = 0x66c,
	1227	+ },
	1228	+ }, {
	1229	+ .name = "pva1rdc",
	1230	+ .sid = TEGRA194_SID_PVA1,
	1231	+ .regs = {
	1232	+ .override = 0x670,
	1233	+ .security = 0x674,
	1234	+ },
	1235	+ }, {
	1236	+ .name = "pva1wra",
	1237	+ .sid = TEGRA194_SID_PVA1,
	1238	+ .regs = {
	1239	+ .override = 0x678,
	1240	+ .security = 0x67c,
	1241	+ },
	1242	+ }, {
	1243	+ .name = "pva1wrb",
	1244	+ .sid = TEGRA194_SID_PVA1,
	1245	+ .regs = {
	1246	+ .override = 0x680,
	1247	+ .security = 0x684,
	1248	+ },
	1249	+ }, {
	1250	+ .name = "pva1wrc",
	1251	+ .sid = TEGRA194_SID_PVA1,
	1252	+ .regs = {
	1253	+ .override = 0x688,
	1254	+ .security = 0x68c,
	1255	+ },
	1256	+ }, {
	1257	+ .name = "rcer",
	1258	+ .sid = TEGRA194_SID_RCE,
	1259	+ .regs = {
	1260	+ .override = 0x690,
	1261	+ .security = 0x694,
	1262	+ },
	1263	+ }, {
	1264	+ .name = "rcew",
	1265	+ .sid = TEGRA194_SID_RCE,
	1266	+ .regs = {
	1267	+ .override = 0x698,
	1268	+ .security = 0x69c,
	1269	+ },
	1270	+ }, {
	1271	+ .name = "rcedmar",
	1272	+ .sid = TEGRA194_SID_RCE,
	1273	+ .regs = {
	1274	+ .override = 0x6a0,
	1275	+ .security = 0x6a4,
	1276	+ },
	1277	+ }, {
	1278	+ .name = "rcedmaw",
	1279	+ .sid = TEGRA194_SID_RCE,
	1280	+ .regs = {
	1281	+ .override = 0x6a8,
	1282	+ .security = 0x6ac,
	1283	+ },
	1284	+ }, {
	1285	+ .name = "nvenc1srd",
	1286	+ .sid = TEGRA194_SID_NVENC1,
	1287	+ .regs = {
	1288	+ .override = 0x6b0,
	1289	+ .security = 0x6b4,
	1290	+ },
	1291	+ }, {
	1292	+ .name = "nvenc1swr",
	1293	+ .sid = TEGRA194_SID_NVENC1,
	1294	+ .regs = {
	1295	+ .override = 0x6b8,
	1296	+ .security = 0x6bc,
	1297	+ },
	1298	+ }, {
	1299	+ .name = "pcie0r",
	1300	+ .sid = TEGRA194_SID_PCIE0,
	1301	+ .regs = {
	1302	+ .override = 0x6c0,
	1303	+ .security = 0x6c4,
	1304	+ },
	1305	+ }, {
	1306	+ .name = "pcie0w",
	1307	+ .sid = TEGRA194_SID_PCIE0,
	1308	+ .regs = {
	1309	+ .override = 0x6c8,
	1310	+ .security = 0x6cc,
	1311	+ },
	1312	+ }, {
	1313	+ .name = "pcie1r",
	1314	+ .sid = TEGRA194_SID_PCIE1,
	1315	+ .regs = {
	1316	+ .override = 0x6d0,
	1317	+ .security = 0x6d4,
	1318	+ },
	1319	+ }, {
	1320	+ .name = "pcie1w",
	1321	+ .sid = TEGRA194_SID_PCIE1,
	1322	+ .regs = {
	1323	+ .override = 0x6d8,
	1324	+ .security = 0x6dc,
	1325	+ },
	1326	+ }, {
	1327	+ .name = "pcie2ar",
	1328	+ .sid = TEGRA194_SID_PCIE2,
	1329	+ .regs = {
	1330	+ .override = 0x6e0,
	1331	+ .security = 0x6e4,
	1332	+ },
	1333	+ }, {
	1334	+ .name = "pcie2aw",
	1335	+ .sid = TEGRA194_SID_PCIE2,
	1336	+ .regs = {
	1337	+ .override = 0x6e8,
	1338	+ .security = 0x6ec,
	1339	+ },
	1340	+ }, {
	1341	+ .name = "pcie3r",
	1342	+ .sid = TEGRA194_SID_PCIE3,
	1343	+ .regs = {
	1344	+ .override = 0x6f0,
	1345	+ .security = 0x6f4,
	1346	+ },
	1347	+ }, {
	1348	+ .name = "pcie3w",
	1349	+ .sid = TEGRA194_SID_PCIE3,
	1350	+ .regs = {
	1351	+ .override = 0x6f8,
	1352	+ .security = 0x6fc,
	1353	+ },
	1354	+ }, {
	1355	+ .name = "pcie4r",
	1356	+ .sid = TEGRA194_SID_PCIE4,
	1357	+ .regs = {
	1358	+ .override = 0x700,
	1359	+ .security = 0x704,
	1360	+ },
	1361	+ }, {
	1362	+ .name = "pcie4w",
	1363	+ .sid = TEGRA194_SID_PCIE4,
	1364	+ .regs = {
	1365	+ .override = 0x708,
	1366	+ .security = 0x70c,
	1367	+ },
	1368	+ }, {
	1369	+ .name = "pcie5r",
	1370	+ .sid = TEGRA194_SID_PCIE5,
	1371	+ .regs = {
	1372	+ .override = 0x710,
	1373	+ .security = 0x714,
	1374	+ },
	1375	+ }, {
	1376	+ .name = "pcie5w",
	1377	+ .sid = TEGRA194_SID_PCIE5,
	1378	+ .regs = {
	1379	+ .override = 0x718,
	1380	+ .security = 0x71c,
	1381	+ },
	1382	+ }, {
	1383	+ .name = "ispfalw",
	1384	+ .sid = TEGRA194_SID_ISP_FALCON,
	1385	+ .regs = {
	1386	+ .override = 0x720,
	1387	+ .security = 0x724,
	1388	+ },
	1389	+ }, {
	1390	+ .name = "dla0rda1",
	1391	+ .sid = TEGRA194_SID_NVDLA0,
	1392	+ .regs = {
	1393	+ .override = 0x748,
	1394	+ .security = 0x74c,
	1395	+ },
	1396	+ }, {
	1397	+ .name = "dla1rda1",
	1398	+ .sid = TEGRA194_SID_NVDLA1,
	1399	+ .regs = {
	1400	+ .override = 0x750,
	1401	+ .security = 0x754,
	1402	+ },
	1403	+ }, {
	1404	+ .name = "pva0rda1",
	1405	+ .sid = TEGRA194_SID_PVA0,
	1406	+ .regs = {
	1407	+ .override = 0x758,
	1408	+ .security = 0x75c,
	1409	+ },
	1410	+ }, {
	1411	+ .name = "pva0rdb1",
	1412	+ .sid = TEGRA194_SID_PVA0,
	1413	+ .regs = {
	1414	+ .override = 0x760,
	1415	+ .security = 0x764,
	1416	+ },
	1417	+ }, {
	1418	+ .name = "pva1rda1",
	1419	+ .sid = TEGRA194_SID_PVA1,
	1420	+ .regs = {
	1421	+ .override = 0x768,
	1422	+ .security = 0x76c,
	1423	+ },
	1424	+ }, {
	1425	+ .name = "pva1rdb1",
	1426	+ .sid = TEGRA194_SID_PVA1,
	1427	+ .regs = {
	1428	+ .override = 0x770,
	1429	+ .security = 0x774,
	1430	+ },
	1431	+ }, {
	1432	+ .name = "pcie5r1",
	1433	+ .sid = TEGRA194_SID_PCIE5,
	1434	+ .regs = {
	1435	+ .override = 0x778,
	1436	+ .security = 0x77c,
	1437	+ },
	1438	+ }, {
	1439	+ .name = "nvencsrd1",
	1440	+ .sid = TEGRA194_SID_NVENC,
	1441	+ .regs = {
	1442	+ .override = 0x780,
	1443	+ .security = 0x784,
	1444	+ },
	1445	+ }, {
	1446	+ .name = "nvenc1srd1",
	1447	+ .sid = TEGRA194_SID_NVENC1,
	1448	+ .regs = {
	1449	+ .override = 0x788,
	1450	+ .security = 0x78c,
	1451	+ },
	1452	+ }, {
	1453	+ .name = "ispra1",
	1454	+ .sid = TEGRA194_SID_ISP,
	1455	+ .regs = {
	1456	+ .override = 0x790,
	1457	+ .security = 0x794,
	1458	+ },
	1459	+ }, {
	1460	+ .name = "pcie0r1",
	1461	+ .sid = TEGRA194_SID_PCIE0,
	1462	+ .regs = {
	1463	+ .override = 0x798,
	1464	+ .security = 0x79c,
	1465	+ },
	1466	+ }, {
	1467	+ .name = "nvdec1srd",
	1468	+ .sid = TEGRA194_SID_NVDEC1,
	1469	+ .regs = {
	1470	+ .override = 0x7c8,
	1471	+ .security = 0x7cc,
	1472	+ },
	1473	+ }, {
	1474	+ .name = "nvdec1srd1",
	1475	+ .sid = TEGRA194_SID_NVDEC1,
	1476	+ .regs = {
	1477	+ .override = 0x7d0,
	1478	+ .security = 0x7d4,
	1479	+ },
	1480	+ }, {
	1481	+ .name = "nvdec1swr",
	1482	+ .sid = TEGRA194_SID_NVDEC1,
	1483	+ .regs = {
	1484	+ .override = 0x7d8,
	1485	+ .security = 0x7dc,
	1486	+ },
	1487	+ }, {
	1488	+ .name = "miu5r",
	1489	+ .sid = TEGRA194_SID_MIU,
	1490	+ .regs = {
	1491	+ .override = 0x7e0,
	1492	+ .security = 0x7e4,
	1493	+ },
	1494	+ }, {
	1495	+ .name = "miu5w",
	1496	+ .sid = TEGRA194_SID_MIU,
	1497	+ .regs = {
	1498	+ .override = 0x7e8,
	1499	+ .security = 0x7ec,
	1500	+ },
	1501	+ }, {
	1502	+ .name = "miu6r",
	1503	+ .sid = TEGRA194_SID_MIU,
	1504	+ .regs = {
	1505	+ .override = 0x7f0,
	1506	+ .security = 0x7f4,
	1507	+ },
	1508	+ }, {
	1509	+ .name = "miu6w",
	1510	+ .sid = TEGRA194_SID_MIU,
	1511	+ .regs = {
	1512	+ .override = 0x7f8,
	1513	+ .security = 0x7fc,
	1514	+ },
	1515	+ },
	1516	+};
	1517	+
	1518	+static const struct tegra186_mc_soc tegra194_mc_soc = {
	1519	+ .num_clients = ARRAY_SIZE(tegra194_mc_clients),
	1520	+ .clients = tegra194_mc_clients,
	1521	+};
	1522	+#endif
	1523	+
538	1524	static int tegra186_mc_probe(struct platform_device *pdev)
539	1525	{
	1526	+ struct tegra186_mc *mc;
540	1527	struct resource *res;
541		- struct tegra_mc *mc;
542		- unsigned int i;
543		- int err = 0;
	1528	+ int err;
544	1529
545	1530	mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
546	1531	if (!mc)
547	1532	return -ENOMEM;
	1533	+
	1534	+ mc->soc = of_device_get_match_data(&pdev->dev);
548	1535
549	1536	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
550	1537	mc->regs = devm_ioremap_resource(&pdev->dev, res);
..	..	@@ -553,46 +1540,63 @@
553	1540
554	1541	mc->dev = &pdev->dev;
555	1542
556		- for (i = 0; i < ARRAY_SIZE(tegra186_mc_clients); i++) {
557		- const struct tegra_mc_client *client = &tegra186_mc_clients[i];
558		- u32 override, security;
559		-
560		- override = readl(mc->regs + client->regs.override);
561		- security = readl(mc->regs + client->regs.security);
562		-
563		- dev_dbg(&pdev->dev, "client %s: override: %x security: %x\n",
564		- client->name, override, security);
565		-
566		- dev_dbg(&pdev->dev, "setting SID %u for %s\n", client->sid,
567		- client->name);
568		- writel(client->sid, mc->regs + client->regs.override);
569		-
570		- override = readl(mc->regs + client->regs.override);
571		- security = readl(mc->regs + client->regs.security);
572		-
573		- dev_dbg(&pdev->dev, "client %s: override: %x security: %x\n",
574		- client->name, override, security);
575		- }
	1543	+ err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
	1544	+ if (err < 0)
	1545	+ return err;
576	1546
577	1547	platform_set_drvdata(pdev, mc);
	1548	+ tegra186_mc_program_sid(mc);
578	1549
579		- return err;
	1550	+ return 0;
	1551	+}
	1552	+
	1553	+static int tegra186_mc_remove(struct platform_device *pdev)
	1554	+{
	1555	+ struct tegra186_mc *mc = platform_get_drvdata(pdev);
	1556	+
	1557	+ of_platform_depopulate(mc->dev);
	1558	+
	1559	+ return 0;
580	1560	}
581	1561
582	1562	static const struct of_device_id tegra186_mc_of_match[] = {
583		- { .compatible = "nvidia,tegra186-mc", },
	1563	+#if defined(CONFIG_ARCH_TEGRA_186_SOC)
	1564	+ { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },
	1565	+#endif
	1566	+#if defined(CONFIG_ARCH_TEGRA_194_SOC)
	1567	+ { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc },
	1568	+#endif
584	1569	{ /* sentinel */ }
585	1570	};
586	1571	MODULE_DEVICE_TABLE(of, tegra186_mc_of_match);
	1572	+
	1573	+static int __maybe_unused tegra186_mc_suspend(struct device *dev)
	1574	+{
	1575	+ return 0;
	1576	+}
	1577	+
	1578	+static int __maybe_unused tegra186_mc_resume(struct device *dev)
	1579	+{
	1580	+ struct tegra186_mc *mc = dev_get_drvdata(dev);
	1581	+
	1582	+ tegra186_mc_program_sid(mc);
	1583	+
	1584	+ return 0;
	1585	+}
	1586	+
	1587	+static const struct dev_pm_ops tegra186_mc_pm_ops = {
	1588	+ SET_SYSTEM_SLEEP_PM_OPS(tegra186_mc_suspend, tegra186_mc_resume)
	1589	+};
587	1590
588	1591	static struct platform_driver tegra186_mc_driver = {
589	1592	.driver = {
590	1593	.name = "tegra186-mc",
591	1594	.of_match_table = tegra186_mc_of_match,
	1595	+ .pm = &tegra186_mc_pm_ops,
592	1596	.suppress_bind_attrs = true,
593	1597	},
594		- .prevent_deferred_probe = true,
595	1598	.probe = tegra186_mc_probe,
	1599	+ .remove = tegra186_mc_remove,
596	1600	};
597	1601	module_platform_driver(tegra186_mc_driver);
598	1602