~ljy/RK356X_SDK_RELEASE.git

..	..	@@ -19,11 +19,14 @@
19	19	#include <media/videobuf2-dma-sg.h>
20	20	#include <soc/rockchip/rockchip-system-status.h>
21	21	#include <dt-bindings/soc/rockchip-system-status.h>
	22	+#include <soc/rockchip/rockchip_iommu.h>
22	23
23	24	#include "dev.h"
24	25	#include "mipi-csi2.h"
	26	+#include "common.h"
	27	+#include "rkcif-externel.h"
25	28
26		-#define CIF_REQ_BUFS_MIN 3
	29	+#define CIF_REQ_BUFS_MIN 1
27	30	#define CIF_MIN_WIDTH 64
28	31	#define CIF_MIN_HEIGHT 64
29	32	#define CIF_MAX_WIDTH 8192
..	..	@@ -33,6 +36,7 @@
33	36
34	37	#define RKCIF_PLANE_Y 0
35	38	#define RKCIF_PLANE_CBCR 1
	39	+#define RKCIF_MAX_PLANE 3
36	40
37	41	#define STREAM_PAD_SINK 0
38	42	#define STREAM_PAD_SOURCE 1
..	..	@@ -146,10 +150,18 @@
146	150	.csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
147	151	.fmt_type = CIF_FMT_TYPE_RAW,
148	152	}, {
	153	+ .fourcc = V4L2_PIX_FMT_BGR24,
	154	+ .cplanes = 1,
	155	+ .mplanes = 1,
	156	+ .bpp = { 24 },
	157	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
	158	+ .fmt_type = CIF_FMT_TYPE_RAW,
	159	+ }, {
149	160	.fourcc = V4L2_PIX_FMT_RGB565,
150	161	.cplanes = 1,
151	162	.mplanes = 1,
152	163	.bpp = { 16 },
	164	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB565,
153	165	.fmt_type = CIF_FMT_TYPE_RAW,
154	166	}, {
155	167	.fourcc = V4L2_PIX_FMT_BGR666,
..	..	@@ -262,6 +274,30 @@
262	274	.csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
263	275	.fmt_type = CIF_FMT_TYPE_RAW,
264	276	}, {
	277	+ .fourcc = V4L2_PIX_FMT_SGBRG16,
	278	+ .cplanes = 1,
	279	+ .mplanes = 1,
	280	+ .bpp = { 16 },
	281	+ .raw_bpp = 16,
	282	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
	283	+ .fmt_type = CIF_FMT_TYPE_RAW,
	284	+ }, {
	285	+ .fourcc = V4L2_PIX_FMT_SGRBG16,
	286	+ .cplanes = 1,
	287	+ .mplanes = 1,
	288	+ .bpp = { 16 },
	289	+ .raw_bpp = 16,
	290	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
	291	+ .fmt_type = CIF_FMT_TYPE_RAW,
	292	+ }, {
	293	+ .fourcc = V4L2_PIX_FMT_SRGGB16,
	294	+ .cplanes = 1,
	295	+ .mplanes = 1,
	296	+ .bpp = { 16 },
	297	+ .raw_bpp = 16,
	298	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
	299	+ .fmt_type = CIF_FMT_TYPE_RAW,
	300	+ }, {
265	301	.fourcc = V4L2_PIX_FMT_Y16,
266	302	.cplanes = 1,
267	303	.mplanes = 1,
..	..	@@ -293,8 +329,51 @@
293	329	.raw_bpp = 16,
294	330	.csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
295	331	.fmt_type = CIF_FMT_TYPE_RAW,
	332	+ }, {
	333	+ .fourcc = V4L2_PIX_FMT_Y12,
	334	+ .cplanes = 1,
	335	+ .mplanes = 1,
	336	+ .bpp = { 16 },
	337	+ .raw_bpp = 12,
	338	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
	339	+ .fmt_type = CIF_FMT_TYPE_RAW,
	340	+ }, {
	341	+ .fourcc = V4L2_PIX_FMT_Y10,
	342	+ .cplanes = 1,
	343	+ .mplanes = 1,
	344	+ .bpp = { 16 },
	345	+ .raw_bpp = 10,
	346	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
	347	+ .fmt_type = CIF_FMT_TYPE_RAW,
	348	+ }, {
	349	+ .fourcc = V4L2_PIX_FMT_SRGGB16,
	350	+ .cplanes = 1,
	351	+ .mplanes = 1,
	352	+ .bpp = { 16 },
	353	+ .raw_bpp = 16,
	354	+ .fmt_type = CIF_FMT_TYPE_RAW,
	355	+ }, {
	356	+ .fourcc = V4L2_PIX_FMT_SGRBG16,
	357	+ .cplanes = 1,
	358	+ .mplanes = 1,
	359	+ .bpp = { 16 },
	360	+ .raw_bpp = 16,
	361	+ .fmt_type = CIF_FMT_TYPE_RAW,
	362	+ }, {
	363	+ .fourcc = V4L2_PIX_FMT_SGBRG16,
	364	+ .cplanes = 1,
	365	+ .mplanes = 1,
	366	+ .bpp = { 16 },
	367	+ .raw_bpp = 16,
	368	+ .fmt_type = CIF_FMT_TYPE_RAW,
	369	+ }, {
	370	+ .fourcc = V4L2_PIX_FMT_SBGGR16,
	371	+ .cplanes = 1,
	372	+ .mplanes = 1,
	373	+ .bpp = { 16 },
	374	+ .raw_bpp = 16,
	375	+ .fmt_type = CIF_FMT_TYPE_RAW,
296	376	}
297		-
298	377	/* TODO: We can support NV12M/NV21M/NV16M/NV61M too */
299	378	};
300	379
..	..	@@ -432,6 +511,14 @@
432	511	.csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
433	512	.field = V4L2_FIELD_NONE,
434	513	}, {
	514	+ .mbus_code = MEDIA_BUS_FMT_BGR888_1X24,
	515	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
	516	+ .field = V4L2_FIELD_NONE,
	517	+ }, {
	518	+ .mbus_code = MEDIA_BUS_FMT_RGB565_1X16,
	519	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB565,
	520	+ .field = V4L2_FIELD_NONE,
	521	+ }, {
435	522	.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
436	523	.dvp_fmt_val = INPUT_MODE_RAW \| RAW_DATA_WIDTH_8,
437	524	.csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
..	..	@@ -463,6 +550,143 @@
463	550	.field = V4L2_FIELD_NONE,
464	551	}
465	552	};
	553	+
	554	+static int rkcif_output_fmt_check(struct rkcif_stream *stream,
	555	+ const struct cif_output_fmt *output_fmt)
	556	+{
	557	+ const struct cif_input_fmt *input_fmt = stream->cif_fmt_in;
	558	+ struct csi_channel_info *channel = &stream->cifdev->channels[stream->id];
	559	+ int ret = -EINVAL;
	560	+
	561	+ switch (input_fmt->mbus_code) {
	562	+ case MEDIA_BUS_FMT_YUYV8_2X8:
	563	+ case MEDIA_BUS_FMT_YVYU8_2X8:
	564	+ case MEDIA_BUS_FMT_UYVY8_2X8:
	565	+ case MEDIA_BUS_FMT_VYUY8_2X8:
	566	+ if (output_fmt->fourcc == V4L2_PIX_FMT_NV16 \|\|
	567	+ output_fmt->fourcc == V4L2_PIX_FMT_NV61 \|\|
	568	+ output_fmt->fourcc == V4L2_PIX_FMT_NV12 \|\|
	569	+ output_fmt->fourcc == V4L2_PIX_FMT_NV21 \|\|
	570	+ output_fmt->fourcc == V4L2_PIX_FMT_YUYV \|\|
	571	+ output_fmt->fourcc == V4L2_PIX_FMT_YVYU \|\|
	572	+ output_fmt->fourcc == V4L2_PIX_FMT_UYVY \|\|
	573	+ output_fmt->fourcc == V4L2_PIX_FMT_VYUY)
	574	+ ret = 0;
	575	+ break;
	576	+ case MEDIA_BUS_FMT_SBGGR8_1X8:
	577	+ case MEDIA_BUS_FMT_SGBRG8_1X8:
	578	+ case MEDIA_BUS_FMT_SGRBG8_1X8:
	579	+ case MEDIA_BUS_FMT_SRGGB8_1X8:
	580	+ case MEDIA_BUS_FMT_Y8_1X8:
	581	+ if (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
	582	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
	583	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
	584	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR8 \|\|
	585	+ output_fmt->fourcc == V4L2_PIX_FMT_GREY)
	586	+ ret = 0;
	587	+ break;
	588	+ case MEDIA_BUS_FMT_SBGGR10_1X10:
	589	+ case MEDIA_BUS_FMT_SGBRG10_1X10:
	590	+ case MEDIA_BUS_FMT_SGRBG10_1X10:
	591	+ case MEDIA_BUS_FMT_SRGGB10_1X10:
	592	+ case MEDIA_BUS_FMT_Y10_1X10:
	593	+ if (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB10 \|\|
	594	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG10 \|\|
	595	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG10 \|\|
	596	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR10 \|\|
	597	+ output_fmt->fourcc == V4L2_PIX_FMT_Y10)
	598	+ ret = 0;
	599	+ break;
	600	+ case MEDIA_BUS_FMT_SBGGR12_1X12:
	601	+ case MEDIA_BUS_FMT_SGBRG12_1X12:
	602	+ case MEDIA_BUS_FMT_SGRBG12_1X12:
	603	+ case MEDIA_BUS_FMT_SRGGB12_1X12:
	604	+ case MEDIA_BUS_FMT_Y12_1X12:
	605	+ if (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB12 \|\|
	606	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG12 \|\|
	607	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG12 \|\|
	608	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR12 \|\|
	609	+ output_fmt->fourcc == V4L2_PIX_FMT_Y12)
	610	+ ret = 0;
	611	+ break;
	612	+ case MEDIA_BUS_FMT_RGB888_1X24:
	613	+ case MEDIA_BUS_FMT_BGR888_1X24:
	614	+ if (output_fmt->fourcc == V4L2_PIX_FMT_RGB24 \|\|
	615	+ output_fmt->fourcc == V4L2_PIX_FMT_BGR24)
	616	+ ret = 0;
	617	+ break;
	618	+ case MEDIA_BUS_FMT_RGB565_1X16:
	619	+ if (output_fmt->fourcc == V4L2_PIX_FMT_RGB565)
	620	+ ret = 0;
	621	+ break;
	622	+ case MEDIA_BUS_FMT_EBD_1X8:
	623	+ if (output_fmt->fourcc == V4l2_PIX_FMT_EBD8 \|\|
	624	+ (channel->data_bit == 8 &&
	625	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
	626	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
	627	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
	628	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR8)) \|\|
	629	+ (channel->data_bit == 10 &&
	630	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB10 \|\|
	631	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG10 \|\|
	632	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG10 \|\|
	633	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR10)) \|\|
	634	+ (channel->data_bit == 12 &&
	635	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB12 \|\|
	636	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG12 \|\|
	637	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG12 \|\|
	638	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR12)) \|\|
	639	+ (channel->data_bit == 16 &&
	640	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB16 \|\|
	641	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG16 \|\|
	642	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG16 \|\|
	643	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR16)))
	644	+ ret = 0;
	645	+ break;
	646	+ case MEDIA_BUS_FMT_SPD_2X8:
	647	+ if (output_fmt->fourcc == V4l2_PIX_FMT_SPD16 \|\|
	648	+ (channel->data_bit == 8 &&
	649	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
	650	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
	651	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
	652	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR8)) \|\|
	653	+ (channel->data_bit == 10 &&
	654	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB10 \|\|
	655	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG10 \|\|
	656	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG10 \|\|
	657	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR10)) \|\|
	658	+ (channel->data_bit == 12 &&
	659	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB12 \|\|
	660	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG12 \|\|
	661	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG12 \|\|
	662	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR12)) \|\|
	663	+ (channel->data_bit == 16 &&
	664	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB16 \|\|
	665	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG16 \|\|
	666	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG16 \|\|
	667	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR16)))
	668	+ ret = 0;
	669	+ break;
	670	+ default:
	671	+ break;
	672	+ }
	673	+ if (ret)
	674	+ v4l2_err(&stream->cifdev->v4l2_dev,
	675	+ "input mbus_code 0x%x, can't transform to %c%c%c%c\n",
	676	+ input_fmt->mbus_code,
	677	+ output_fmt->fourcc & 0xff,
	678	+ (output_fmt->fourcc >> 8) & 0xff,
	679	+ (output_fmt->fourcc >> 16) & 0xff,
	680	+ (output_fmt->fourcc >> 24) & 0xff);
	681	+ return ret;
	682	+}
	683	+
	684	+static int rkcif_stop_dma_capture(struct rkcif_stream *stream);
	685	+
	686	+struct rkcif_rx_buffer to_cif_rx_buf(struct rkisp_rx_buf dbufs)
	687	+{
	688	+ return container_of(dbufs, struct rkcif_rx_buffer, dbufs);
	689	+}
466	690
467	691	static struct v4l2_subdev get_remote_sensor(struct rkcif_stream stream, u16 *index)
468	692	{
..	..	@@ -553,18 +777,21 @@
553	777	case MEDIA_BUS_FMT_SGBRG8_1X8:
554	778	case MEDIA_BUS_FMT_SGRBG8_1X8:
555	779	case MEDIA_BUS_FMT_SRGGB8_1X8:
	780	+ case MEDIA_BUS_FMT_Y8_1X8:
556	781	return 0x2a;
557	782	/* csi raw10 */
558	783	case MEDIA_BUS_FMT_SBGGR10_1X10:
559	784	case MEDIA_BUS_FMT_SGBRG10_1X10:
560	785	case MEDIA_BUS_FMT_SGRBG10_1X10:
561	786	case MEDIA_BUS_FMT_SRGGB10_1X10:
	787	+ case MEDIA_BUS_FMT_Y10_1X10:
562	788	return 0x2b;
563	789	/* csi raw12 */
564	790	case MEDIA_BUS_FMT_SBGGR12_1X12:
565	791	case MEDIA_BUS_FMT_SGBRG12_1X12:
566	792	case MEDIA_BUS_FMT_SGRBG12_1X12:
567	793	case MEDIA_BUS_FMT_SRGGB12_1X12:
	794	+ case MEDIA_BUS_FMT_Y12_1X12:
568	795	return 0x2c;
569	796	/* csi uyvy 422 */
570	797	case MEDIA_BUS_FMT_UYVY8_2X8:
..	..	@@ -572,7 +799,8 @@
572	799	case MEDIA_BUS_FMT_YUYV8_2X8:
573	800	case MEDIA_BUS_FMT_YVYU8_2X8:
574	801	return 0x1e;
575		- case MEDIA_BUS_FMT_RGB888_1X24: {
	802	+ case MEDIA_BUS_FMT_RGB888_1X24:
	803	+ case MEDIA_BUS_FMT_BGR888_1X24:
576	804	if (dsi_input) {
577	805	if (cmd_mode_en) /* dsi command mode*/
578	806	return 0x39;
..	..	@@ -581,7 +809,15 @@
581	809	} else {
582	810	return 0x24;
583	811	}
584		- }
	812	+ case MEDIA_BUS_FMT_RGB565_1X16:
	813	+ if (dsi_input) {
	814	+ if (cmd_mode_en) /* dsi command mode*/
	815	+ return 0x39;
	816	+ else /* dsi video mode */
	817	+ return 0x0e;
	818	+ } else {
	819	+ return 0x22;
	820	+ }
585	821	case MEDIA_BUS_FMT_EBD_1X8:
586	822	return 0x12;
587	823	case MEDIA_BUS_FMT_SPD_2X8:
..	..	@@ -597,6 +833,8 @@
597	833	switch (fmt_in->csi_fmt_val) {
598	834	case CSI_WRDDR_TYPE_RGB888:
599	835	return 24;
	836	+ case CSI_WRDDR_TYPE_RGB565:
	837	+ return 16;
600	838	case CSI_WRDDR_TYPE_RAW10:
601	839	case CSI_WRDDR_TYPE_RAW12:
602	840	return 4;
..	..	@@ -608,51 +846,59 @@
608	846	}
609	847	}
610	848
611		-static const struct
	849	+const struct
612	850	cif_input_fmt get_input_fmt(struct v4l2_subdev sd, struct v4l2_rect *rect,
613		- u32 pad, int *vc)
	851	+ u32 pad_id, struct csi_channel_info *csi_info)
614	852	{
615	853	struct v4l2_subdev_format fmt;
	854	+ struct rkmodule_channel_info ch_info = {0};
616	855	int ret;
617	856	u32 i;
618		- struct rkmodule_vc_fmt_info vc_info = {0};
619	857
620		- ret = v4l2_subdev_call(sd,
621		- core, ioctl,
622		- RKMODULE_GET_VC_FMT_INFO,
623		- &vc_info);
624		- if (ret < 0)
625		- v4l2_warn(sd->v4l2_dev,
626		- "get sensor vc info failed, maybe not support\n");
627		-
628		- fmt.pad = pad;
	858	+ fmt.pad = 0;
629	859	fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
630	860	fmt.reserved[0] = 0;
	861	+ fmt.format.field = V4L2_FIELD_NONE;
631	862	ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
632	863	if (ret < 0) {
633	864	v4l2_warn(sd->v4l2_dev,
634	865	"sensor fmt invalid, set to default size\n");
635	866	goto set_default;
636	867	}
637		-
638		- /* v4l2_subdev_format reserved[0]
639		- * using as mipi virtual channel
640		- */
641		- switch (fmt.reserved[0]) {
642		- case V4L2_MBUS_CSI2_CHANNEL_3:
643		- *vc = 3;
644		- break;
645		- case V4L2_MBUS_CSI2_CHANNEL_2:
646		- *vc = 2;
647		- break;
648		- case V4L2_MBUS_CSI2_CHANNEL_1:
649		- *vc = 1;
650		- break;
651		- case V4L2_MBUS_CSI2_CHANNEL_0:
652		- *vc = 0;
653		- break;
654		- default:
655		- *vc = -1;
	868	+ ch_info.index = pad_id;
	869	+ ret = v4l2_subdev_call(sd,
	870	+ core, ioctl,
	871	+ RKMODULE_GET_CHANNEL_INFO,
	872	+ &ch_info);
	873	+ if (!ret) {
	874	+ fmt.format.width = ch_info.width;
	875	+ fmt.format.height = ch_info.height;
	876	+ fmt.format.code = ch_info.bus_fmt;
	877	+ switch (ch_info.vc) {
	878	+ case V4L2_MBUS_CSI2_CHANNEL_3:
	879	+ csi_info->vc = 3;
	880	+ break;
	881	+ case V4L2_MBUS_CSI2_CHANNEL_2:
	882	+ csi_info->vc = 2;
	883	+ break;
	884	+ case V4L2_MBUS_CSI2_CHANNEL_1:
	885	+ csi_info->vc = 1;
	886	+ break;
	887	+ case V4L2_MBUS_CSI2_CHANNEL_0:
	888	+ csi_info->vc = 0;
	889	+ break;
	890	+ default:
	891	+ csi_info->vc = 0xff;
	892	+ }
	893	+ if (ch_info.bus_fmt == MEDIA_BUS_FMT_SPD_2X8 \|\|
	894	+ ch_info.bus_fmt == MEDIA_BUS_FMT_EBD_1X8) {
	895	+ if (ch_info.data_type > 0)
	896	+ csi_info->data_type = ch_info.data_type;
	897	+ if (ch_info.data_bit > 0)
	898	+ csi_info->data_bit = ch_info.data_bit;
	899	+ }
	900	+ } else {
	901	+ csi_info->vc = 0xff;
656	902	}
657	903
658	904	v4l2_dbg(1, rkcif_debug, sd->v4l2_dev,
..	..	@@ -680,8 +926,8 @@
680	926	return NULL;
681	927	}
682	928
683		-static const struct
684		-cif_output_fmt find_output_fmt(struct rkcif_stream stream, u32 pixelfmt)
	929	+const struct
	930	+cif_output_fmt rkcif_find_output_fmt(struct rkcif_stream stream, u32 pixelfmt)
685	931	{
686	932	const struct cif_output_fmt *fmt;
687	933	u32 i;
..	..	@@ -714,6 +960,31 @@
714	960	break;
715	961	default:
716	962	index = CIF_REG_MIPI_LVDS_ID0_CTRL0;
	963	+ break;
	964	+ }
	965	+
	966	+ return index;
	967	+}
	968	+
	969	+static enum cif_reg_index get_reg_index_of_lvds_id_ctrl0(int channel_id)
	970	+{
	971	+ enum cif_reg_index index;
	972	+
	973	+ switch (channel_id) {
	974	+ case 0:
	975	+ index = CIF_REG_LVDS_ID0_CTRL0;
	976	+ break;
	977	+ case 1:
	978	+ index = CIF_REG_LVDS_ID1_CTRL0;
	979	+ break;
	980	+ case 2:
	981	+ index = CIF_REG_LVDS_ID2_CTRL0;
	982	+ break;
	983	+ case 3:
	984	+ index = CIF_REG_LVDS_ID3_CTRL0;
	985	+ break;
	986	+ default:
	987	+ index = CIF_REG_LVDS_ID0_CTRL0;
717	988	break;
718	989	}
719	990
..	..	@@ -1170,12 +1441,50 @@
1170	1441	return index;
1171	1442	}
1172	1443
	1444	+int rkcif_get_linetime(struct rkcif_stream *stream)
	1445	+{
	1446	+ struct rkcif_device *cif_dev = stream->cifdev;
	1447	+ struct rkcif_sensor_info *sensor = &cif_dev->terminal_sensor;
	1448	+ u32 numerator, denominator;
	1449	+ u32 def_fps = 0;
	1450	+ int line_time = 0;
	1451	+ int vblank_def = 0;
	1452	+ int vblank_curr = 0;
	1453	+
	1454	+ numerator = sensor->fi.interval.numerator;
	1455	+ denominator = sensor->fi.interval.denominator;
	1456	+ if (!numerator \|\| !denominator) {
	1457	+ v4l2_err(&cif_dev->v4l2_dev,
	1458	+ "get frame interval fail, numerator %d, denominator %d\n",
	1459	+ numerator, denominator);
	1460	+ return -EINVAL;
	1461	+ }
	1462	+ def_fps = denominator / numerator;
	1463	+ if (!def_fps) {
	1464	+ v4l2_err(&cif_dev->v4l2_dev,
	1465	+ "get fps fail, numerator %d, denominator %d\n",
	1466	+ numerator, denominator);
	1467	+ return -EINVAL;
	1468	+ }
	1469	+ vblank_def = rkcif_get_sensor_vblank_def(cif_dev);
	1470	+ vblank_curr = rkcif_get_sensor_vblank(cif_dev);
	1471	+ if (!vblank_def \|\| !vblank_curr) {
	1472	+ v4l2_err(&cif_dev->v4l2_dev,
	1473	+ "get vblank fail, vblank_def %d, vblank_curr %d\n",
	1474	+ vblank_def, vblank_curr);
	1475	+ return -EINVAL;
	1476	+ }
	1477	+ line_time = div_u64(1000000000, def_fps);
	1478	+ line_time = div_u64(line_time, vblank_def + sensor->raw_rect.height);
	1479	+ return line_time;
	1480	+}
	1481	+
1173	1482	/*************************** stream operations ****************************/
1174	1483	static int rkcif_assign_new_buffer_oneframe(struct rkcif_stream *stream,
1175		- enum rkcif_yuvaddr_state stat)
	1484	+ enum rkcif_yuvaddr_state stat)
1176	1485	{
1177	1486	struct rkcif_device *dev = stream->cifdev;
1178		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	1487	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1179	1488	struct rkcif_buffer *buffer = NULL;
1180	1489	u32 frm_addr_y = CIF_REG_DVP_FRM0_ADDR_Y;
1181	1490	u32 frm_addr_uv = CIF_REG_DVP_FRM0_ADDR_UV;
..	..	@@ -1270,12 +1579,580 @@
1270	1579	} else {
1271	1580	ret = -EINVAL;
1272	1581	}
1273		- v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
1274		- "not active buffer, frame Drop\n");
	1582	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	1583	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
1275	1584	}
1276	1585	}
1277	1586	spin_unlock_irqrestore(&stream->vbq_lock, flags);
1278	1587	return ret;
	1588	+}
	1589	+
	1590	+static void rkcif_rx_buffer_free(struct rkcif_stream *stream)
	1591	+{
	1592	+ struct media_pad *pad = NULL;
	1593	+ struct v4l2_subdev *sd;
	1594	+ struct rkisp_rx_buf *dbufs;
	1595	+ struct rkcif_device *dev = stream->cifdev;
	1596	+
	1597	+ if (dev->sditf[0] && dev->sditf[0]->num_sensors != 0) {
	1598	+ if (dev->sditf[0]->is_combine_mode)
	1599	+ pad = media_entity_remote_pad(&dev->sditf[0]->pads[1]);
	1600	+ else
	1601	+ pad = media_entity_remote_pad(&dev->sditf[0]->pads[0]);
	1602	+ } else {
	1603	+ return;
	1604	+ }
	1605	+
	1606	+ if (pad)
	1607	+ sd = media_entity_to_v4l2_subdev(pad->entity);
	1608	+ else
	1609	+ return;
	1610	+
	1611	+ while (!list_empty(&stream->rx_buf_head_vicap)) {
	1612	+ dbufs = list_first_entry(&stream->rx_buf_head_vicap, struct rkisp_rx_buf, list);
	1613	+ if (dbufs->is_init)
	1614	+ v4l2_subdev_call(sd, core, ioctl,
	1615	+ RKISP_VICAP_CMD_RX_BUFFER_FREE, dbufs);
	1616	+ dma_buf_put(dbufs->dbuf);
	1617	+ list_del(&dbufs->list);
	1618	+ kfree(dbufs);
	1619	+ }
	1620	+}
	1621	+
	1622	+static void rkcif_s_rx_buffer(struct rkcif_device dev, struct rkisp_rx_buf dbufs)
	1623	+{
	1624	+ struct media_pad *pad = NULL;
	1625	+ struct v4l2_subdev *sd;
	1626	+ struct rkcif_rx_buffer *rx_buf = NULL;
	1627	+
	1628	+ if (dev->sditf[0]) {
	1629	+ if (dev->sditf[0]->is_combine_mode)
	1630	+ pad = media_entity_remote_pad(&dev->sditf[0]->pads[1]);
	1631	+ else
	1632	+ pad = media_entity_remote_pad(&dev->sditf[0]->pads[0]);
	1633	+ } else {
	1634	+ return;
	1635	+ }
	1636	+ if (pad)
	1637	+ sd = media_entity_to_v4l2_subdev(pad->entity);
	1638	+ else
	1639	+ return;
	1640	+ if (dev->rdbk_debug &&
	1641	+ dbufs->sequence < 15) {
	1642	+ rx_buf = to_cif_rx_buf(dbufs);
	1643	+ v4l2_info(&dev->v4l2_dev,
	1644	+ "s_buf seq %d type %d, dma addr %x, %lld\n",
	1645	+ dbufs->sequence, dbufs->type, (u32)rx_buf->dummy.dma_addr,
	1646	+ ktime_get_ns());
	1647	+ }
	1648	+ v4l2_subdev_call(sd, video, s_rx_buffer, dbufs, NULL);
	1649	+}
	1650	+
	1651	+static void rkcif_enable_skip_frame(struct rkcif_stream *stream, int cap_m, int skip_n)
	1652	+{
	1653	+ struct rkcif_device *dev = stream->cifdev;
	1654	+ u32 val = 0;
	1655	+
	1656	+ val = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_CTRL);
	1657	+ val &= 0xc00fffff;
	1658	+ val \|= cap_m << RKCIF_CAP_SHIFT \| skip_n << RKCIF_SKIP_SHIFT \| RKCIF_SKIP_EN(stream->id);
	1659	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
	1660	+ stream->skip_info.skip_en = true;
	1661	+}
	1662	+
	1663	+static void rkcif_disable_skip_frame(struct rkcif_stream *stream)
	1664	+{ struct rkcif_device *dev = stream->cifdev;
	1665	+ u32 val = 0;
	1666	+
	1667	+ val = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_CTRL);
	1668	+ val &= ~(RKCIF_SKIP_EN(stream->id));
	1669	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
	1670	+ stream->skip_info.skip_en = false;
	1671	+}
	1672	+
	1673	+static void rkcif_rdbk_frame_end_toisp(struct rkcif_stream *stream,
	1674	+ struct rkcif_rx_buffer *buffer)
	1675	+{
	1676	+ struct rkcif_device *dev = stream->cifdev;
	1677	+ struct rkcif_sensor_info *sensor = &stream->cifdev->terminal_sensor;
	1678	+ u32 denominator, numerator;
	1679	+ u64 l_ts, m_ts, s_ts, time = 30000000LL;
	1680	+ int ret, fps = -1;
	1681	+ unsigned long flags;
	1682	+
	1683	+ spin_lock_irqsave(&dev->hdr_lock, flags);
	1684	+ if (dev->rdbk_rx_buf[stream->id]) {
	1685	+ list_add_tail(&dev->rdbk_rx_buf[stream->id]->list, &stream->rx_buf_head);
	1686	+ dev->rdbk_rx_buf[stream->id] = buffer;
	1687	+ } else {
	1688	+ dev->rdbk_rx_buf[stream->id] = buffer;
	1689	+ }
	1690	+
	1691	+ numerator = sensor->fi.interval.numerator;
	1692	+ denominator = sensor->fi.interval.denominator;
	1693	+ if (denominator && numerator)
	1694	+ time = numerator * 1000 / denominator * 1000 * 1000;
	1695	+
	1696	+ if (dev->hdr.hdr_mode == HDR_X3 &&
	1697	+ dev->rdbk_rx_buf[RDBK_L] &&
	1698	+ dev->rdbk_rx_buf[RDBK_M] &&
	1699	+ dev->rdbk_rx_buf[RDBK_S]) {
	1700	+ l_ts = dev->rdbk_rx_buf[RDBK_L]->fe_timestamp;
	1701	+ m_ts = dev->rdbk_rx_buf[RDBK_M]->fe_timestamp;
	1702	+ s_ts = dev->rdbk_rx_buf[RDBK_S]->fe_timestamp;
	1703	+
	1704	+ if (m_ts < l_ts \|\| s_ts < m_ts) {
	1705	+ v4l2_err(&dev->v4l2_dev,
	1706	+ "s/m/l frame err, timestamp s:%lld m:%lld l:%lld\n",
	1707	+ s_ts, m_ts, l_ts);
	1708	+ goto RDBK_TOISP_UNMATCH;
	1709	+ }
	1710	+
	1711	+ if ((m_ts - l_ts) > time \|\| (s_ts - m_ts) > time) {
	1712	+ ret = v4l2_subdev_call(sensor->sd,
	1713	+ video,
	1714	+ g_frame_interval,
	1715	+ &sensor->fi);
	1716	+ if (!ret) {
	1717	+ denominator = sensor->fi.interval.denominator;
	1718	+ numerator = sensor->fi.interval.numerator;
	1719	+ if (denominator && numerator) {
	1720	+ time = numerator * 1000 / denominator * 1000 * 1000;
	1721	+ fps = denominator / numerator;
	1722	+ }
	1723	+ }
	1724	+
	1725	+ if ((m_ts - l_ts) > time \|\| (s_ts - m_ts) > time) {
	1726	+ v4l2_err(&dev->v4l2_dev,
	1727	+ "timestamp no match, s:%lld m:%lld l:%lld, fps:%d\n",
	1728	+ s_ts, m_ts, l_ts, fps);
	1729	+ goto RDBK_TOISP_UNMATCH;
	1730	+ }
	1731	+ }
	1732	+ dev->rdbk_rx_buf[RDBK_M]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
	1733	+ dev->rdbk_rx_buf[RDBK_S]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
	1734	+ rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_L]->dbufs);
	1735	+ rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_M]->dbufs);
	1736	+ rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_S]->dbufs);
	1737	+ dev->rdbk_rx_buf[RDBK_L] = NULL;
	1738	+ dev->rdbk_rx_buf[RDBK_M] = NULL;
	1739	+ dev->rdbk_rx_buf[RDBK_S] = NULL;
	1740	+ } else if (dev->hdr.hdr_mode == HDR_X2 &&
	1741	+ dev->rdbk_rx_buf[RDBK_L] && dev->rdbk_rx_buf[RDBK_M]) {
	1742	+ l_ts = dev->rdbk_rx_buf[RDBK_L]->fe_timestamp;
	1743	+ s_ts = dev->rdbk_rx_buf[RDBK_M]->fe_timestamp;
	1744	+
	1745	+ if (s_ts < l_ts) {
	1746	+ v4l2_err(&dev->v4l2_dev,
	1747	+ "s/l frame err, timestamp s:%lld l:%lld\n",
	1748	+ s_ts, l_ts);
	1749	+ goto RDBK_TOISP_UNMATCH;
	1750	+ }
	1751	+
	1752	+ if ((s_ts - l_ts) > time) {
	1753	+ ret = v4l2_subdev_call(sensor->sd,
	1754	+ video,
	1755	+ g_frame_interval,
	1756	+ &sensor->fi);
	1757	+ if (!ret) {
	1758	+ denominator = sensor->fi.interval.denominator;
	1759	+ numerator = sensor->fi.interval.numerator;
	1760	+ if (denominator && numerator) {
	1761	+ time = numerator * 1000 / denominator * 1000 * 1000;
	1762	+ fps = denominator / numerator;
	1763	+ }
	1764	+ }
	1765	+ if ((s_ts - l_ts) > time) {
	1766	+ v4l2_err(&dev->v4l2_dev,
	1767	+ "timestamp no match, s:%lld l:%lld, fps:%d\n",
	1768	+ s_ts, l_ts, fps);
	1769	+ goto RDBK_TOISP_UNMATCH;
	1770	+ }
	1771	+ }
	1772	+ dev->rdbk_rx_buf[RDBK_M]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
	1773	+ rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_L]->dbufs);
	1774	+ rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_M]->dbufs);
	1775	+ dev->rdbk_rx_buf[RDBK_L] = NULL;
	1776	+ dev->rdbk_rx_buf[RDBK_M] = NULL;
	1777	+ }
	1778	+
	1779	+ spin_unlock_irqrestore(&dev->hdr_lock, flags);
	1780	+ return;
	1781	+
	1782	+RDBK_TOISP_UNMATCH:
	1783	+ spin_unlock_irqrestore(&dev->hdr_lock, flags);
	1784	+}
	1785	+
	1786	+static void rkcif_assign_new_buffer_init_toisp(struct rkcif_stream *stream,
	1787	+ int channel_id)
	1788	+{
	1789	+ struct rkcif_device *dev = stream->cifdev;
	1790	+ struct rkcif_rx_buffer *rx_buf;
	1791	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	1792	+ u32 frm0_addr_y;
	1793	+ u32 frm1_addr_y;
	1794	+ unsigned long flags;
	1795	+
	1796	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	1797	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	1798	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	1799	+ frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
	1800	+ frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
	1801	+ } else {
	1802	+ frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
	1803	+ frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
	1804	+ }
	1805	+
	1806	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	1807	+
	1808	+ if (!stream->curr_buf_toisp) {
	1809	+ if (!list_empty(&stream->rx_buf_head)) {
	1810	+ rx_buf = list_first_entry(&stream->rx_buf_head,
	1811	+ struct rkcif_rx_buffer,
	1812	+ list);
	1813	+ if (rx_buf) {
	1814	+ list_del(&rx_buf->list);
	1815	+ stream->curr_buf_toisp = rx_buf;
	1816	+ }
	1817	+ }
	1818	+ }
	1819	+
	1820	+ if (stream->curr_buf_toisp)
	1821	+ rkcif_write_register(dev, frm0_addr_y,
	1822	+ stream->curr_buf_toisp->dummy.dma_addr);
	1823	+
	1824	+ if (!stream->next_buf_toisp) {
	1825	+ if (!list_empty(&stream->rx_buf_head)) {
	1826	+ rx_buf = list_first_entry(&stream->rx_buf_head,
	1827	+ struct rkcif_rx_buffer, list);
	1828	+ if (rx_buf) {
	1829	+ list_del(&rx_buf->list);
	1830	+ stream->next_buf_toisp = rx_buf;
	1831	+ } else {
	1832	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	1833	+ }
	1834	+ } else {
	1835	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	1836	+ }
	1837	+ }
	1838	+
	1839	+ if (stream->next_buf_toisp)
	1840	+ rkcif_write_register(dev, frm1_addr_y,
	1841	+ stream->next_buf_toisp->dummy.dma_addr);
	1842	+
	1843	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	1844	+ stream->buf_owner = RKCIF_DMAEN_BY_ISP;
	1845	+}
	1846	+
	1847	+static int rkcif_assign_new_buffer_update_toisp(struct rkcif_stream *stream,
	1848	+ int channel_id)
	1849	+{
	1850	+ struct rkcif_device *dev = stream->cifdev;
	1851	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	1852	+ struct rkcif_rx_buffer *buffer = NULL;
	1853	+ struct rkcif_rx_buffer *active_buf = NULL;
	1854	+ struct sditf_priv *priv = dev->sditf[0];
	1855	+ u32 frm_addr_y;
	1856	+ unsigned long flags;
	1857	+
	1858	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	1859	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	1860	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	1861	+ frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	1862	+ get_reg_index_of_frm0_y_addr(channel_id) :
	1863	+ get_reg_index_of_frm1_y_addr(channel_id);
	1864	+ } else {
	1865	+ frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	1866	+ get_dvp_reg_index_of_frm0_y_addr(channel_id) :
	1867	+ get_dvp_reg_index_of_frm1_y_addr(channel_id);
	1868	+ }
	1869	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	1870	+ if (!list_empty(&stream->rx_buf_head)) {
	1871	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	1872	+ if (stream->curr_buf_toisp == stream->next_buf_toisp)
	1873	+ active_buf = NULL;
	1874	+ else
	1875	+ active_buf = stream->curr_buf_toisp;
	1876	+
	1877	+ buffer = list_first_entry(&stream->rx_buf_head,
	1878	+ struct rkcif_rx_buffer, list);
	1879	+ if (buffer) {
	1880	+ list_del(&buffer->list);
	1881	+ stream->curr_buf_toisp = buffer;
	1882	+ }
	1883	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
	1884	+ if (!active_buf)
	1885	+ goto out_get_buf;
	1886	+ if (stream->frame_idx == 1)
	1887	+ active_buf->dbufs.is_first = true;
	1888	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	1889	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	1890	+ active_buf->fe_timestamp = ktime_get_ns();
	1891	+ stream->last_frame_idx = stream->frame_idx;
	1892	+ if (dev->hdr.hdr_mode == NO_HDR)
	1893	+ rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	1894	+ else
	1895	+ rkcif_rdbk_frame_end_toisp(stream, active_buf);
	1896	+ stream->buf_num_toisp--;
	1897	+ } else {
	1898	+ rkcif_s_rx_buffer(dev, &stream->next_buf_toisp->dbufs);
	1899	+ stream->buf_num_toisp--;
	1900	+ }
	1901	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	1902	+ if (stream->curr_buf_toisp == stream->next_buf_toisp)
	1903	+ active_buf = NULL;
	1904	+ else
	1905	+ active_buf = stream->next_buf_toisp;
	1906	+ buffer = list_first_entry(&stream->rx_buf_head,
	1907	+ struct rkcif_rx_buffer, list);
	1908	+ if (buffer) {
	1909	+ list_del(&buffer->list);
	1910	+ stream->next_buf_toisp = buffer;
	1911	+ }
	1912	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
	1913	+ if (!active_buf)
	1914	+ goto out_get_buf;
	1915	+ if (stream->frame_idx == 1)
	1916	+ active_buf->dbufs.is_first = true;
	1917	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	1918	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	1919	+ active_buf->fe_timestamp = ktime_get_ns();
	1920	+ stream->last_frame_idx = stream->frame_idx;
	1921	+ if (dev->hdr.hdr_mode == NO_HDR)
	1922	+ rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	1923	+ else
	1924	+ rkcif_rdbk_frame_end_toisp(stream, active_buf);
	1925	+ stream->buf_num_toisp--;
	1926	+ } else {
	1927	+ rkcif_s_rx_buffer(dev, &stream->curr_buf_toisp->dbufs);
	1928	+ stream->buf_num_toisp--;
	1929	+ }
	1930	+ }
	1931	+ if (stream->lack_buf_cnt)
	1932	+ stream->lack_buf_cnt--;
	1933	+ } else {
	1934	+ if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	1935	+ goto out_get_buf;
	1936	+ if (stream->lack_buf_cnt < 2)
	1937	+ stream->lack_buf_cnt++;
	1938	+ if (dev->hw_dev->dummy_buf.vaddr) {
	1939	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	1940	+ active_buf = stream->curr_buf_toisp;
	1941	+ stream->curr_buf_toisp = NULL;
	1942	+ } else {
	1943	+ active_buf = stream->next_buf_toisp;
	1944	+ stream->next_buf_toisp = NULL;
	1945	+ }
	1946	+ } else if (stream->curr_buf_toisp && stream->next_buf_toisp &&
	1947	+ stream->curr_buf_toisp != stream->next_buf_toisp) {
	1948	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	1949	+ active_buf = stream->curr_buf_toisp;
	1950	+ stream->curr_buf_toisp = stream->next_buf_toisp;
	1951	+ buffer = stream->next_buf_toisp;
	1952	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	1953	+ active_buf = stream->next_buf_toisp;
	1954	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	1955	+ buffer = stream->curr_buf_toisp;
	1956	+ }
	1957	+ if (stream->cifdev->rdbk_debug)
	1958	+ v4l2_info(&stream->cifdev->v4l2_dev,
	1959	+ "stream[%d] hold buf %x\n",
	1960	+ stream->id,
	1961	+ (u32)stream->next_buf_toisp->dummy.dma_addr);
	1962	+ }
	1963	+ if (active_buf) {
	1964	+ if (stream->frame_idx == 1)
	1965	+ active_buf->dbufs.is_first = true;
	1966	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	1967	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	1968	+ active_buf->fe_timestamp = ktime_get_ns();
	1969	+ stream->last_frame_idx = stream->frame_idx;
	1970	+ if (dev->hdr.hdr_mode == NO_HDR)
	1971	+ rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	1972	+ else
	1973	+ rkcif_rdbk_frame_end_toisp(stream, active_buf);
	1974	+ } else {
	1975	+ if (stream->cifdev->rdbk_debug && dev->hw_dev->dummy_buf.vaddr)
	1976	+ v4l2_info(&stream->cifdev->v4l2_dev,
	1977	+ "stream[%d] loss frame %d\n",
	1978	+ stream->id,
	1979	+ stream->frame_idx - 1);
	1980	+ }
	1981	+ }
	1982	+
	1983	+out_get_buf:
	1984	+ stream->frame_phase_cache = stream->frame_phase;
	1985	+ if (buffer) {
	1986	+ rkcif_write_register(dev, frm_addr_y,
	1987	+ buffer->dummy.dma_addr);
	1988	+ if (dev->rdbk_debug > 1 &&
	1989	+ stream->frame_idx < 15)
	1990	+ v4l2_info(&dev->v4l2_dev,
	1991	+ "stream[%d] update, seq %d, reg %x, buf %x\n",
	1992	+ stream->id,
	1993	+ stream->frame_idx - 1,
	1994	+ frm_addr_y, (u32)buffer->dummy.dma_addr);
	1995	+ } else if (dev->hw_dev->dummy_buf.vaddr && priv &&
	1996	+ priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
	1997	+ rkcif_write_register(dev, frm_addr_y,
	1998	+ dev->hw_dev->dummy_buf.dma_addr);
	1999	+ }
	2000	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	2001	+ return 0;
	2002	+}
	2003	+
	2004	+static int rkcif_assign_new_buffer_pingpong_toisp(struct rkcif_stream *stream,
	2005	+ int init, int channel_id)
	2006	+{
	2007	+ int ret = 0;
	2008	+
	2009	+ if (init)
	2010	+ rkcif_assign_new_buffer_init_toisp(stream, channel_id);
	2011	+ else
	2012	+ ret = rkcif_assign_new_buffer_update_toisp(stream, channel_id);
	2013	+ return ret;
	2014	+}
	2015	+
	2016	+void rkcif_assign_check_buffer_update_toisp(struct rkcif_stream *stream)
	2017	+{
	2018	+ struct rkcif_device *dev = stream->cifdev;
	2019	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	2020	+ struct rkcif_rx_buffer *buffer = NULL;
	2021	+ struct rkcif_rx_buffer *active_buf = NULL;
	2022	+ u32 frm_addr_y;
	2023	+ u32 vblank = 0;
	2024	+ u32 vblank_ns = 0;
	2025	+ u64 cur_time = 0;
	2026	+ int frame_phase = 0;
	2027	+ int frame_phase_next = 0;
	2028	+ bool is_early_update = false;
	2029	+
	2030	+ if (stream->curr_buf_toisp != stream->next_buf_toisp) {
	2031	+ if (dev->rdbk_debug > 2 &&
	2032	+ stream->frame_idx < 15)
	2033	+ v4l2_info(&dev->v4l2_dev,
	2034	+ "stream[%d] addr check not equal 0x%x 0x%x\n",
	2035	+ stream->id,
	2036	+ (u32)stream->curr_buf_toisp->dummy.dma_addr,
	2037	+ (u32)stream->next_buf_toisp->dummy.dma_addr);
	2038	+ return;
	2039	+ }
	2040	+ if (!dev->sensor_linetime)
	2041	+ dev->sensor_linetime = rkcif_get_linetime(stream);
	2042	+ vblank = rkcif_get_sensor_vblank(dev);
	2043	+ vblank_ns = vblank * dev->sensor_linetime;
	2044	+ cur_time = ktime_get_ns();
	2045	+
	2046	+ if (dev->chip_id > CHIP_RK3568_CIF &&
	2047	+ dev->hdr.hdr_mode == NO_HDR &&
	2048	+ cur_time - stream->readout.fe_timestamp < (vblank_ns - 500000) &&
	2049	+ stream->lack_buf_cnt == 2 &&
	2050	+ stream->frame_idx > stream->last_frame_idx) {
	2051	+ is_early_update = true;
	2052	+ frame_phase = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	2053	+ CIF_CSI_FRAME1_READY : CIF_CSI_FRAME0_READY;
	2054	+ frame_phase_next = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	2055	+ CIF_CSI_FRAME0_READY : CIF_CSI_FRAME1_READY;
	2056	+ } else {
	2057	+ frame_phase = stream->frame_phase;
	2058	+ }
	2059	+ if (dev->rdbk_debug > 2 &&
	2060	+ stream->frame_idx < 15)
	2061	+ v4l2_info(&dev->v4l2_dev,
	2062	+ "stream[%d] check update, cur %lld, fe %lld, vb %u lack_buf %d\n",
	2063	+ stream->id,
	2064	+ cur_time, stream->readout.fe_timestamp,
	2065	+ vblank_ns, stream->lack_buf_cnt);
	2066	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2067	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	2068	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	2069	+ frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
	2070	+ get_reg_index_of_frm0_y_addr(stream->id) :
	2071	+ get_reg_index_of_frm1_y_addr(stream->id);
	2072	+ } else {
	2073	+ frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
	2074	+ get_dvp_reg_index_of_frm0_y_addr(stream->id) :
	2075	+ get_dvp_reg_index_of_frm1_y_addr(stream->id);
	2076	+ }
	2077	+ if (!list_empty(&stream->rx_buf_head)) {
	2078	+ if (frame_phase == CIF_CSI_FRAME0_READY) {
	2079	+ active_buf = stream->curr_buf_toisp;
	2080	+ buffer = list_first_entry(&stream->rx_buf_head,
	2081	+ struct rkcif_rx_buffer, list);
	2082	+ if (buffer) {
	2083	+ list_del(&buffer->list);
	2084	+ stream->curr_buf_toisp = buffer;
	2085	+ rkcif_write_register(dev, frm_addr_y,
	2086	+ stream->curr_buf_toisp->dummy.dma_addr);
	2087	+ if (dev->rdbk_debug > 1 &&
	2088	+ stream->frame_idx < 15)
	2089	+ v4l2_info(&dev->v4l2_dev,
	2090	+ "stream[%d] check update, seq %d, addr 0x%x, buf 0x%x\n",
	2091	+ stream->id,
	2092	+ stream->frame_idx - 1, frm_addr_y,
	2093	+ (u32)stream->curr_buf_toisp->dummy.dma_addr);
	2094	+ stream->buf_num_toisp--;
	2095	+ }
	2096	+ } else if (frame_phase == CIF_CSI_FRAME1_READY) {
	2097	+ active_buf = stream->next_buf_toisp;
	2098	+ buffer = list_first_entry(&stream->rx_buf_head,
	2099	+ struct rkcif_rx_buffer, list);
	2100	+ if (buffer) {
	2101	+ list_del(&buffer->list);
	2102	+ stream->next_buf_toisp = buffer;
	2103	+ rkcif_write_register(dev, frm_addr_y,
	2104	+ stream->next_buf_toisp->dummy.dma_addr);
	2105	+ if (dev->rdbk_debug > 1 &&
	2106	+ stream->frame_idx < 15)
	2107	+ v4l2_info(&dev->v4l2_dev,
	2108	+ "stream[%d] check update, seq %d, addr 0x%x, buf 0x%x\n",
	2109	+ stream->id,
	2110	+ stream->frame_idx - 1, frm_addr_y,
	2111	+ (u32)stream->next_buf_toisp->dummy.dma_addr);
	2112	+ stream->buf_num_toisp--;
	2113	+ }
	2114	+ }
	2115	+ if (stream->lack_buf_cnt)
	2116	+ stream->lack_buf_cnt--;
	2117	+ }
	2118	+ if (is_early_update) {
	2119	+ if (dev->rdbk_debug > 1 &&
	2120	+ stream->frame_idx < 15)
	2121	+ v4l2_info(&dev->v4l2_dev,
	2122	+ "stream[%d] early update, seq %d\n",
	2123	+ stream->id,
	2124	+ stream->frame_idx - 1);
	2125	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2126	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
	2127	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_CTRL, 0x00010000);
	2128	+ else
	2129	+ rkcif_write_register_or(dev, CIF_REG_DVP_CTRL, 0x00010000);
	2130	+ if (active_buf) {
	2131	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	2132	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	2133	+ stream->last_frame_idx = stream->frame_idx;
	2134	+ rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	2135	+ }
	2136	+ if (dev->hw_dev->dummy_buf.vaddr)
	2137	+ return;
	2138	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2139	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	2140	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	2141	+ frm_addr_y = frame_phase_next & CIF_CSI_FRAME0_READY ?
	2142	+ get_reg_index_of_frm0_y_addr(stream->id) :
	2143	+ get_reg_index_of_frm1_y_addr(stream->id);
	2144	+ } else {
	2145	+ frm_addr_y = frame_phase_next & CIF_CSI_FRAME0_READY ?
	2146	+ get_dvp_reg_index_of_frm0_y_addr(stream->id) :
	2147	+ get_dvp_reg_index_of_frm1_y_addr(stream->id);
	2148	+ }
	2149	+ if (frame_phase == CIF_CSI_FRAME0_READY)
	2150	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	2151	+ else
	2152	+ stream->curr_buf_toisp = stream->next_buf_toisp;
	2153	+ rkcif_write_register(dev, frm_addr_y,
	2154	+ stream->curr_buf_toisp->dummy.dma_addr);
	2155	+ }
1279	2156	}
1280	2157
1281	2158	static void rkcif_assign_new_buffer_init(struct rkcif_stream *stream,
..	..	@@ -1286,10 +2163,11 @@
1286	2163	u32 frm0_addr_y, frm0_addr_uv;
1287	2164	u32 frm1_addr_y, frm1_addr_uv;
1288	2165	unsigned long flags;
1289		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2166	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1290	2167	struct csi_channel_info *channel = &dev->channels[channel_id];
1291	2168
1292		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	2169	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2170	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
1293	2171	mbus_cfg->type == V4L2_MBUS_CCP2) {
1294	2172	frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
1295	2173	frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
..	..	@@ -1324,6 +2202,9 @@
1324	2202	rkcif_write_register(dev, frm0_addr_y, dummy_buf->dma_addr);
1325	2203	if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1326	2204	rkcif_write_register(dev, frm0_addr_uv, dummy_buf->dma_addr);
	2205	+ } else {
	2206	+ if (stream->lack_buf_cnt < 2)
	2207	+ stream->lack_buf_cnt++;
1327	2208	}
1328	2209	}
1329	2210
..	..	@@ -1356,6 +2237,17 @@
1356	2237	rkcif_write_register(dev, frm1_addr_y, dummy_buf->dma_addr);
1357	2238	if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1358	2239	rkcif_write_register(dev, frm1_addr_uv, dummy_buf->dma_addr);
	2240	+ } else {
	2241	+ if (stream->curr_buf) {
	2242	+ stream->next_buf = stream->curr_buf;
	2243	+ rkcif_write_register(dev, frm1_addr_y,
	2244	+ stream->next_buf->buff_addr[RKCIF_PLANE_Y]);
	2245	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2246	+ rkcif_write_register(dev, frm1_addr_uv,
	2247	+ stream->next_buf->buff_addr[RKCIF_PLANE_CBCR]);
	2248	+ }
	2249	+ if (stream->lack_buf_cnt < 2)
	2250	+ stream->lack_buf_cnt++;
1359	2251	}
1360	2252	}
1361	2253	}
..	..	@@ -1388,22 +2280,25 @@
1388	2280	}
1389	2281	}
1390	2282	}
1391		-
	2283	+ stream->buf_owner = RKCIF_DMAEN_BY_VICAP;
1392	2284	}
1393	2285
1394	2286	static int rkcif_assign_new_buffer_update(struct rkcif_stream *stream,
1395		- int channel_id)
	2287	+ int channel_id)
1396	2288	{
1397	2289	struct rkcif_device *dev = stream->cifdev;
1398		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2290	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1399	2291	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1400	2292	struct rkcif_buffer *buffer = NULL;
1401	2293	u32 frm_addr_y, frm_addr_uv;
1402	2294	struct csi_channel_info *channel = &dev->channels[channel_id];
	2295	+ struct rkisp_rx_buf *dbufs = NULL;
	2296	+ struct dma_buf *dbuf = NULL;
1403	2297	int ret = 0;
1404	2298	unsigned long flags;
1405	2299
1406		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	2300	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2301	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
1407	2302	mbus_cfg->type == V4L2_MBUS_CCP2) {
1408	2303	frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1409	2304	get_reg_index_of_frm0_y_addr(channel_id) :
..	..	@@ -1420,20 +2315,44 @@
1420	2315	get_dvp_reg_index_of_frm1_uv_addr(channel_id);
1421	2316	}
1422	2317
	2318	+ if (dev->hdr.hdr_mode != NO_HDR && stream->id != 0 && (!dev->rdbk_buf[RDBK_L])) {
	2319	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
	2320	+ return -EINVAL;
	2321	+ }
	2322	+
	2323	+ if (stream->to_stop_dma) {
	2324	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	2325	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
	2326	+ goto stop_dma;
	2327	+ } else {
	2328	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
	2329	+ return -EINVAL;
	2330	+ }
	2331	+ }
	2332	+
1423	2333	spin_lock_irqsave(&stream->vbq_lock, flags);
1424	2334	if (!list_empty(&stream->buf_head)) {
	2335	+
1425	2336	if (!dummy_buf->vaddr &&
1426	2337	stream->curr_buf == stream->next_buf &&
1427	2338	stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED)
1428	2339	ret = -EINVAL;
	2340	+
1429	2341	if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2342	+ if (!stream->curr_buf)
	2343	+ ret = -EINVAL;
1430	2344	stream->curr_buf = list_first_entry(&stream->buf_head,
1431	2345	struct rkcif_buffer, queue);
1432	2346	if (stream->curr_buf) {
1433	2347	list_del(&stream->curr_buf->queue);
1434	2348	buffer = stream->curr_buf;
	2349	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	2350	+ "stream[%d] update curr_buf 0x%x\n",
	2351	+ stream->id, buffer->buff_addr[0]);
1435	2352	}
1436	2353	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2354	+ if (!stream->next_buf)
	2355	+ ret = -EINVAL;
1437	2356	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1438	2357	if (stream->next_buf != stream->curr_buf) {
1439	2358	stream->next_buf = stream->curr_buf;
..	..	@@ -1448,14 +2367,17 @@
1448	2367	if (stream->next_buf) {
1449	2368	list_del(&stream->next_buf->queue);
1450	2369	buffer = stream->next_buf;
	2370	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	2371	+ "stream[%d] update next_buf 0x%x\n",
	2372	+ stream->id, buffer->buff_addr[0]);
1451	2373	}
1452	2374	}
1453	2375	}
1454		- } else {
	2376	+ } else if (!(stream->dma_en & RKCIF_DMAEN_BY_ISP)) {
1455	2377	buffer = NULL;
1456	2378	if (dummy_buf->vaddr) {
1457	2379	if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1458		- stream->curr_buf = NULL;
	2380	+ stream->curr_buf = NULL;
1459	2381	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1460	2382	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1461	2383	stream->next_buf = stream->curr_buf;
..	..	@@ -1464,7 +2386,8 @@
1464	2386	stream->next_buf = NULL;
1465	2387	}
1466	2388	}
1467		- } else if (stream->curr_buf != stream->next_buf) {
	2389	+ } else if (stream->curr_buf && stream->next_buf &&
	2390	+ stream->curr_buf != stream->next_buf) {
1468	2391	if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1469	2392	stream->curr_buf = stream->next_buf;
1470	2393	buffer = stream->next_buf;
..	..	@@ -1472,12 +2395,16 @@
1472	2395	stream->next_buf = stream->curr_buf;
1473	2396	buffer = stream->curr_buf;
1474	2397	}
1475		-
	2398	+ if (stream->lack_buf_cnt < 2)
	2399	+ stream->lack_buf_cnt++;
	2400	+ } else {
	2401	+ stream->curr_buf = NULL;
	2402	+ stream->next_buf = NULL;
	2403	+ if (stream->lack_buf_cnt < 2)
	2404	+ stream->lack_buf_cnt++;
1476	2405	}
1477		-
1478	2406	}
1479	2407	stream->frame_phase_cache = stream->frame_phase;
1480		- spin_unlock_irqrestore(&stream->vbq_lock, flags);
1481	2408
1482	2409	if (buffer) {
1483	2410	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED &&
..	..	@@ -1494,27 +2421,113 @@
1494	2421	rkcif_write_register(dev, frm_addr_uv,
1495	2422	buffer->buff_addr[RKCIF_PLANE_CBCR]);
1496	2423	}
	2424	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	2425	+ if (stream->buf_replace_cnt < 2)
	2426	+ stream->buf_replace_cnt++;
	2427	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
	2428	+ stream->next_buf)
	2429	+ dbuf = stream->next_buf->dbuf;
	2430	+ else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
	2431	+ stream->curr_buf)
	2432	+ dbuf = stream->curr_buf->dbuf;
	2433	+
	2434	+ if (dbuf) {
	2435	+ list_for_each_entry(dbufs, &stream->rx_buf_head_vicap, list) {
	2436	+ if (dbufs->dbuf == dbuf)
	2437	+ break;
	2438	+ }
	2439	+ }
	2440	+ if (dbufs)
	2441	+ rkcif_s_rx_buffer(dev, dbufs);
	2442	+ stream->buf_num_toisp--;
	2443	+ }
1497	2444	} else {
1498		- if (dummy_buf->vaddr) {
	2445	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	2446	+ rkcif_write_register(dev, frm_addr_y,
	2447	+ stream->curr_buf_toisp->dummy.dma_addr);
	2448	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
	2449	+ stream->next_buf)
	2450	+ dbuf = stream->next_buf->dbuf;
	2451	+ else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
	2452	+ stream->curr_buf)
	2453	+ dbuf = stream->curr_buf->dbuf;
	2454	+
	2455	+ if (dbuf) {
	2456	+ list_for_each_entry(dbufs, &stream->rx_buf_head_vicap, list)
	2457	+ if (dbufs->dbuf == dbuf)
	2458	+ break;
	2459	+ } else {
	2460	+ dbufs = &stream->curr_buf_toisp->dbufs;
	2461	+ }
	2462	+ rkcif_s_rx_buffer(dev, dbufs);
	2463	+ stream->buf_num_toisp--;
	2464	+ if (stream->curr_buf && stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2465	+ stream->curr_buf = NULL;
	2466	+ if (stream->buf_replace_cnt)
	2467	+ stream->buf_replace_cnt--;
	2468	+ } else if (stream->next_buf && stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2469	+ stream->next_buf = NULL;
	2470	+ if (stream->buf_replace_cnt)
	2471	+ stream->buf_replace_cnt--;
	2472	+ }
	2473	+ } else if (dummy_buf->vaddr) {
1499	2474	rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
1500	2475	if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1501	2476	rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
	2477	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	2478	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
1502	2479	} else {
1503	2480	ret = -EINVAL;
	2481	+ stream->curr_buf = NULL;
	2482	+ stream->next_buf = NULL;
	2483	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	2484	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
1504	2485	}
1505		- v4l2_info(&dev->v4l2_dev,
1506		- "not active buffer, skip current frame, %s stream[%d]\n",
1507		- (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
1508		- mbus_cfg->type == V4L2_MBUS_CCP2) ? "mipi/lvds" : "dvp",
1509		- stream->id);
1510	2486	}
	2487	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
1511	2488	return ret;
	2489	+stop_dma:
	2490	+ if (stream->buf_replace_cnt) {
	2491	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	2492	+ rkcif_write_register(dev, frm_addr_y,
	2493	+ stream->curr_buf_toisp->dummy.dma_addr);
	2494	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
	2495	+ stream->next_buf)
	2496	+ dbuf = stream->next_buf->dbuf;
	2497	+ else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
	2498	+ stream->curr_buf)
	2499	+ dbuf = stream->curr_buf->dbuf;
	2500	+
	2501	+ if (dbuf) {
	2502	+ list_for_each_entry(dbufs, &stream->rx_buf_head_vicap, list)
	2503	+ if (dbufs->dbuf == dbuf)
	2504	+ break;
	2505	+ } else {
	2506	+ dbufs = &stream->curr_buf_toisp->dbufs;
	2507	+ }
	2508	+ if (dbufs)
	2509	+ rkcif_s_rx_buffer(dev, dbufs);
	2510	+ stream->buf_num_toisp--;
	2511	+
	2512	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
	2513	+ stream->curr_buf) {
	2514	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
	2515	+ stream->curr_buf = NULL;
	2516	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
	2517	+ stream->next_buf) {
	2518	+ list_add_tail(&stream->next_buf->queue, &stream->buf_head);
	2519	+ stream->next_buf = NULL;
	2520	+ }
	2521	+ stream->buf_replace_cnt--;
	2522	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	2523	+ }
	2524	+ return -EINVAL;
1512	2525	}
1513	2526
1514	2527	static int rkcif_get_new_buffer_wake_up_mode(struct rkcif_stream *stream)
1515	2528	{
1516	2529	struct rkcif_device *dev = stream->cifdev;
1517		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2530	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1518	2531	int ret = 0;
1519	2532	unsigned long flags;
1520	2533
..	..	@@ -1535,6 +2548,8 @@
1535	2548	list_del(&stream->next_buf->queue);
1536	2549	}
1537	2550	stream->is_buf_active = true;
	2551	+ if (stream->lack_buf_cnt)
	2552	+ stream->lack_buf_cnt--;
1538	2553	} else {
1539	2554	stream->is_buf_active = false;
1540	2555	if (dummy_buf->vaddr) {
..	..	@@ -1551,8 +2566,15 @@
1551	2566	stream->frame_phase_cache = CIF_CSI_FRAME1_READY;
1552	2567	}
1553	2568	stream->is_buf_active = true;
	2569	+ if (stream->lack_buf_cnt < 2)
	2570	+ stream->lack_buf_cnt++;
1554	2571	} else {
1555		- ret = -EINVAL;
	2572	+ if (dev->chip_id < CHIP_RK3588_CIF)
	2573	+ ret = -EINVAL;
	2574	+ else
	2575	+ ret = 0;
	2576	+ if (stream->lack_buf_cnt < 2)
	2577	+ stream->lack_buf_cnt++;
1556	2578	}
1557	2579	}
1558	2580	spin_unlock_irqrestore(&stream->vbq_lock, flags);
..	..	@@ -1563,7 +2585,7 @@
1563	2585	static int rkcif_update_new_buffer_wake_up_mode(struct rkcif_stream *stream)
1564	2586	{
1565	2587	struct rkcif_device *dev = stream->cifdev;
1566		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2588	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1567	2589	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1568	2590	struct rkcif_buffer *buffer = NULL;
1569	2591	u32 frm_addr_y, frm_addr_uv;
..	..	@@ -1571,7 +2593,8 @@
1571	2593	int ret = 0;
1572	2594	unsigned long flags;
1573	2595
1574		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	2596	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2597	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
1575	2598	mbus_cfg->type == V4L2_MBUS_CCP2) {
1576	2599	frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1577	2600	get_reg_index_of_frm0_y_addr(channel_id) :
..	..	@@ -1607,14 +2630,92 @@
1607	2630	if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1608	2631	rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
1609	2632	} else {
	2633	+ if (dev->chip_id < CHIP_RK3588_CIF)
	2634	+ ret = -EINVAL;
	2635	+ else
	2636	+ ret = 0;
	2637	+ }
	2638	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	2639	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
	2640	+ }
	2641	+
	2642	+ return ret;
	2643	+}
	2644	+
	2645	+static int rkcif_get_new_buffer_wake_up_mode_rdbk(struct rkcif_stream *stream)
	2646	+{
	2647	+ struct rkcif_rx_buffer *buffer = NULL;
	2648	+ struct rkcif_device *dev = stream->cifdev;
	2649	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	2650	+ int ret = 0;
	2651	+ unsigned long flags;
	2652	+ u32 frm_addr_y;
	2653	+ int frame_phase = 0;
	2654	+
	2655	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	2656	+ if (!list_empty(&stream->rx_buf_head)) {
	2657	+ if (stream->line_int_cnt % 2) {
	2658	+ buffer = list_first_entry(&stream->rx_buf_head,
	2659	+ struct rkcif_rx_buffer, list);
	2660	+ if (buffer) {
	2661	+ list_del(&buffer->list);
	2662	+ stream->curr_buf_toisp = buffer;
	2663	+ }
	2664	+ frame_phase = CIF_CSI_FRAME0_READY;
	2665	+ } else {
	2666	+ buffer = list_first_entry(&stream->rx_buf_head,
	2667	+ struct rkcif_rx_buffer, list);
	2668	+ if (buffer) {
	2669	+ list_del(&buffer->list);
	2670	+ stream->next_buf_toisp = buffer;
	2671	+ }
	2672	+ frame_phase = CIF_CSI_FRAME1_READY;
	2673	+ }
	2674	+ if (stream->lack_buf_cnt)
	2675	+ stream->lack_buf_cnt--;
	2676	+ } else {
	2677	+ if (stream->lack_buf_cnt < 2)
	2678	+ stream->lack_buf_cnt++;
	2679	+ if (stream->curr_buf_toisp && stream->next_buf_toisp &&
	2680	+ stream->curr_buf_toisp != stream->next_buf_toisp) {
	2681	+ if (stream->line_int_cnt % 2)
	2682	+ stream->curr_buf_toisp = stream->next_buf_toisp;
	2683	+ else
	2684	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	2685	+ buffer = stream->curr_buf_toisp;
	2686	+ ret = 0;
	2687	+ if (stream->cifdev->rdbk_debug)
	2688	+ v4l2_info(&stream->cifdev->v4l2_dev,
	2689	+ "stream[%d] hold buf %x\n",
	2690	+ stream->id,
	2691	+ (u32)stream->next_buf_toisp->dummy.dma_addr);
	2692	+ } else {
1610	2693	ret = -EINVAL;
1611	2694	}
1612		- v4l2_info(&dev->v4l2_dev,
1613		- "not active buffer, skip current frame, %s stream[%d]\n",
1614		- (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
1615		- mbus_cfg->type == V4L2_MBUS_CCP2) ? "mipi/lvds" : "dvp",
1616		- stream->id);
1617	2695	}
	2696	+ if (buffer) {
	2697	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2698	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	2699	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	2700	+ frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
	2701	+ get_reg_index_of_frm0_y_addr(stream->id) :
	2702	+ get_reg_index_of_frm1_y_addr(stream->id);
	2703	+ } else {
	2704	+ frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
	2705	+ get_dvp_reg_index_of_frm0_y_addr(stream->id) :
	2706	+ get_dvp_reg_index_of_frm1_y_addr(stream->id);
	2707	+ }
	2708	+ rkcif_write_register(dev, frm_addr_y,
	2709	+ buffer->dummy.dma_addr);
	2710	+ if (dev->rdbk_debug > 1 &&
	2711	+ stream->frame_idx < 15)
	2712	+ v4l2_info(&dev->v4l2_dev,
	2713	+ "stream[%d] rdbk update, seq %d, reg %x, buf %x\n",
	2714	+ stream->id,
	2715	+ stream->frame_idx - 1,
	2716	+ frm_addr_y, (u32)buffer->dummy.dma_addr);
	2717	+ }
	2718	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
1618	2719
1619	2720	return ret;
1620	2721	}
..	..	@@ -1623,7 +2724,7 @@
1623	2724	{
1624	2725	struct rkcif_device *dev = stream->cifdev;
1625	2726	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1626		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2727	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1627	2728	unsigned long flags;
1628	2729
1629	2730	spin_lock_irqsave(&stream->vbq_lock, flags);
..	..	@@ -1658,6 +2759,276 @@
1658	2759	rkcif_assign_new_buffer_init(stream, channel_id);
1659	2760	else
1660	2761	ret = rkcif_assign_new_buffer_update(stream, channel_id);
	2762	+ return ret;
	2763	+}
	2764	+
	2765	+static void rkcif_assign_new_buffer_init_rockit(struct rkcif_stream *stream,
	2766	+ int channel_id)
	2767	+{
	2768	+ struct rkcif_device *dev = stream->cifdev;
	2769	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	2770	+ u32 frm0_addr_y, frm0_addr_uv;
	2771	+ u32 frm1_addr_y, frm1_addr_uv;
	2772	+ unsigned long flags;
	2773	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
	2774	+ struct csi_channel_info *channel = &dev->channels[channel_id];
	2775	+
	2776	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2777	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	2778	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	2779	+ frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
	2780	+ frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
	2781	+ frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
	2782	+ frm1_addr_uv = get_reg_index_of_frm1_uv_addr(channel_id);
	2783	+ } else {
	2784	+ frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
	2785	+ frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(channel_id);
	2786	+ frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
	2787	+ frm1_addr_uv = get_dvp_reg_index_of_frm1_uv_addr(channel_id);
	2788	+ }
	2789	+
	2790	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	2791	+
	2792	+ if (!stream->curr_buf_rockit) {
	2793	+ if (!list_empty(&stream->rockit_buf_head)) {
	2794	+ stream->curr_buf_rockit = list_first_entry(&stream->rockit_buf_head,
	2795	+ struct rkcif_buffer,
	2796	+ queue);
	2797	+ list_del(&stream->curr_buf_rockit->queue);
	2798	+ }
	2799	+ }
	2800	+
	2801	+ if (stream->curr_buf_rockit) {
	2802	+ rkcif_write_register(dev, frm0_addr_y,
	2803	+ stream->curr_buf_rockit->buff_addr[RKCIF_PLANE_Y]);
	2804	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2805	+ rkcif_write_register(dev, frm0_addr_uv,
	2806	+ stream->curr_buf_rockit->buff_addr[RKCIF_PLANE_CBCR]);
	2807	+ } else {
	2808	+ if (dummy_buf->vaddr) {
	2809	+ rkcif_write_register(dev, frm0_addr_y, dummy_buf->dma_addr);
	2810	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2811	+ rkcif_write_register(dev, frm0_addr_uv, dummy_buf->dma_addr);
	2812	+ } else {
	2813	+ if (stream->lack_buf_cnt < 2)
	2814	+ stream->lack_buf_cnt++;
	2815	+ }
	2816	+ }
	2817	+
	2818	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	2819	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	2820	+ if (stream->next_buf_rockit) {
	2821	+ rkcif_write_register(dev, frm1_addr_y,
	2822	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
	2823	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2824	+ rkcif_write_register(dev, frm1_addr_uv,
	2825	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	2826	+ }
	2827	+ } else {
	2828	+ if (!stream->next_buf_rockit) {
	2829	+ if (!list_empty(&stream->rockit_buf_head)) {
	2830	+ stream->next_buf_rockit = list_first_entry(&stream->rockit_buf_head,
	2831	+ struct rkcif_buffer, queue);
	2832	+ list_del(&stream->next_buf_rockit->queue);
	2833	+ }
	2834	+ }
	2835	+
	2836	+ if (stream->next_buf_rockit) {
	2837	+ rkcif_write_register(dev, frm1_addr_y,
	2838	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_Y]);
	2839	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2840	+ rkcif_write_register(dev, frm1_addr_uv,
	2841	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_CBCR]);
	2842	+ } else {
	2843	+ if (dummy_buf->vaddr) {
	2844	+ rkcif_write_register(dev, frm1_addr_y, dummy_buf->dma_addr);
	2845	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2846	+ rkcif_write_register(dev, frm1_addr_uv, dummy_buf->dma_addr);
	2847	+ } else {
	2848	+ if (stream->curr_buf_rockit) {
	2849	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	2850	+ rkcif_write_register(dev, frm1_addr_y,
	2851	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_Y]);
	2852	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2853	+ rkcif_write_register(dev, frm1_addr_uv,
	2854	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_CBCR]);
	2855	+ }
	2856	+ if (stream->lack_buf_cnt < 2)
	2857	+ stream->lack_buf_cnt++;
	2858	+ }
	2859	+ }
	2860	+ }
	2861	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	2862	+
	2863	+ stream->is_dvp_yuv_addr_init = true;
	2864	+
	2865	+ /* for BT.656/BT.1120 multi channels function,
	2866	+ * yuv addr of unused channel must be set
	2867	+ */
	2868	+ if (mbus_cfg->type == V4L2_MBUS_BT656) {
	2869	+ int ch_id;
	2870	+
	2871	+ for (ch_id = 0; ch_id < RKCIF_MAX_STREAM_DVP; ch_id++) {
	2872	+ if (dev->stream[ch_id].is_dvp_yuv_addr_init)
	2873	+ continue;
	2874	+ if (dummy_buf->dma_addr) {
	2875	+ rkcif_write_register(dev,
	2876	+ get_dvp_reg_index_of_frm0_y_addr(ch_id),
	2877	+ dummy_buf->dma_addr);
	2878	+ rkcif_write_register(dev,
	2879	+ get_dvp_reg_index_of_frm0_uv_addr(ch_id),
	2880	+ dummy_buf->dma_addr);
	2881	+ rkcif_write_register(dev,
	2882	+ get_dvp_reg_index_of_frm1_y_addr(ch_id),
	2883	+ dummy_buf->dma_addr);
	2884	+ rkcif_write_register(dev,
	2885	+ get_dvp_reg_index_of_frm1_uv_addr(ch_id),
	2886	+ dummy_buf->dma_addr);
	2887	+ }
	2888	+ }
	2889	+ }
	2890	+ stream->buf_owner = RKCIF_DMAEN_BY_ROCKIT;
	2891	+}
	2892	+
	2893	+static int rkcif_assign_new_buffer_update_rockit(struct rkcif_stream *stream,
	2894	+ int channel_id)
	2895	+{
	2896	+ struct rkcif_device *dev = stream->cifdev;
	2897	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
	2898	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	2899	+ struct rkcif_buffer *buffer = NULL;
	2900	+ u32 frm_addr_y, frm_addr_uv;
	2901	+ struct csi_channel_info *channel = &dev->channels[channel_id];
	2902	+ int ret = 0;
	2903	+ unsigned long flags;
	2904	+
	2905	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2906	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	2907	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	2908	+ frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	2909	+ get_reg_index_of_frm0_y_addr(channel_id) :
	2910	+ get_reg_index_of_frm1_y_addr(channel_id);
	2911	+ frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	2912	+ get_reg_index_of_frm0_uv_addr(channel_id) :
	2913	+ get_reg_index_of_frm1_uv_addr(channel_id);
	2914	+ } else {
	2915	+ frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	2916	+ get_dvp_reg_index_of_frm0_y_addr(channel_id) :
	2917	+ get_dvp_reg_index_of_frm1_y_addr(channel_id);
	2918	+ frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	2919	+ get_dvp_reg_index_of_frm0_uv_addr(channel_id) :
	2920	+ get_dvp_reg_index_of_frm1_uv_addr(channel_id);
	2921	+ }
	2922	+
	2923	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	2924	+ if (!list_empty(&stream->rockit_buf_head)) {
	2925	+
	2926	+ if (!dummy_buf->vaddr &&
	2927	+ stream->curr_buf_rockit == stream->next_buf_rockit &&
	2928	+ stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED)
	2929	+ ret = -EINVAL;
	2930	+
	2931	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2932	+ if (!stream->curr_buf_rockit)
	2933	+ ret = -EINVAL;
	2934	+ stream->curr_buf_rockit = list_first_entry(&stream->rockit_buf_head,
	2935	+ struct rkcif_buffer, queue);
	2936	+ if (stream->curr_buf_rockit) {
	2937	+ list_del(&stream->curr_buf_rockit->queue);
	2938	+ buffer = stream->curr_buf_rockit;
	2939	+ }
	2940	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2941	+ if (!stream->next_buf_rockit)
	2942	+ ret = -EINVAL;
	2943	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	2944	+ if (stream->next_buf_rockit != stream->curr_buf_rockit) {
	2945	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	2946	+ buffer = stream->next_buf_rockit;
	2947	+ } else {
	2948	+ buffer = NULL;
	2949	+ }
	2950	+
	2951	+ } else {
	2952	+ stream->next_buf_rockit = list_first_entry(&stream->rockit_buf_head,
	2953	+ struct rkcif_buffer, queue);
	2954	+ if (stream->next_buf_rockit) {
	2955	+ list_del(&stream->next_buf_rockit->queue);
	2956	+ buffer = stream->next_buf_rockit;
	2957	+ }
	2958	+ }
	2959	+ }
	2960	+ } else {
	2961	+ buffer = NULL;
	2962	+ if (dummy_buf->vaddr) {
	2963	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2964	+ stream->curr_buf_rockit = NULL;
	2965	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2966	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	2967	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	2968	+ buffer = stream->next_buf_rockit;
	2969	+ } else {
	2970	+ stream->next_buf_rockit = NULL;
	2971	+ }
	2972	+ }
	2973	+ } else if (stream->curr_buf_rockit && stream->next_buf_rockit &&
	2974	+ stream->curr_buf_rockit != stream->next_buf_rockit) {
	2975	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2976	+ stream->curr_buf_rockit = stream->next_buf_rockit;
	2977	+ buffer = stream->next_buf_rockit;
	2978	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2979	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	2980	+ buffer = stream->curr_buf_rockit;
	2981	+ }
	2982	+ if (stream->lack_buf_cnt < 2)
	2983	+ stream->lack_buf_cnt++;
	2984	+ } else {
	2985	+ if (stream->lack_buf_cnt < 2)
	2986	+ stream->lack_buf_cnt++;
	2987	+ }
	2988	+ }
	2989	+ stream->frame_phase_cache = stream->frame_phase;
	2990	+
	2991	+ if (buffer) {
	2992	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED &&
	2993	+ stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2994	+ rkcif_write_register(dev, frm_addr_y,
	2995	+ buffer->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
	2996	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2997	+ rkcif_write_register(dev, frm_addr_uv,
	2998	+ buffer->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	2999	+ } else {
	3000	+ rkcif_write_register(dev, frm_addr_y,
	3001	+ buffer->buff_addr[RKCIF_PLANE_Y]);
	3002	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3003	+ rkcif_write_register(dev, frm_addr_uv,
	3004	+ buffer->buff_addr[RKCIF_PLANE_CBCR]);
	3005	+ }
	3006	+ } else {
	3007	+ if (dummy_buf->vaddr) {
	3008	+ rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
	3009	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3010	+ rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
	3011	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	3012	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
	3013	+ } else {
	3014	+ ret = -EINVAL;
	3015	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	3016	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
	3017	+ }
	3018	+ }
	3019	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	3020	+ return ret;
	3021	+}
	3022	+
	3023	+static int rkcif_assign_new_buffer_pingpong_rockit(struct rkcif_stream *stream,
	3024	+ int init, int channel_id)
	3025	+{
	3026	+ int ret = 0;
	3027	+
	3028	+ if (init)
	3029	+ rkcif_assign_new_buffer_init_rockit(stream, channel_id);
	3030	+ else
	3031	+ ret = rkcif_assign_new_buffer_update_rockit(stream, channel_id);
1661	3032	return ret;
1662	3033	}
1663	3034
..	..	@@ -1709,7 +3080,7 @@
1709	3080	struct rkmodule_lvds_frm_sync_code *odd_sync_code = NULL;
1710	3081	struct rkmodule_lvds_frm_sync_code *even_sync_code = NULL;
1711	3082
1712		- if (dev->hdr.mode == NO_HDR) {
	3083	+ if (dev->hdr.hdr_mode == NO_HDR \|\| dev->hdr.hdr_mode == HDR_COMPR) {
1713	3084	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LINEAR];
1714	3085	odd_sync_code = &frm_sync_code->odd_sync_code;
1715	3086	even_sync_code = odd_sync_code;
..	..	@@ -1717,12 +3088,12 @@
1717	3088	if (channel->id == RKCIF_STREAM_MIPI_ID0)
1718	3089	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LONG];
1719	3090
1720		- if (dev->hdr.mode == HDR_X2) {
	3091	+ if (dev->hdr.hdr_mode == HDR_X2) {
1721	3092	if (channel->id == RKCIF_STREAM_MIPI_ID1)
1722	3093	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_SHORT];
1723	3094	else
1724	3095	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LONG];
1725		- } else if (dev->hdr.mode == HDR_X3) {
	3096	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
1726	3097	if (channel->id == RKCIF_STREAM_MIPI_ID1)
1727	3098	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_MEDIUM];
1728	3099	else if (channel->id == RKCIF_STREAM_MIPI_ID2)
..	..	@@ -1758,12 +3129,43 @@
1758	3129	}
1759	3130	}
1760	3131
	3132	+static unsigned char get_csi_fmt_val(const struct cif_input_fmt *cif_fmt_in,
	3133	+ struct csi_channel_info *csi_info)
	3134	+{
	3135	+ unsigned char csi_fmt_val = 0;
	3136	+
	3137	+ if (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 \|\|
	3138	+ cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8) {
	3139	+ switch (csi_info->data_bit) {
	3140	+ case 8:
	3141	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW8;
	3142	+ break;
	3143	+ case 10:
	3144	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW10;
	3145	+ break;
	3146	+ case 12:
	3147	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW12;
	3148	+ break;
	3149	+ default:
	3150	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW12;
	3151	+ break;
	3152	+ }
	3153	+ } else if (cif_fmt_in->csi_fmt_val == CSI_WRDDR_TYPE_RGB888 \|\|
	3154	+ cif_fmt_in->csi_fmt_val == CSI_WRDDR_TYPE_RGB565) {
	3155	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW8;
	3156	+ } else {
	3157	+ csi_fmt_val = cif_fmt_in->csi_fmt_val;
	3158	+ }
	3159	+ return csi_fmt_val;
	3160	+}
	3161	+
1761	3162	static int rkcif_csi_channel_init(struct rkcif_stream *stream,
1762	3163	struct csi_channel_info *channel)
1763	3164	{
1764	3165	struct rkcif_device *dev = stream->cifdev;
1765	3166	const struct cif_output_fmt *fmt;
1766	3167	u32 fourcc;
	3168	+ int vc = dev->channels[stream->id].vc;
1767	3169
1768	3170	channel->enable = 1;
1769	3171	channel->width = stream->pixm.width;
..	..	@@ -1779,10 +3181,14 @@
1779	3181
1780	3182	if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
1781	3183	channel->crop_st_x = 3 * stream->crop[CROP_SRC_ACT].left;
	3184	+ else if (channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
	3185	+ channel->crop_st_x = 2 * stream->crop[CROP_SRC_ACT].left;
1782	3186	else
1783	3187	channel->crop_st_x = stream->crop[CROP_SRC_ACT].left;
1784	3188
1785	3189	channel->crop_st_y = stream->crop[CROP_SRC_ACT].top;
	3190	+ if (dev->sditf_cnt > 1 && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	3191	+ channel->crop_st_y *= dev->sditf_cnt;
1786	3192	channel->width = stream->crop[CROP_SRC_ACT].width;
1787	3193	channel->height = stream->crop[CROP_SRC_ACT].height;
1788	3194	} else {
..	..	@@ -1791,7 +3197,10 @@
1791	3197	channel->crop_en = 0;
1792	3198	}
1793	3199
1794		- fmt = find_output_fmt(stream, stream->pixm.pixelformat);
	3200	+ if (dev->sditf_cnt > 1 && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	3201	+ channel->height *= dev->sditf_cnt;
	3202	+
	3203	+ fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
1795	3204	if (!fmt) {
1796	3205	v4l2_err(&dev->v4l2_dev, "can not find output format: 0x%x",
1797	3206	stream->pixm.pixelformat);
..	..	@@ -1805,13 +3214,14 @@
1805	3214	* writing of ddr, aliged with 256
1806	3215	*/
1807	3216	if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
1808		- fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888) {
	3217	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
	3218	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
1809	3219	channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 256);
1810	3220	} else {
1811	3221	channel->virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
1812	3222	}
1813	3223
1814		- if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
	3224	+ if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888 \|\| channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
1815	3225	channel->width = channel->width * fmt->bpp[0] / 8;
1816	3226	/*
1817	3227	* rk cif don't support output yuyv fmt data
..	..	@@ -1819,36 +3229,51 @@
1819	3229	* and the width is double Because the real input fmt is
1820	3230	* yuyv
1821	3231	*/
1822		- fourcc = stream->cif_fmt_out->fourcc;
	3232	+ fourcc = stream->cif_fmt_out->fourcc;
1823	3233	if (fourcc == V4L2_PIX_FMT_YUYV \|\| fourcc == V4L2_PIX_FMT_YVYU \|\|
1824	3234	fourcc == V4L2_PIX_FMT_UYVY \|\| fourcc == V4L2_PIX_FMT_VYUY) {
1825		- channel->fmt_val = CSI_WRDDR_TYPE_RAW8;
1826		- channel->width *= 2;
	3235	+ if (dev->chip_id < CHIP_RK3588_CIF) {
	3236	+ channel->fmt_val = CSI_WRDDR_TYPE_RAW8;
	3237	+ channel->width *= 2;
	3238	+ }
1827	3239	channel->virtual_width *= 2;
1828	3240	}
1829	3241	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1830	3242	channel->virtual_width *= 2;
1831	3243	channel->height /= 2;
1832	3244	}
	3245	+ if (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
	3246	+ stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8) {
	3247	+ if (dev->channels[stream->id].data_type)
	3248	+ channel->data_type = dev->channels[stream->id].data_type;
	3249	+ else
	3250	+ channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
	3251	+ channel->cmd_mode_en,
	3252	+ channel->dsi_input);
	3253	+ } else {
	3254	+ channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
	3255	+ channel->cmd_mode_en,
	3256	+ channel->dsi_input);
	3257	+ }
	3258	+ channel->csi_fmt_val = get_csi_fmt_val(stream->cif_fmt_in,
	3259	+ &dev->channels[stream->id]);
1833	3260
1834		- channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
1835		- channel->cmd_mode_en, channel->dsi_input);
1836		-
1837		- if ((dev->hdr.mode == NO_HDR && stream->vc >= 0) \|\|
1838		- (dev->hdr.mode == HDR_X2 && stream->vc > 1) \|\|
1839		- (dev->hdr.mode == HDR_X3 && stream->vc > 2))
1840		- channel->vc = stream->vc;
	3261	+ if (dev->hdr.hdr_mode == NO_HDR \|\|
	3262	+ dev->hdr.hdr_mode == HDR_COMPR \|\|
	3263	+ (dev->hdr.hdr_mode == HDR_X2 && stream->id > 1) \|\|
	3264	+ (dev->hdr.hdr_mode == HDR_X3 && stream->id > 2))
	3265	+ channel->vc = vc < 4 ? vc : channel->id;
1841	3266	else
1842	3267	channel->vc = channel->id;
1843		- v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	3268	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
1844	3269	"%s: channel width %d, height %d, virtual_width %d, vc %d\n", __func__,
1845	3270	channel->width, channel->height, channel->virtual_width, channel->vc);
1846	3271	return 0;
1847	3272	}
1848	3273
1849	3274	static int rkcif_csi_channel_set(struct rkcif_stream *stream,
1850		- struct csi_channel_info *channel,
1851		- enum v4l2_mbus_type mbus_type)
	3275	+ struct csi_channel_info *channel,
	3276	+ enum v4l2_mbus_type mbus_type)
1852	3277	{
1853	3278	unsigned int val = 0x0;
1854	3279	struct rkcif_device *dev = stream->cifdev;
..	..	@@ -1869,10 +3294,9 @@
1869	3294	CSI_DMA_END_INTSTAT(channel->id) \|
1870	3295	CSI_LINE_INTSTAT(channel->id)));
1871	3296
1872		- /* enable id0 frame start int for sof(long frame, for hdr) */
1873		- if (channel->id == RKCIF_STREAM_MIPI_ID0)
1874		- rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
1875		- CSI_START_INTEN(channel->id));
	3297	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3298	+ CSI_START_INTEN(channel->id));
	3299	+
1876	3300	if (detect_stream->is_line_wake_up) {
1877	3301	rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
1878	3302	CSI_LINE_INTEN(channel->id));
..	..	@@ -1891,15 +3315,15 @@
1891	3315	CIF_MIPI_LVDS_SW_HURRY_VALUE_RK1808(0x3) \|
1892	3316	CIF_MIPI_LVDS_SW_HURRY_ENABLE_RK1808);
1893	3317
1894		- val = CIF_MIPI_LVDS_SW_PRESS_VALUE(0x7) \|
	3318	+ val = CIF_MIPI_LVDS_SW_PRESS_VALUE(0x3) \|
1895	3319	CIF_MIPI_LVDS_SW_PRESS_ENABLE \|
1896		- CIF_MIPI_LVDS_SW_HURRY_VALUE(0x7) \|
	3320	+ CIF_MIPI_LVDS_SW_HURRY_VALUE(0x3) \|
1897	3321	CIF_MIPI_LVDS_SW_HURRY_ENABLE \|
1898	3322	CIF_MIPI_LVDS_SW_WATER_LINE_25 \|
1899	3323	CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
1900		- if (mbus_type == V4L2_MBUS_CSI2) {
	3324	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
1901	3325	val &= ~CIF_MIPI_LVDS_SW_SEL_LVDS;
1902		- } else if (mbus_type == V4L2_MBUS_CCP2) {
	3326	+ } else if (mbus_type == V4L2_MBUS_CCP2) {
1903	3327	if (channel->fmt_val == CSI_WRDDR_TYPE_RAW12)
1904	3328	val \|= CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS;
1905	3329	else if (channel->fmt_val == CSI_WRDDR_TYPE_RAW10)
..	..	@@ -1934,7 +3358,7 @@
1934	3358	RKCIF_YUV_ADDR_STATE_INIT,
1935	3359	channel->id);
1936	3360
1937		- if (mbus_type == V4L2_MBUS_CSI2) {
	3361	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
1938	3362	//need always enable crop
1939	3363	val = CSI_ENABLE_CAPTURE \| channel->fmt_val \|
1940	3364	channel->cmd_mode_en << 4 \| CSI_ENABLE_CROP \|
..	..	@@ -1946,7 +3370,7 @@
1946	3370
1947	3371	if (stream->cifdev->chip_id >= CHIP_RK3568_CIF)
1948	3372	val \|= stream->cif_fmt_in->csi_yuv_order;
1949		- } else if (mbus_type == V4L2_MBUS_CCP2) {
	3373	+ } else if (mbus_type == V4L2_MBUS_CCP2) {
1950	3374	rkcif_csi_set_lvds_sav_eav(stream, channel);
1951	3375	val = LVDS_ENABLE_CAPTURE \| LVDS_MODE(channel->lvds_cfg.mode) \|
1952	3376	LVDS_MAIN_LANE(0) \| LVDS_FID(0) \|
..	..	@@ -1958,15 +3382,364 @@
1958	3382	val &= ~LVDS_COMPACT;
1959	3383	}
1960	3384	if (stream->is_high_align)
1961		- val \|= CSI_ENABLE_MIPI_HIGH_ALIGN;
	3385	+ val \|= CSI_HIGH_ALIGN;
1962	3386	else
1963		- val &= ~CSI_ENABLE_MIPI_HIGH_ALIGN;
	3387	+ val &= ~CSI_HIGH_ALIGN;
1964	3388	rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
1965	3389
1966	3390	return 0;
1967	3391	}
1968	3392
1969		-static int rkcif_csi_stream_start(struct rkcif_stream *stream)
	3393	+static int rkcif_dvp_get_input_yuv_order(struct rkcif_stream *stream)
	3394	+{
	3395	+ unsigned int mask;
	3396	+ const struct cif_input_fmt *fmt = stream->cif_fmt_in;
	3397	+
	3398	+ switch (fmt->mbus_code) {
	3399	+ case MEDIA_BUS_FMT_UYVY8_2X8:
	3400	+ mask = CSI_YUV_INPUT_ORDER_UYVY >> 11;
	3401	+ break;
	3402	+ case MEDIA_BUS_FMT_VYUY8_2X8:
	3403	+ mask = CSI_YUV_INPUT_ORDER_VYUY >> 11;
	3404	+ break;
	3405	+ case MEDIA_BUS_FMT_YUYV8_2X8:
	3406	+ mask = CSI_YUV_INPUT_ORDER_YUYV >> 11;
	3407	+ break;
	3408	+ case MEDIA_BUS_FMT_YVYU8_2X8:
	3409	+ mask = CSI_YUV_INPUT_ORDER_YVYU >> 11;
	3410	+ break;
	3411	+ default:
	3412	+ mask = CSI_YUV_INPUT_ORDER_UYVY >> 11;
	3413	+ break;
	3414	+ }
	3415	+ return mask;
	3416	+}
	3417	+
	3418	+static int rkcif_csi_get_output_type_mask(struct rkcif_stream *stream)
	3419	+{
	3420	+ unsigned int mask;
	3421	+ const struct cif_output_fmt *fmt = stream->cif_fmt_out;
	3422	+
	3423	+ switch (fmt->fourcc) {
	3424	+ case V4L2_PIX_FMT_NV16:
	3425	+ mask = CSI_WRDDR_TYPE_YUV422SP_RK3588 \| CSI_YUV_OUTPUT_ORDER_UYVY;
	3426	+ break;
	3427	+ case V4L2_PIX_FMT_NV61:
	3428	+ mask = CSI_WRDDR_TYPE_YUV422SP_RK3588 \| CSI_YUV_OUTPUT_ORDER_VYUY;
	3429	+ break;
	3430	+ case V4L2_PIX_FMT_NV12:
	3431	+ mask = CSI_WRDDR_TYPE_YUV420SP_RK3588 \| CSI_YUV_OUTPUT_ORDER_UYVY;
	3432	+ break;
	3433	+ case V4L2_PIX_FMT_NV21:
	3434	+ mask = CSI_WRDDR_TYPE_YUV420SP_RK3588 \| CSI_YUV_OUTPUT_ORDER_VYUY;
	3435	+ break;
	3436	+ case V4L2_PIX_FMT_YUYV:
	3437	+ mask = CSI_WRDDR_TYPE_YUV_PACKET \| CSI_YUV_OUTPUT_ORDER_YUYV;
	3438	+ break;
	3439	+ case V4L2_PIX_FMT_YVYU:
	3440	+ mask = CSI_WRDDR_TYPE_YUV_PACKET \| CSI_YUV_OUTPUT_ORDER_YVYU;
	3441	+ break;
	3442	+ case V4L2_PIX_FMT_UYVY:
	3443	+ mask = CSI_WRDDR_TYPE_YUV_PACKET \| CSI_YUV_OUTPUT_ORDER_UYVY;
	3444	+ break;
	3445	+ case V4L2_PIX_FMT_VYUY:
	3446	+ mask = CSI_WRDDR_TYPE_YUV_PACKET \| CSI_YUV_OUTPUT_ORDER_VYUY;
	3447	+ break;
	3448	+ case V4L2_PIX_FMT_RGB24:
	3449	+ case V4L2_PIX_FMT_BGR24:
	3450	+ case V4L2_PIX_FMT_RGB565:
	3451	+ case V4L2_PIX_FMT_BGR666:
	3452	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT;
	3453	+ break;
	3454	+ case V4L2_PIX_FMT_SRGGB8:
	3455	+ case V4L2_PIX_FMT_SGRBG8:
	3456	+ case V4L2_PIX_FMT_SGBRG8:
	3457	+ case V4L2_PIX_FMT_SBGGR8:
	3458	+ case V4L2_PIX_FMT_SRGGB10:
	3459	+ case V4L2_PIX_FMT_SGRBG10:
	3460	+ case V4L2_PIX_FMT_SGBRG10:
	3461	+ case V4L2_PIX_FMT_SBGGR10:
	3462	+ case V4L2_PIX_FMT_SRGGB12:
	3463	+ case V4L2_PIX_FMT_SGRBG12:
	3464	+ case V4L2_PIX_FMT_SGBRG12:
	3465	+ case V4L2_PIX_FMT_SBGGR12:
	3466	+ case V4L2_PIX_FMT_GREY:
	3467	+ case V4L2_PIX_FMT_Y10:
	3468	+ case V4L2_PIX_FMT_Y12:
	3469	+ if (stream->is_compact)
	3470	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT;
	3471	+ else
	3472	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT;
	3473	+ break;
	3474	+ case V4L2_PIX_FMT_SBGGR16:
	3475	+ case V4L2_PIX_FMT_SGBRG16:
	3476	+ case V4L2_PIX_FMT_SGRBG16:
	3477	+ case V4L2_PIX_FMT_SRGGB16:
	3478	+ case V4L2_PIX_FMT_Y16:
	3479	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT;
	3480	+ break;
	3481	+ default:
	3482	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT;
	3483	+ break;
	3484	+ }
	3485	+ return mask;
	3486	+}
	3487	+
	3488	+static int rkcif_lvds_get_output_type_mask(struct rkcif_stream *stream)
	3489	+{
	3490	+ unsigned int mask;
	3491	+ const struct cif_output_fmt *fmt = stream->cif_fmt_out;
	3492	+ int wr_type_offset = 0;
	3493	+ int yuvout_offset = 0;
	3494	+
	3495	+ if (stream->cifdev->chip_id == CHIP_RV1106_CIF) {
	3496	+ wr_type_offset = 17;
	3497	+ yuvout_offset = 9;
	3498	+ }
	3499	+
	3500	+ switch (fmt->fourcc) {
	3501	+ case V4L2_PIX_FMT_NV16:
	3502	+ mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << wr_type_offset) \|
	3503	+ (CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
	3504	+ break;
	3505	+ case V4L2_PIX_FMT_NV61:
	3506	+ mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << wr_type_offset) \|
	3507	+ (CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
	3508	+ break;
	3509	+ case V4L2_PIX_FMT_NV12:
	3510	+ mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << wr_type_offset) \|
	3511	+ (CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
	3512	+ break;
	3513	+ case V4L2_PIX_FMT_NV21:
	3514	+ mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << wr_type_offset) \|
	3515	+ (CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
	3516	+ break;
	3517	+ case V4L2_PIX_FMT_YUYV:
	3518	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) \|
	3519	+ (CSI_YUV_OUTPUT_ORDER_YUYV << yuvout_offset);
	3520	+ break;
	3521	+ case V4L2_PIX_FMT_YVYU:
	3522	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) \|
	3523	+ (CSI_YUV_OUTPUT_ORDER_YVYU << yuvout_offset);
	3524	+ break;
	3525	+ case V4L2_PIX_FMT_UYVY:
	3526	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) \|
	3527	+ (CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
	3528	+ break;
	3529	+ case V4L2_PIX_FMT_VYUY:
	3530	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) \|
	3531	+ (CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
	3532	+ break;
	3533	+ case V4L2_PIX_FMT_RGB24:
	3534	+ case V4L2_PIX_FMT_BGR24:
	3535	+ case V4L2_PIX_FMT_RGB565:
	3536	+ case V4L2_PIX_FMT_BGR666:
	3537	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
	3538	+ break;
	3539	+ case V4L2_PIX_FMT_SRGGB8:
	3540	+ case V4L2_PIX_FMT_SGRBG8:
	3541	+ case V4L2_PIX_FMT_SGBRG8:
	3542	+ case V4L2_PIX_FMT_SBGGR8:
	3543	+ case V4L2_PIX_FMT_SRGGB10:
	3544	+ case V4L2_PIX_FMT_SGRBG10:
	3545	+ case V4L2_PIX_FMT_SGBRG10:
	3546	+ case V4L2_PIX_FMT_SBGGR10:
	3547	+ case V4L2_PIX_FMT_SRGGB12:
	3548	+ case V4L2_PIX_FMT_SGRBG12:
	3549	+ case V4L2_PIX_FMT_SGBRG12:
	3550	+ case V4L2_PIX_FMT_SBGGR12:
	3551	+ case V4L2_PIX_FMT_GREY:
	3552	+ case V4L2_PIX_FMT_Y10:
	3553	+ case V4L2_PIX_FMT_Y12:
	3554	+ if (stream->is_compact)
	3555	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
	3556	+ else
	3557	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << wr_type_offset;
	3558	+ break;
	3559	+ case V4L2_PIX_FMT_SBGGR16:
	3560	+ case V4L2_PIX_FMT_SGBRG16:
	3561	+ case V4L2_PIX_FMT_SGRBG16:
	3562	+ case V4L2_PIX_FMT_SRGGB16:
	3563	+ case V4L2_PIX_FMT_Y16:
	3564	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << wr_type_offset;
	3565	+ break;
	3566	+ default:
	3567	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
	3568	+ break;
	3569	+ }
	3570	+ return mask;
	3571	+}
	3572	+
	3573	+static void rkcif_modify_frame_skip_config(struct rkcif_stream *stream)
	3574	+{
	3575	+ if (stream->skip_info.skip_to_en) {
	3576	+ rkcif_disable_skip_frame(stream);
	3577	+ rkcif_enable_skip_frame(stream,
	3578	+ stream->skip_info.cap_m,
	3579	+ stream->skip_info.skip_n);
	3580	+ stream->skip_info.skip_to_en = false;
	3581	+ } else if (stream->skip_info.skip_to_dis) {
	3582	+ rkcif_disable_skip_frame(stream);
	3583	+ }
	3584	+}
	3585	+
	3586	+/config reg for rk3588/
	3587	+static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
	3588	+ struct csi_channel_info *channel,
	3589	+ enum v4l2_mbus_type mbus_type, unsigned int mode)
	3590	+{
	3591	+ unsigned int val = 0x0;
	3592	+ struct rkcif_device *dev = stream->cifdev;
	3593	+ struct rkcif_stream *detect_stream = &dev->stream[0];
	3594	+ struct sditf_priv *priv = dev->sditf[0];
	3595	+ unsigned int wait_line = 0x3fff;
	3596	+ unsigned int dma_en = 0;
	3597	+
	3598	+ if (channel->id >= 4)
	3599	+ return -EINVAL;
	3600	+
	3601	+ if (!channel->enable) {
	3602	+ rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id),
	3603	+ CSI_DISABLE_CAPTURE);
	3604	+ return 0;
	3605	+ }
	3606	+
	3607	+ rkcif_write_register_and(dev, CIF_REG_MIPI_LVDS_INTSTAT,
	3608	+ ~(CSI_START_INTSTAT(channel->id) \|
	3609	+ CSI_DMA_END_INTSTAT(channel->id) \|
	3610	+ CSI_LINE_INTSTAT_V1(channel->id)));
	3611	+
	3612	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3613	+ CSI_START_INTEN(channel->id));
	3614	+
	3615	+ if (priv && priv->mode.rdbk_mode && detect_stream->is_line_wake_up) {
	3616	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3617	+ CSI_LINE_INTEN_RK3588(channel->id));
	3618	+ wait_line = dev->wait_line;
	3619	+ }
	3620	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
	3621	+ wait_line << 16 \| wait_line);
	3622	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
	3623	+ wait_line << 16 \| wait_line);
	3624	+
	3625	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3626	+ CSI_DMA_END_INTEN(channel->id));
	3627	+ if (stream->cifdev->id_use_cnt == 0) {
	3628	+ val = CIF_MIPI_LVDS_SW_PRESS_VALUE_RK3588(0x3) \|
	3629	+ CIF_MIPI_LVDS_SW_PRESS_ENABLE \|
	3630	+ CIF_MIPI_LVDS_SW_HURRY_VALUE_RK3588(0x3) \|
	3631	+ CIF_MIPI_LVDS_SW_HURRY_ENABLE \|
	3632	+ CIF_MIPI_LVDS_SW_WATER_LINE_25 \|
	3633	+ CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
	3634	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY \|\|
	3635	+ mbus_type == V4L2_MBUS_CSI2_CPHY)
	3636	+ val &= ~CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106;
	3637	+ else
	3638	+ val \|= CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106;
	3639	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
	3640	+
	3641	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3642	+ CSI_ALL_ERROR_INTEN_V1);
	3643	+ }
	3644	+#if IS_ENABLED(CONFIG_CPU_RV1106)
	3645	+ if (channel->id == 1)
	3646	+ rv1106_sdmmc_get_lock();
	3647	+#endif
	3648	+ rkcif_write_register(dev, get_reg_index_of_id_ctrl1(channel->id),
	3649	+ channel->width \| (channel->height << 16));
	3650	+
	3651	+#if IS_ENABLED(CONFIG_CPU_RV1106)
	3652	+ if (channel->id == 1)
	3653	+ rv1106_sdmmc_put_lock();
	3654	+#endif
	3655	+
	3656	+ rkcif_write_register(dev, get_reg_index_of_frm0_y_vlw(channel->id),
	3657	+ channel->virtual_width);
	3658	+
	3659	+ if (channel->crop_en)
	3660	+ rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
	3661	+ channel->crop_st_y << 16 \| channel->crop_st_x);
	3662	+
	3663	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	3664	+ rkcif_assign_new_buffer_pingpong(stream,
	3665	+ RKCIF_YUV_ADDR_STATE_INIT,
	3666	+ channel->id);
	3667	+ else if (mode == RKCIF_STREAM_MODE_TOISP \|\|
	3668	+ mode == RKCIF_STREAM_MODE_TOISP_RDBK)
	3669	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	3670	+ RKCIF_YUV_ADDR_STATE_INIT,
	3671	+ channel->id);
	3672	+ else if (mode == RKCIF_STREAM_MODE_ROCKIT)
	3673	+ rkcif_assign_new_buffer_pingpong_rockit(stream,
	3674	+ RKCIF_YUV_ADDR_STATE_INIT,
	3675	+ channel->id);
	3676	+ if (stream->lack_buf_cnt == 2)
	3677	+ stream->dma_en = 0;
	3678	+
	3679	+ if (stream->dma_en) {
	3680	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY \|\|
	3681	+ mbus_type == V4L2_MBUS_CSI2_CPHY)
	3682	+ dma_en = CSI_DMA_ENABLE;
	3683	+ else
	3684	+ dma_en = LVDS_DMAEN_RV1106;
	3685	+ }
	3686	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY \|\|
	3687	+ mbus_type == V4L2_MBUS_CSI2_CPHY) {
	3688	+
	3689	+ if (stream->cifdev->hdr.esp.mode == HDR_LINE_CNT \|\|
	3690	+ stream->cifdev->hdr.esp.mode == HDR_ID_CODE)
	3691	+ channel->vc = 0;
	3692	+
	3693	+ val = CSI_ENABLE_CAPTURE \| dma_en \|
	3694	+ channel->cmd_mode_en << 26 \| CSI_ENABLE_CROP_V1 \|
	3695	+ channel->vc << 8 \| channel->data_type << 10 \|
	3696	+ channel->csi_fmt_val;
	3697	+
	3698	+ val \|= stream->cif_fmt_in->csi_yuv_order;
	3699	+ val \|= rkcif_csi_get_output_type_mask(stream);
	3700	+ if (stream->cifdev->hdr.hdr_mode == NO_HDR \|\|
	3701	+ stream->cifdev->hdr.hdr_mode == HDR_COMPR)
	3702	+ val \|= CSI_NO_HDR;
	3703	+ else if (stream->cifdev->hdr.hdr_mode == HDR_X2)
	3704	+ val \|= CSI_HDR2;
	3705	+ else if (stream->cifdev->hdr.hdr_mode == HDR_X3)
	3706	+ val \|= CSI_HDR3;
	3707	+ if (stream->cifdev->hdr.esp.mode == HDR_NORMAL_VC)
	3708	+ val \|= CSI_HDR_MODE_VC;
	3709	+ else if (stream->cifdev->hdr.esp.mode == HDR_LINE_CNT)
	3710	+ val \|= CSI_HDR_MODE_LINE_CNT;
	3711	+ else if (stream->cifdev->hdr.esp.mode == HDR_ID_CODE)
	3712	+ val \|= CSI_HDR_MODE_LINE_INFO;
	3713	+ if (stream->cifdev->hdr.hdr_mode != NO_HDR &&
	3714	+ stream->cifdev->hdr.esp.mode == HDR_NORMAL_VC)
	3715	+ val \|= CSI_HDR_VC_MODE_PROTECT;
	3716	+ if (stream->is_high_align)
	3717	+ val \|= CSI_HIGH_ALIGN_RK3588;
	3718	+ else
	3719	+ val &= ~CSI_HIGH_ALIGN_RK3588;
	3720	+ rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
	3721	+ rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID0, 0x02410251);
	3722	+ rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID1, 0x02420252);
	3723	+ } else if (mbus_type == V4L2_MBUS_CCP2) {
	3724	+ rkcif_csi_set_lvds_sav_eav(stream, channel);
	3725	+ val = LVDS_ENABLE_CAPTURE_RV1106 \| LVDS_MODE_RV1106(channel->lvds_cfg.mode) \|
	3726	+ LVDS_MAIN_LANE_RV1106(0) \| LVDS_FID_RV1106(0) \|
	3727	+ LVDS_LANES_ENABLED_RV1106(dev->active_sensor->lanes) \|
	3728	+ (channel->csi_fmt_val << 18) \|
	3729	+ rkcif_lvds_get_output_type_mask(stream) \|
	3730	+ (stream->cif_fmt_in->csi_yuv_order << 9) \|
	3731	+ dma_en;
	3732	+ if (stream->cifdev->hdr.hdr_mode == HDR_X3)
	3733	+ val \|= BIT(12);
	3734	+ rkcif_write_register(dev, get_reg_index_of_lvds_id_ctrl0(channel->id), val);
	3735	+ }
	3736	+ if (dev->chip_id >= CHIP_RV1106_CIF)
	3737	+ rkcif_modify_frame_skip_config(stream);
	3738	+ stream->cifdev->id_use_cnt++;
	3739	+ return 0;
	3740	+}
	3741	+
	3742	+static int rkcif_csi_stream_start(struct rkcif_stream *stream, unsigned int mode)
1970	3743	{
1971	3744	struct rkcif_device *dev = stream->cifdev;
1972	3745	struct rkcif_sensor_info *active_sensor = dev->active_sensor;
..	..	@@ -1975,22 +3748,20 @@
1975	3748	struct csi_channel_info *channel;
1976	3749	u32 ret = 0;
1977	3750
1978		- if (stream->state != RKCIF_STATE_RESET_IN_STREAMING)
	3751	+ if (stream->state < RKCIF_STATE_STREAMING) {
1979	3752	stream->frame_idx = 0;
	3753	+ stream->buf_wake_up_cnt = 0;
	3754	+ stream->frame_phase = 0;
	3755	+ stream->lack_buf_cnt = 0;
	3756	+ stream->is_in_vblank = false;
	3757	+ stream->is_change_toisp = false;
	3758	+ }
1980	3759
1981		- if (mbus_type == V4L2_MBUS_CSI2) {
1982		- rkcif_csi_get_vc_num(dev, flags);
	3760	+ rkcif_csi_get_vc_num(dev, flags);
1983	3761
1984		- channel = &dev->channels[stream->id];
1985		- channel->id = stream->id;
1986		- rkcif_csi_channel_init(stream, channel);
1987		- rkcif_csi_channel_set(stream, channel, V4L2_MBUS_CSI2);
1988		- } else if (mbus_type == V4L2_MBUS_CCP2) {
1989		- rkcif_csi_get_vc_num(dev, flags);
1990		-
1991		- channel = &dev->channels[stream->id];
1992		- channel->id = stream->id;
1993		-
	3762	+ channel = &dev->channels[stream->id];
	3763	+ channel->id = stream->id;
	3764	+ if (mbus_type == V4L2_MBUS_CCP2) {
1994	3765	ret = v4l2_subdev_call(dev->terminal_sensor.sd, core,
1995	3766	ioctl, RKMODULE_GET_LVDS_CFG,
1996	3767	&channel->lvds_cfg);
..	..	@@ -1998,18 +3769,55 @@
1998	3769	v4l2_err(&dev->v4l2_dev, "Err: get lvds config failed!!\n");
1999	3770	return ret;
2000	3771	}
2001		-
2002		- rkcif_csi_channel_init(stream, channel);
2003		- rkcif_csi_channel_set(stream, channel, V4L2_MBUS_CCP2);
2004	3772	}
2005		-
2006		- stream->line_int_cnt = 0;
2007		- if (stream->is_line_wake_up)
2008		- stream->is_can_stop = false;
2009		- else
2010		- stream->is_can_stop = true;
2011		- stream->state = RKCIF_STATE_STREAMING;
2012		- dev->workmode = RKCIF_WORKMODE_PINGPONG;
	3773	+ rkcif_csi_channel_init(stream, channel);
	3774	+ if (stream->state != RKCIF_STATE_STREAMING) {
	3775	+ if (mode == RKCIF_STREAM_MODE_CAPTURE) {
	3776	+ stream->dma_en \|= RKCIF_DMAEN_BY_VICAP;
	3777	+ } else if (mode == RKCIF_STREAM_MODE_TOISP_RDBK) {
	3778	+ stream->dma_en \|= RKCIF_DMAEN_BY_ISP;
	3779	+ } else if (mode == RKCIF_STREAM_MODE_TOISP) {
	3780	+ if (dev->hdr.hdr_mode == HDR_X2 &&
	3781	+ stream->id == 0)
	3782	+ stream->dma_en \|= RKCIF_DMAEN_BY_ISP;
	3783	+ else if (dev->hdr.hdr_mode == HDR_X3 && (stream->id == 0 \|\| stream->id == 1))
	3784	+ stream->dma_en \|= RKCIF_DMAEN_BY_ISP;
	3785	+ } else if (mode == RKCIF_STREAM_MODE_ROCKIT) {
	3786	+ stream->dma_en \|= RKCIF_DMAEN_BY_ROCKIT;
	3787	+ }
	3788	+ if (stream->cifdev->chip_id < CHIP_RK3588_CIF)
	3789	+ rkcif_csi_channel_set(stream, channel, mbus_type);
	3790	+ else
	3791	+ rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode);
	3792	+ } else {
	3793	+ if (stream->cifdev->chip_id >= CHIP_RK3588_CIF) {
	3794	+ if (mode == RKCIF_STREAM_MODE_CAPTURE) {
	3795	+ stream->to_en_dma = RKCIF_DMAEN_BY_VICAP;
	3796	+ } else if (mode == RKCIF_STREAM_MODE_TOISP_RDBK) {
	3797	+ stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
	3798	+ } else if (mode == RKCIF_STREAM_MODE_TOISP) {
	3799	+ if (dev->hdr.hdr_mode == HDR_X2 &&
	3800	+ stream->id == 0 &&
	3801	+ (!stream->dma_en))
	3802	+ stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
	3803	+ else if (dev->hdr.hdr_mode == HDR_X3 &&
	3804	+ (stream->id == 0 \|\| stream->id == 1) &&
	3805	+ (!stream->dma_en))
	3806	+ stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
	3807	+ } else if (mode == RKCIF_STREAM_MODE_ROCKIT) {
	3808	+ stream->to_en_dma = RKCIF_DMAEN_BY_ROCKIT;
	3809	+ }
	3810	+ }
	3811	+ }
	3812	+ if (stream->state != RKCIF_STATE_STREAMING) {
	3813	+ stream->line_int_cnt = 0;
	3814	+ if (stream->is_line_wake_up)
	3815	+ stream->is_can_stop = false;
	3816	+ else
	3817	+ stream->is_can_stop = true;
	3818	+ stream->state = RKCIF_STATE_STREAMING;
	3819	+ dev->workmode = RKCIF_WORKMODE_PINGPONG;
	3820	+ }
2013	3821
2014	3822	return 0;
2015	3823	}
..	..	@@ -2021,12 +3829,14 @@
2021	3829	u32 val;
2022	3830	int id;
2023	3831
2024		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	3832	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	3833	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
2025	3834	mbus_cfg->type == V4L2_MBUS_CCP2) {
2026	3835	id = stream->id;
2027	3836	val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(id));
2028		- if (mbus_cfg->type == V4L2_MBUS_CSI2)
2029		- val &= ~CSI_ENABLE_CAPTURE;
	3837	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	3838	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
	3839	+ val &= ~(CSI_ENABLE_CAPTURE \| CSI_DMA_ENABLE);
2030	3840	else
2031	3841	val &= ~LVDS_ENABLE_CAPTURE;
2032	3842
..	..	@@ -2042,8 +3852,17 @@
2042	3852	CSI_DMA_END_INTEN(id) \|
2043	3853	CSI_LINE_INTEN(id)));
2044	3854
2045		- rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
2046		- ~CSI_ALL_ERROR_INTEN);
	3855	+ if (stream->cifdev->chip_id < CHIP_RK3588_CIF) {
	3856	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
	3857	+ ~CSI_ALL_ERROR_INTEN);
	3858	+ } else {
	3859	+ if (stream->cifdev->id_use_cnt == 0) {
	3860	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
	3861	+ ~CSI_ALL_ERROR_INTEN_V1);
	3862	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
	3863	+ ~CSI_ENABLE_CAPTURE);
	3864	+ }
	3865	+ }
2047	3866
2048	3867	} else {
2049	3868	if (atomic_read(&cif_dev->pipe.stream_cnt) == 1) {
..	..	@@ -2053,16 +3872,18 @@
2053	3872	rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, 0x0);
2054	3873	rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, 0x3ff);
2055	3874	rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS, 0x0);
	3875	+ if (IS_ENABLED(CONFIG_CPU_RV1106))
	3876	+ rkcif_config_dvp_pin(cif_dev, false);
2056	3877	}
2057		- stream->is_dvp_yuv_addr_init = false;
2058	3878	}
2059		-
	3879	+ stream->cifdev->id_use_cnt--;
2060	3880	stream->state = RKCIF_STATE_READY;
	3881	+ stream->dma_en = 0;
2061	3882	}
2062	3883
2063	3884	static bool rkcif_is_extending_line_for_height(struct rkcif_device *dev,
2064		- struct rkcif_stream *stream,
2065		- const struct cif_input_fmt *fmt)
	3885	+ struct rkcif_stream *stream,
	3886	+ const struct cif_input_fmt *fmt)
2066	3887	{
2067	3888	bool is_extended = false;
2068	3889	struct rkmodule_hdr_cfg hdr_cfg;
..	..	@@ -2076,17 +3897,17 @@
2076	3897	RKMODULE_GET_HDR_CFG,
2077	3898	&hdr_cfg);
2078	3899	if (!ret)
2079		- dev->hdr.mode = hdr_cfg.hdr_mode;
	3900	+ dev->hdr = hdr_cfg;
2080	3901	else
2081		- dev->hdr.mode = NO_HDR;
	3902	+ dev->hdr.hdr_mode = NO_HDR;
2082	3903	}
2083	3904
2084	3905	if (fmt && fmt->fmt_type == CIF_FMT_TYPE_RAW) {
2085		- if ((dev->hdr.mode == HDR_X2 &&
	3906	+ if ((dev->hdr.hdr_mode == HDR_X2 &&
2086	3907	stream->id == RKCIF_STREAM_MIPI_ID1) \|\|
2087		- (dev->hdr.mode == HDR_X3 &&
	3908	+ (dev->hdr.hdr_mode == HDR_X3 &&
2088	3909	stream->id == RKCIF_STREAM_MIPI_ID2) \|\|
2089		- (dev->hdr.mode == NO_HDR)) {
	3910	+ (dev->hdr.hdr_mode == NO_HDR)) {
2090	3911	is_extended = true;
2091	3912	}
2092	3913	}
..	..	@@ -2143,67 +3964,103 @@
2143	3964	}
2144	3965
2145	3966	static void rkcif_check_buffer_update_pingpong(struct rkcif_stream *stream,
2146		- int channel_id)
	3967	+ int channel_id)
2147	3968	{
2148	3969	struct rkcif_device *dev = stream->cifdev;
2149	3970	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2150	3971	struct rkcif_buffer *buffer = NULL;
2151		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
2152		- u32 frm_addr_y, frm_addr_uv;
	3972	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
	3973	+ u32 frm_addr_y = 0, frm_addr_uv = 0;
	3974	+ u32 frm0_addr_y = 0, frm0_addr_uv = 0;
	3975	+ u32 frm1_addr_y = 0, frm1_addr_uv = 0;
2153	3976	unsigned long flags;
	3977	+ int frame_phase = 0;
	3978	+ bool is_dual_update_buf = false;
2154	3979
	3980	+ spin_lock_irqsave(&stream->vbq_lock, flags);
2155	3981	if (stream->state == RKCIF_STATE_STREAMING &&
2156		- stream->curr_buf == stream->next_buf &&
2157		- stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED &&
2158		- (!dummy_buf->vaddr)) {
2159		- if (!stream->is_line_wake_up) {
2160		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	3982	+ ((stream->curr_buf == stream->next_buf &&
	3983	+ stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED &&
	3984	+ (!dummy_buf->vaddr)) \|\|
	3985	+ stream->curr_buf == NULL \|\|
	3986	+ stream->next_buf == NULL)) {
	3987	+ frame_phase = stream->frame_phase_cache;
	3988	+ if (!stream->is_line_wake_up \|\|
	3989	+ (stream->is_line_wake_up && stream->frame_idx < 2)) {
	3990	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	3991	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
2161	3992	mbus_cfg->type == V4L2_MBUS_CCP2) {
2162		- frm_addr_y = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2163		- get_reg_index_of_frm0_y_addr(channel_id) :
2164		- get_reg_index_of_frm1_y_addr(channel_id);
2165		- frm_addr_uv = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2166		- get_reg_index_of_frm0_uv_addr(channel_id) :
2167		- get_reg_index_of_frm1_uv_addr(channel_id);
	3993	+ frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
	3994	+ frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
	3995	+ frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
	3996	+ frm1_addr_uv = get_reg_index_of_frm1_uv_addr(channel_id);
2168	3997	} else {
2169		- frm_addr_y = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2170		- get_dvp_reg_index_of_frm0_y_addr(channel_id) :
2171		- get_dvp_reg_index_of_frm1_y_addr(channel_id);
2172		- frm_addr_uv = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2173		- get_dvp_reg_index_of_frm0_uv_addr(channel_id) :
2174		- get_dvp_reg_index_of_frm1_uv_addr(channel_id);
	3998	+ frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
	3999	+ frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
	4000	+ frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(channel_id);
	4001	+ frm1_addr_uv = get_dvp_reg_index_of_frm1_uv_addr(channel_id);
2175	4002	}
2176		- v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
2177		- "stream[%d] update buf in %s, stream->frame_phase_cache %d\n",
2178		- stream->id, __func__, stream->frame_phase_cache);
2179		- spin_lock_irqsave(&stream->vbq_lock, flags);
	4003	+ if (frame_phase & CIF_CSI_FRAME0_READY) {
	4004	+ frm_addr_y = frm0_addr_y;
	4005	+ frm_addr_uv = frm0_addr_uv;
	4006	+ } else {
	4007	+ frm_addr_y = frm1_addr_y;
	4008	+ frm_addr_uv = frm1_addr_uv;
	4009	+ }
	4010	+ if (!stream->dma_en && stream->curr_buf == NULL && stream->next_buf == NULL)
	4011	+ is_dual_update_buf = true;
2180	4012	if (!list_empty(&stream->buf_head)) {
2181		- if (stream->frame_phase_cache == CIF_CSI_FRAME0_READY) {
	4013	+ if (frame_phase == CIF_CSI_FRAME0_READY) {
2182	4014	stream->curr_buf = list_first_entry(&stream->buf_head,
2183	4015	struct rkcif_buffer, queue);
2184	4016	if (stream->curr_buf) {
2185	4017	list_del(&stream->curr_buf->queue);
2186	4018	buffer = stream->curr_buf;
2187	4019	}
2188		- } else if (stream->frame_phase_cache == CIF_CSI_FRAME1_READY) {
2189		- stream->next_buf = list_first_entry(&stream->buf_head,
	4020	+ if (buffer && is_dual_update_buf)
	4021	+ stream->next_buf = buffer;
	4022	+ } else if (frame_phase == CIF_CSI_FRAME1_READY) {
	4023	+ if (stream->next_buf == NULL &&
	4024	+ stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	4025	+ stream->next_buf = stream->curr_buf;
	4026	+ } else {
	4027	+ stream->next_buf = list_first_entry(&stream->buf_head,
2190	4028	struct rkcif_buffer, queue);
2191		- if (stream->next_buf) {
2192		- list_del(&stream->next_buf->queue);
2193		- buffer = stream->next_buf;
	4029	+ if (stream->next_buf) {
	4030	+ list_del(&stream->next_buf->queue);
	4031	+ buffer = stream->next_buf;
	4032	+ }
	4033	+ if (buffer && is_dual_update_buf)
	4034	+ stream->curr_buf = buffer;
2194	4035	}
2195	4036	}
	4037	+ } else {
	4038	+ v4l2_info(&dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
2196	4039	}
2197		- spin_unlock_irqrestore(&stream->vbq_lock, flags);
2198	4040	if (buffer) {
2199		- rkcif_write_register(dev, frm_addr_y,
2200		- buffer->buff_addr[RKCIF_PLANE_Y]);
2201		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2202		- rkcif_write_register(dev, frm_addr_uv,
2203		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	4041	+ if (is_dual_update_buf) {
	4042	+ rkcif_write_register(dev, frm0_addr_y,
	4043	+ buffer->buff_addr[RKCIF_PLANE_Y]);
	4044	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4045	+ rkcif_write_register(dev, frm0_addr_uv,
	4046	+ buffer->buff_addr[RKCIF_PLANE_CBCR]);
	4047	+ rkcif_write_register(dev, frm1_addr_y,
	4048	+ buffer->buff_addr[RKCIF_PLANE_Y]);
	4049	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4050	+ rkcif_write_register(dev, frm1_addr_uv,
	4051	+ buffer->buff_addr[RKCIF_PLANE_CBCR]);
	4052	+ } else {
	4053	+ rkcif_write_register(dev, frm_addr_y,
	4054	+ buffer->buff_addr[RKCIF_PLANE_Y]);
	4055	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4056	+ rkcif_write_register(dev, frm_addr_uv,
	4057	+ buffer->buff_addr[RKCIF_PLANE_CBCR]);
	4058	+ }
2204	4059	}
2205	4060	} else {
2206		- spin_lock_irqsave(&stream->vbq_lock, flags);
	4061	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4062	+ "%s %d, is_wake_up %d, frame_idx %d\n",
	4063	+ __func__, __LINE__, stream->is_line_wake_up, stream->frame_idx);
2207	4064	if (stream->curr_buf == stream->next_buf) {
2208	4065	if (stream->frame_phase_cache == CIF_CSI_FRAME0_READY) {
2209	4066	stream->curr_buf = list_first_entry(&stream->buf_head,
..	..	@@ -2218,16 +4075,43 @@
2218	4075	}
2219	4076	stream->is_buf_active = true;
2220	4077	}
2221		- spin_unlock_irqrestore(&stream->vbq_lock, flags);
2222	4078	}
	4079	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4080	+ "%s, stream[%d] update buffer, frame_phase %d, is_stop %s, lack_buf_cnt %d\n",
	4081	+ __func__, stream->id, frame_phase,
	4082	+ (stream->dma_en ? "false" : "true"),
	4083	+ stream->lack_buf_cnt);
	4084	+ if (!stream->dma_en) {
	4085	+ if (stream->to_stop_dma) {
	4086	+ stream->to_stop_dma = 0;
	4087	+ wake_up(&stream->wq_stopped);
	4088	+ } else {
	4089	+ stream->to_en_dma = RKCIF_DMAEN_BY_VICAP;
	4090	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4091	+ "%s stream[%d] start dma capture, frame cnt %d\n",
	4092	+ __func__, stream->id, stream->frame_idx);
	4093	+ }
	4094	+ } else {
	4095	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4096	+ "%s %d, dma_en 0x%x, frame cnt %d\n",
	4097	+ __func__, __LINE__, stream->dma_en, stream->frame_idx);
	4098	+ }
	4099	+ if (stream->lack_buf_cnt)
	4100	+ stream->lack_buf_cnt--;
	4101	+ } else {
	4102	+ v4l2_info(&dev->v4l2_dev, "%s %d, state %d, curr_buf %p, next_buf %p\n",
	4103	+ __func__, __LINE__, stream->state, stream->curr_buf, stream->next_buf);
2223	4104	}
	4105	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	4106	+ if (stream->to_en_dma)
	4107	+ rkcif_enable_dma_capture(stream, true);
2224	4108	}
2225	4109
2226	4110	/*
2227	4111	* The vb2_buffer are stored in rkcif_buffer, in order to unify
2228	4112	* mplane buffer and none-mplane buffer.
2229	4113	*/
2230		-static void rkcif_buf_queue(struct vb2_buffer *vb)
	4114	+void rkcif_buf_queue(struct vb2_buffer *vb)
2231	4115	{
2232	4116	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2233	4117	struct rkcif_buffer *cifbuf = to_rkcif_buffer(vbuf);
..	..	@@ -2236,8 +4120,32 @@
2236	4120	struct v4l2_pix_format_mplane *pixm = &stream->pixm;
2237	4121	const struct cif_output_fmt *fmt = stream->cif_fmt_out;
2238	4122	struct rkcif_hw *hw_dev = stream->cifdev->hw_dev;
	4123	+ struct rkcif_tools_buffer *tools_buf;
	4124	+ struct rkcif_tools_vdev *tools_vdev = stream->tools_vdev;
2239	4125	unsigned long flags;
2240	4126	int i;
	4127	+ bool is_find_tools_buf = false;
	4128	+
	4129	+ if (tools_vdev) {
	4130	+ spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
	4131	+ if (!list_empty(&tools_vdev->src_buf_head)) {
	4132	+ list_for_each_entry(tools_buf, &tools_vdev->src_buf_head, list) {
	4133	+ if (tools_buf->vb == vbuf) {
	4134	+ is_find_tools_buf = true;
	4135	+ break;
	4136	+ }
	4137	+ }
	4138	+ if (is_find_tools_buf) {
	4139	+ if (tools_buf->use_cnt)
	4140	+ tools_buf->use_cnt--;
	4141	+ if (tools_buf->use_cnt) {
	4142	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
	4143	+ return;
	4144	+ }
	4145	+ }
	4146	+ }
	4147	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
	4148	+ }
2241	4149
2242	4150	memset(cifbuf->buff_addr, 0, sizeof(cifbuf->buff_addr));
2243	4151	/* If mplanes > 1, every c-plane has its own m-plane,
..	..	@@ -2246,7 +4154,7 @@
2246	4154	for (i = 0; i < fmt->mplanes; i++) {
2247	4155	void *addr = vb2_plane_vaddr(vb, i);
2248	4156
2249		- if (hw_dev->iommu_en) {
	4157	+ if (hw_dev->is_dma_sg_ops) {
2250	4158	struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, i);
2251	4159
2252	4160	cifbuf->buff_addr[i] = sg_dma_address(sgt->sgl);
..	..	@@ -2255,7 +4163,7 @@
2255	4163	}
2256	4164	if (rkcif_debug && addr && !hw_dev->iommu_en) {
2257	4165	memset(addr, 0, pixm->plane_fmt[i].sizeimage);
2258		- v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
	4166	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
2259	4167	"Clear buffer, size: 0x%08x\n",
2260	4168	pixm->plane_fmt[i].sizeimage);
2261	4169	}
..	..	@@ -2269,40 +4177,221 @@
2269	4177	spin_lock_irqsave(&stream->vbq_lock, flags);
2270	4178	list_add_tail(&cifbuf->queue, &stream->buf_head);
2271	4179	spin_unlock_irqrestore(&stream->vbq_lock, flags);
2272		- if (stream->cifdev->workmode == RKCIF_WORKMODE_PINGPONG)
	4180	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP && (!cifbuf->dbuf)) {
	4181	+ struct rkisp_rx_buf *dbufs = NULL;
	4182	+
	4183	+ dbufs = kzalloc(sizeof(struct rkisp_rx_buf), GFP_KERNEL);
	4184	+
	4185	+ memset(dbufs, 0, sizeof(struct rkisp_rx_buf));
	4186	+ if (stream->cifdev->hdr.hdr_mode == HDR_X2 && stream->id == 0)
	4187	+ dbufs->type = BUF_MIDDLE;
	4188	+ else if (stream->cifdev->hdr.hdr_mode == HDR_X3 && stream->id == 0)
	4189	+ dbufs->type = BUF_LONG;
	4190	+ else if (stream->cifdev->hdr.hdr_mode == HDR_X3 && stream->id == 1)
	4191	+ dbufs->type = BUF_MIDDLE;
	4192	+ cifbuf->dbuf = hw_dev->mem_ops->get_dmabuf(vb->planes[0].mem_priv, O_RDWR);
	4193	+ if (cifbuf->dbuf)
	4194	+ dbufs->dbuf = cifbuf->dbuf;
	4195	+ list_add_tail(&dbufs->list, &stream->rx_buf_head_vicap);
	4196	+ }
	4197	+ if (stream->cifdev->workmode == RKCIF_WORKMODE_PINGPONG &&
	4198	+ stream->lack_buf_cnt)
2273	4199	rkcif_check_buffer_update_pingpong(stream, stream->id);
	4200	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4201	+ "stream[%d] buf queue, index: %d, dma_addr 0x%x\n",
	4202	+ stream->id, vb->index, cifbuf->buff_addr[0]);
	4203	+}
	4204	+
	4205	+void rkcif_free_rx_buf(struct rkcif_stream *stream, int buf_num)
	4206	+{
	4207	+ struct rkcif_rx_buffer *buf;
	4208	+ struct rkcif_device *dev = stream->cifdev;
	4209	+ struct sditf_priv *priv = dev->sditf[0];
	4210	+ int i = 0;
	4211	+ unsigned long flags;
	4212	+
	4213	+ if (!priv)
	4214	+ return;
	4215	+
	4216	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	4217	+ stream->curr_buf_toisp = NULL;
	4218	+ stream->next_buf_toisp = NULL;
	4219	+ INIT_LIST_HEAD(&stream->rx_buf_head);
	4220	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	4221	+
	4222	+ if (dev->is_thunderboot)
	4223	+ spin_lock_irqsave(&dev->buffree_lock, flags);
	4224	+ for (i = 0; i < buf_num; i++) {
	4225	+ buf = &stream->rx_buf[i];
	4226	+ if (buf->dummy.is_free)
	4227	+ continue;
	4228	+ if (!dev->is_thunderboot)
	4229	+ rkcif_free_buffer(dev, &buf->dummy);
	4230	+ else
	4231	+ list_add_tail(&buf->list_free, &priv->buf_free_list);
	4232	+ }
	4233	+
	4234	+ if (dev->is_thunderboot) {
	4235	+ spin_unlock_irqrestore(&dev->buffree_lock, flags);
	4236	+ schedule_work(&priv->buffree_work.work);
	4237	+ }
	4238	+ stream->dma_en &= ~RKCIF_DMAEN_BY_ISP;
2274	4239	v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
2275		- "stream[%d] buf queue, index: %d\n",
2276		- stream->id, vb->index);
	4240	+ "free rx_buf, buf_num %d\n", buf_num);
	4241	+}
	4242	+
	4243	+int rkcif_init_rx_buf(struct rkcif_stream *stream, int buf_num)
	4244	+{
	4245	+ struct rkcif_device *dev = stream->cifdev;
	4246	+ struct v4l2_pix_format_mplane *pixm = &stream->pixm;
	4247	+ struct rkcif_dummy_buffer *dummy;
	4248	+ struct rkcif_rx_buffer *buf;
	4249	+ struct sditf_priv *priv = dev->sditf[0];
	4250	+ int frm_type = 0;
	4251	+ int i = 0;
	4252	+ int ret = 0;
	4253	+
	4254	+ if (!priv)
	4255	+ return -EINVAL;
	4256	+
	4257	+ if (buf_num > RKISP_VICAP_BUF_CNT_MAX)
	4258	+ return -EINVAL;
	4259	+
	4260	+ if (dev->hdr.hdr_mode == NO_HDR) {
	4261	+ if (stream->id == 0)
	4262	+ frm_type = BUF_SHORT;
	4263	+ else
	4264	+ return -EINVAL;
	4265	+ } else if (dev->hdr.hdr_mode == HDR_X2) {
	4266	+ if (stream->id == 0)
	4267	+ frm_type = BUF_MIDDLE;
	4268	+ else if (stream->id == 1)
	4269	+ frm_type = BUF_SHORT;
	4270	+ else
	4271	+ return -EINVAL;
	4272	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
	4273	+ if (stream->id == 0)
	4274	+ frm_type = BUF_LONG;
	4275	+ else if (stream->id == 1)
	4276	+ frm_type = BUF_MIDDLE;
	4277	+ else if (stream->id == 2)
	4278	+ frm_type = BUF_SHORT;
	4279	+ else
	4280	+ return -EINVAL;
	4281	+ }
	4282	+ while (true) {
	4283	+ buf = &stream->rx_buf[i];
	4284	+ memset(buf, 0, sizeof(*buf));
	4285	+ dummy = &buf->dummy;
	4286	+ dummy->size = pixm->plane_fmt[0].sizeimage;
	4287	+ dummy->is_need_vaddr = true;
	4288	+ dummy->is_need_dbuf = true;
	4289	+ if (dev->is_thunderboot) {
	4290	+ buf->buf_idx = i;
	4291	+ ret = rkcif_alloc_reserved_mem_buf(dev, buf);
	4292	+ if (ret) {
	4293	+ priv->buf_num = i;
	4294	+ v4l2_info(&dev->v4l2_dev,
	4295	+ "reserved mem support alloc buf num %d, require buf num %d\n",
	4296	+ i, buf_num);
	4297	+ break;
	4298	+ }
	4299	+ if (dev->rdbk_debug)
	4300	+ v4l2_info(&dev->v4l2_dev,
	4301	+ "stream[%d] buf addr 0x%llx\n",
	4302	+ stream->id, (u64)dummy->dma_addr);
	4303	+ } else {
	4304	+ ret = rkcif_alloc_buffer(dev, dummy);
	4305	+ if (ret) {
	4306	+ priv->buf_num = i;
	4307	+ v4l2_info(&dev->v4l2_dev,
	4308	+ "alloc buf num %d, require buf num %d\n",
	4309	+ i, buf_num);
	4310	+ break;
	4311	+ }
	4312	+ buf->dbufs.dbuf = dummy->dbuf;
	4313	+ }
	4314	+ buf->dbufs.is_init = false;
	4315	+ buf->dbufs.type = frm_type;
	4316	+ list_add_tail(&buf->list, &stream->rx_buf_head);
	4317	+ dummy->is_free = false;
	4318	+ if (stream->is_compact)
	4319	+ buf->dbufs.is_uncompact = false;
	4320	+ else
	4321	+ buf->dbufs.is_uncompact = true;
	4322	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE && i == 0) {
	4323	+ buf->dbufs.is_first = true;
	4324	+ rkcif_s_rx_buffer(dev, &buf->dbufs);
	4325	+ stream->buf_num_toisp--;
	4326	+ }
	4327	+ i++;
	4328	+ if (!dev->is_thunderboot && i >= buf_num) {
	4329	+ break;
	4330	+ } else if (i >= RKISP_VICAP_BUF_CNT_MAX) {
	4331	+ priv->buf_num = i;
	4332	+ v4l2_info(&dev->v4l2_dev,
	4333	+ "reserved mem alloc buf num %d\n", i);
	4334	+ break;
	4335	+ }
	4336	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
	4337	+ "init rx_buf,dma_addr 0x%llx size: 0x%x\n",
	4338	+ (u64)dummy->dma_addr, pixm->plane_fmt[0].sizeimage);
	4339	+ }
	4340	+ if (priv->buf_num) {
	4341	+ stream->buf_num_toisp = priv->buf_num;
	4342	+ return 0;
	4343	+ } else {
	4344	+ return -EINVAL;
	4345	+ }
2277	4346	}
2278	4347
2279	4348	static int rkcif_create_dummy_buf(struct rkcif_stream *stream)
2280	4349	{
2281		- u32 fourcc;
2282	4350	struct rkcif_device *dev = stream->cifdev;
2283		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
2284		- struct rkcif_hw *hw_dev = dev->hw_dev;
	4351	+ struct rkcif_hw *hw = dev->hw_dev;
	4352	+ struct rkcif_dummy_buffer *dummy_buf = &hw->dummy_buf;
	4353	+ struct rkcif_device *tmp_dev = NULL;
	4354	+ struct v4l2_subdev_frame_interval_enum fie;
	4355	+ u32 max_size = 0;
	4356	+ u32 size = 0;
	4357	+ int ret = 0;
	4358	+ int i, j;
2285	4359
2286		- /* get a maximum plane size */
2287		- dummy_buf->size = max3(stream->pixm.plane_fmt[0].bytesperline *
2288		- stream->pixm.height,
2289		- stream->pixm.plane_fmt[1].sizeimage,
2290		- stream->pixm.plane_fmt[2].sizeimage);
2291		- /*
2292		- * rk cif don't support output yuyv fmt data
2293		- * if user request yuyv fmt, the input mode must be RAW8
2294		- * and the width is double Because the real input fmt is
2295		- * yuyv
2296		- */
2297		- fourcc = stream->cif_fmt_out->fourcc;
2298		- if (fourcc == V4L2_PIX_FMT_YUYV \|\| fourcc == V4L2_PIX_FMT_YVYU \|\|
2299		- fourcc == V4L2_PIX_FMT_UYVY \|\| fourcc == V4L2_PIX_FMT_VYUY)
2300		- dummy_buf->size *= 2;
	4360	+ for (i = 0; i < hw->dev_num; i++) {
	4361	+ tmp_dev = hw->cif_dev[i];
	4362	+ if (tmp_dev->terminal_sensor.sd) {
	4363	+ for (j = 0; j < 32; j++) {
	4364	+ memset(&fie, 0, sizeof(fie));
	4365	+ fie.index = j;
	4366	+ fie.pad = 0;
	4367	+ fie.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	4368	+ ret = v4l2_subdev_call(tmp_dev->terminal_sensor.sd,
	4369	+ pad, enum_frame_interval,
	4370	+ NULL, &fie);
	4371	+ if (!ret) {
	4372	+ if (fie.code == MEDIA_BUS_FMT_RGB888_1X24)
	4373	+ size = fie.width * fie.height * 3;
	4374	+ else
	4375	+ size = fie.width * fie.height * 2;
	4376	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
	4377	+ "%s enum fmt, width %d, height %d\n",
	4378	+ __func__, fie.width, fie.height);
	4379	+ } else {
	4380	+ break;
	4381	+ }
	4382	+ if (size > max_size)
	4383	+ max_size = size;
	4384	+ }
	4385	+ } else {
	4386	+ continue;
	4387	+ }
	4388	+ }
	4389	+ dummy_buf->size = max_size;
2301	4390
2302		- dummy_buf->vaddr = dma_alloc_coherent(hw_dev->dev, dummy_buf->size,
2303		- &dummy_buf->dma_addr,
2304		- GFP_KERNEL);
2305		- if (!dummy_buf->vaddr) {
	4391	+ dummy_buf->is_need_vaddr = true;
	4392	+ dummy_buf->is_need_dbuf = true;
	4393	+ ret = rkcif_alloc_buffer(dev, dummy_buf);
	4394	+ if (ret) {
2306	4395	v4l2_err(&dev->v4l2_dev,
2307	4396	"Failed to allocate the memory for dummy buffer\n");
2308	4397	return -ENOMEM;
..	..	@@ -2311,18 +4400,16 @@
2311	4400	v4l2_info(&dev->v4l2_dev, "Allocate dummy buffer, size: 0x%08x\n",
2312	4401	dummy_buf->size);
2313	4402
2314		- return 0;
	4403	+ return ret;
2315	4404	}
2316	4405
2317	4406	static void rkcif_destroy_dummy_buf(struct rkcif_stream *stream)
2318	4407	{
2319	4408	struct rkcif_device *dev = stream->cifdev;
2320		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
2321		- struct rkcif_hw *hw_dev = dev->hw_dev;
	4409	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
2322	4410
2323	4411	if (dummy_buf->vaddr)
2324		- dma_free_coherent(hw_dev->dev, dummy_buf->size,
2325		- dummy_buf->vaddr, dummy_buf->dma_addr);
	4412	+ rkcif_free_buffer(dev, dummy_buf);
2326	4413	dummy_buf->dma_addr = 0;
2327	4414	dummy_buf->vaddr = NULL;
2328	4415	}
..	..	@@ -2336,7 +4423,7 @@
2336	4423	if (dev->luma_vdev.enable)
2337	4424	rkcif_stop_luma(&dev->luma_vdev);
2338	4425
2339		- if (dev->hdr.mode != NO_HDR) {
	4426	+ if (dev->hdr.hdr_mode != NO_HDR) {
2340	4427	if (dev->chip_id == CHIP_RK1808_CIF) {
2341	4428	val = rkcif_read_register(dev, CIF_REG_MIPI_WATER_LINE);
2342	4429	val \|= CIF_MIPI_LVDS_SW_DMA_IDLE_RK1808;
..	..	@@ -2360,14 +4447,22 @@
2360	4447	reset_control_deassert(cif_hw->cif_rst[i]);
2361	4448
2362	4449	if (cif_hw->iommu_en) {
2363		- struct iommu_domain *domain;
2364		-
2365		- domain = iommu_get_domain_for_dev(cif_hw->dev);
2366		- if (domain) {
2367		- iommu_detach_device(domain, cif_hw->dev);
2368		- iommu_attach_device(domain, cif_hw->dev);
2369		- }
	4450	+ rockchip_iommu_disable(cif_hw->dev);
	4451	+ rockchip_iommu_enable(cif_hw->dev);
2370	4452	}
	4453	+}
	4454	+
	4455	+void rkcif_do_soft_reset(struct rkcif_device *dev)
	4456	+{
	4457	+ if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	4458	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	4459	+ dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)
	4460	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_CTRL, 0x000A0000);
	4461	+ else
	4462	+ rkcif_write_register_or(dev, CIF_REG_DVP_CTRL, 0x000A0000);
	4463	+ usleep_range(10, 20);
	4464	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
	4465	+ "vicap do soft reset 0x%x\n", 0x000A0000);
2371	4466	}
2372	4467
2373	4468	static void rkcif_release_rdbk_buf(struct rkcif_stream *stream)
..	..	@@ -2412,9 +4507,52 @@
2412	4507
2413	4508	}
2414	4509
2415		-static void rkcif_stop_streaming(struct vb2_queue *queue)
	4510	+static void rkcif_detach_sync_mode(struct rkcif_device *cif_dev)
2416	4511	{
2417		- struct rkcif_stream *stream = queue->drv_priv;
	4512	+ int i = 0;
	4513	+ struct rkcif_hw *hw = cif_dev->hw_dev;
	4514	+ struct rkcif_device *tmp_dev;
	4515	+ struct rkcif_multi_sync_config *sync_config;
	4516	+
	4517	+ if ((!cif_dev->sync_cfg.type) \|\|
	4518	+ (atomic_read(&cif_dev->pipe.stream_cnt) != 0))
	4519	+ return;
	4520	+ mutex_lock(&hw->dev_lock);
	4521	+ memset(&cif_dev->sync_cfg, 0, sizeof(cif_dev->sync_cfg));
	4522	+ sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
	4523	+ sync_config->streaming_cnt--;
	4524	+ if (cif_dev->sync_cfg.type == EXTERNAL_MASTER_MODE) {
	4525	+ for (i = 0; i < sync_config->ext_master.count; i++) {
	4526	+ tmp_dev = sync_config->ext_master.cif_dev[i];
	4527	+ if (tmp_dev == cif_dev) {
	4528	+ sync_config->ext_master.is_streaming[i] = false;
	4529	+ break;
	4530	+ }
	4531	+ }
	4532	+ }
	4533	+ if (cif_dev->sync_cfg.type == INTERNAL_MASTER_MODE)
	4534	+ sync_config->int_master.is_streaming[0] = false;
	4535	+ if (cif_dev->sync_cfg.type == SLAVE_MODE) {
	4536	+ for (i = 0; i < sync_config->slave.count; i++) {
	4537	+ tmp_dev = sync_config->slave.cif_dev[i];
	4538	+ if (tmp_dev == cif_dev) {
	4539	+ sync_config->slave.is_streaming[i] = false;
	4540	+ break;
	4541	+ }
	4542	+ }
	4543	+ }
	4544	+
	4545	+ if (!sync_config->streaming_cnt && sync_config->is_attach) {
	4546	+ sync_config->is_attach = false;
	4547	+ sync_config->mode = RKCIF_NOSYNC_MODE;
	4548	+ sync_config->dev_cnt = 0;
	4549	+ }
	4550	+ mutex_unlock(&hw->dev_lock);
	4551	+}
	4552	+
	4553	+void rkcif_do_stop_stream(struct rkcif_stream *stream,
	4554	+ unsigned int mode)
	4555	+{
2418	4556	struct rkcif_vdev_node *node = &stream->vnode;
2419	4557	struct rkcif_device *dev = stream->cifdev;
2420	4558	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
..	..	@@ -2424,95 +4562,164 @@
2424	4562	bool can_reset = true;
2425	4563	int i;
2426	4564	unsigned long flags;
	4565	+ u32 vblank = 0;
	4566	+ u32 frame_time_ns = 0;
	4567	+ u64 cur_time = 0;
	4568	+ u64 fs_time = 0;
2427	4569
2428	4570	mutex_lock(&dev->stream_lock);
2429	4571
2430		- v4l2_info(&dev->v4l2_dev, "stream[%d] start stopping\n", stream->id);
	4572	+ v4l2_info(&dev->v4l2_dev, "stream[%d] start stopping, total mode 0x%x, cur 0x%x\n",
	4573	+ stream->id, stream->cur_stream_mode, mode);
2431	4574
2432		- stream->stopping = true;
	4575	+ if (mode == stream->cur_stream_mode) {
	4576	+ if (stream->dma_en) {
	4577	+ if (!dev->sensor_linetime)
	4578	+ dev->sensor_linetime = rkcif_get_linetime(stream);
	4579	+ vblank = rkcif_get_sensor_vblank(dev);
	4580	+ if (vblank) {
	4581	+ frame_time_ns = (vblank + dev->terminal_sensor.raw_rect.height) *
	4582	+ dev->sensor_linetime;
	4583	+ spin_lock_irqsave(&stream->fps_lock, flags);
	4584	+ fs_time = stream->readout.fs_timestamp;
	4585	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	4586	+ cur_time = ktime_get_ns();
	4587	+ if (cur_time > fs_time &&
	4588	+ cur_time - fs_time < (frame_time_ns - 10000000)) {
	4589	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	4590	+ if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
	4591	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	4592	+ else if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
	4593	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	4594	+ stream->is_stop_capture = true;
	4595	+ rkcif_stop_dma_capture(stream);
	4596	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	4597	+ }
	4598	+ }
	4599	+ }
	4600	+ stream->stopping = true;
	4601	+ ret = wait_event_timeout(stream->wq_stopped,
	4602	+ stream->state != RKCIF_STATE_STREAMING,
	4603	+ msecs_to_jiffies(500));
	4604	+ if (!ret) {
	4605	+ rkcif_stream_stop(stream);
	4606	+ stream->stopping = false;
	4607	+ }
2433	4608
2434		- ret = wait_event_timeout(stream->wq_stopped,
2435		- stream->state != RKCIF_STATE_STREAMING,
2436		- msecs_to_jiffies(1000));
2437		- if (!ret) {
2438		- rkcif_stream_stop(stream);
2439		- stream->stopping = false;
	4609	+ media_pipeline_stop(&node->vdev.entity);
	4610	+ ret = dev->pipe.set_stream(&dev->pipe, false);
	4611	+ if (ret < 0)
	4612	+ v4l2_err(v4l2_dev, "pipeline stream-off failed error:%d\n",
	4613	+ ret);
	4614	+
	4615	+ dev->is_start_hdr = false;
	4616	+ stream->is_dvp_yuv_addr_init = false;
	4617	+ if (stream->skip_info.skip_en) {
	4618	+ stream->skip_info.skip_en = false;
	4619	+ stream->skip_info.skip_to_en = true;
	4620	+ }
	4621	+ } else if (mode == RKCIF_STREAM_MODE_CAPTURE && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
	4622	+ //only stop dma
	4623	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	4624	+ wait_event_timeout(stream->wq_stopped,
	4625	+ stream->to_stop_dma != RKCIF_DMAEN_BY_VICAP,
	4626	+ msecs_to_jiffies(1000));
	4627	+ } else if (mode == RKCIF_STREAM_MODE_TOISP && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
	4628	+ //only stop dma
	4629	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	4630	+ wait_event_timeout(stream->wq_stopped,
	4631	+ stream->to_stop_dma != RKCIF_DMAEN_BY_ISP,
	4632	+ msecs_to_jiffies(1000));
	4633	+ }
	4634	+ if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE) {
	4635	+ /* release buffers */
	4636	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	4637	+ if (stream->curr_buf)
	4638	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
	4639	+ if (stream->next_buf &&
	4640	+ stream->next_buf != stream->curr_buf)
	4641	+ list_add_tail(&stream->next_buf->queue, &stream->buf_head);
	4642	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	4643	+
	4644	+ stream->curr_buf = NULL;
	4645	+ stream->next_buf = NULL;
	4646	+
	4647	+ if (dev->hdr.hdr_mode == HDR_X2 \|\|
	4648	+ dev->hdr.hdr_mode == HDR_X3)
	4649	+ rkcif_release_rdbk_buf(stream);
	4650	+
	4651	+ rkcif_rx_buffer_free(stream);
	4652	+ list_for_each_entry(buf, &stream->buf_head, queue) {
	4653	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	4654	+ "stream[%d] buf return addr 0x%x\n",
	4655	+ stream->id, buf->buff_addr[0]);
	4656	+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
	4657	+ }
	4658	+ INIT_LIST_HEAD(&stream->buf_head);
	4659	+ while (!list_empty(&stream->vb_done_list)) {
	4660	+ buf = list_first_entry(&stream->vb_done_list,
	4661	+ struct rkcif_buffer, queue);
	4662	+ if (buf) {
	4663	+ list_del(&buf->queue);
	4664	+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
	4665	+ }
	4666	+ }
	4667	+ stream->lack_buf_cnt = 0;
	4668	+ stream->dma_en &= ~RKCIF_DMAEN_BY_VICAP;
2440	4669	}
2441	4670
2442		- media_pipeline_stop(&node->vdev.entity);
2443		- ret = dev->pipe.set_stream(&dev->pipe, false);
2444		- if (ret < 0)
2445		- v4l2_err(v4l2_dev, "pipeline stream-off failed error:%d\n",
2446		- ret);
2447		-
2448		- dev->is_start_hdr = false;
2449		- stream->is_dvp_yuv_addr_init = false;
2450		-
2451		- /* release buffers */
2452		- if (stream->curr_buf)
2453		- list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
2454		-
2455		- if (stream->next_buf &&
2456		- stream->next_buf != stream->curr_buf)
2457		- list_add_tail(&stream->next_buf->queue, &stream->buf_head);
2458		-
2459		- if (dev->hdr.mode != NO_HDR)
2460		- rkcif_release_rdbk_buf(stream);
2461		-
2462		- stream->curr_buf = NULL;
2463		- stream->next_buf = NULL;
2464		-
2465		- while (!list_empty(&stream->buf_head)) {
2466		- buf = list_first_entry(&stream->buf_head,
2467		- struct rkcif_buffer, queue);
2468		- list_del(&buf->queue);
2469		- vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
2470		- }
2471		-
2472		- ret = dev->pipe.close(&dev->pipe);
2473		- if (ret < 0)
2474		- v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
2475		-
2476		- if (dev->hdr.mode == HDR_X2) {
2477		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
2478		- dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY) {
	4671	+ if (mode == stream->cur_stream_mode) {
	4672	+ ret = dev->pipe.close(&dev->pipe);
	4673	+ if (ret < 0)
	4674	+ v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
	4675	+ if (dev->hdr.hdr_mode == HDR_X2) {
	4676	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
	4677	+ dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY) {
	4678	+ dev->can_be_reset = true;
	4679	+ }
	4680	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
	4681	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
	4682	+ dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY &&
	4683	+ dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_READY) {
	4684	+ dev->can_be_reset = true;
	4685	+ }
	4686	+ } else {
2479	4687	dev->can_be_reset = true;
2480	4688	}
2481		- } else if (dev->hdr.mode == HDR_X3) {
2482		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
2483		- dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY &&
2484		- dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_READY) {
2485		- dev->can_be_reset = true;
	4689	+ mutex_lock(&hw_dev->dev_lock);
	4690	+ for (i = 0; i < hw_dev->dev_num; i++) {
	4691	+ if (atomic_read(&hw_dev->cif_dev[i]->pipe.stream_cnt) != 0) {
	4692	+ can_reset = false;
	4693	+ break;
	4694	+ }
2486	4695	}
2487		- } else {
2488		- dev->can_be_reset = true;
2489		- }
2490		-
2491		- spin_lock_irqsave(&hw_dev->hw_timer.timer_lock, flags);
2492		- for (i = 0; i < hw_dev->dev_num; i++) {
2493		- if (atomic_read(&hw_dev->cif_dev[i]->pipe.stream_cnt) != 0) {
2494		- can_reset = false;
2495		- break;
	4696	+ mutex_unlock(&hw_dev->dev_lock);
	4697	+ if (dev->can_be_reset && dev->chip_id >= CHIP_RK3588_CIF)
	4698	+ rkcif_do_soft_reset(dev);
	4699	+ if (dev->can_be_reset && can_reset) {
	4700	+ dev->can_be_reset = false;
	4701	+ dev->reset_work_cancel = true;
	4702	+ dev->early_line = 0;
	4703	+ dev->sensor_linetime = 0;
	4704	+ dev->wait_line = 0;
	4705	+ stream->is_line_wake_up = false;
2496	4706	}
	4707	+ tasklet_disable(&stream->vb_done_tasklet);
2497	4708	}
2498		-
2499		- if (dev->can_be_reset && can_reset) {
2500		- rkcif_do_cru_reset(dev);
2501		- dev->can_be_reset = false;
2502		- dev->reset_work_cancel = true;
2503		- hw_dev->hw_timer.is_running = false;
2504		- hw_dev->reset_info.is_need_reset = 0;
2505		- }
2506		- spin_unlock_irqrestore(&hw_dev->hw_timer.timer_lock, flags);
2507		-
2508		- pm_runtime_put_sync(dev->dev);
2509		-
2510		- if (!atomic_read(&dev->pipe.stream_cnt) && dev->dummy_buf.vaddr)
	4709	+ if (can_reset && hw_dev->dummy_buf.vaddr)
2511	4710	rkcif_destroy_dummy_buf(stream);
2512		-
2513		- v4l2_info(&dev->v4l2_dev, "stream[%d] stopping finished\n", stream->id);
2514		-
	4711	+ stream->cur_stream_mode &= ~mode;
	4712	+ INIT_LIST_HEAD(&stream->vb_done_list);
	4713	+ v4l2_info(&dev->v4l2_dev, "stream[%d] stopping finished, dma_en 0x%x\n", stream->id, stream->dma_en);
2515	4714	mutex_unlock(&dev->stream_lock);
	4715	+ rkcif_detach_sync_mode(dev);
	4716	+}
	4717	+
	4718	+static void rkcif_stop_streaming(struct vb2_queue *queue)
	4719	+{
	4720	+ struct rkcif_stream *stream = queue->drv_priv;
	4721	+
	4722	+ rkcif_do_stop_stream(stream, RKCIF_STREAM_MODE_CAPTURE);
2516	4723	}
2517	4724
2518	4725	/*
..	..	@@ -2588,6 +4795,70 @@
2588	4795	return mode;
2589	4796	}
2590	4797
	4798	+static u32 rkcif_determine_input_mode_rk3588(struct rkcif_stream *stream)
	4799	+{
	4800	+ struct rkcif_device *dev = stream->cifdev;
	4801	+ struct rkcif_sensor_info *sensor_info = dev->active_sensor;
	4802	+ struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
	4803	+ __u32 intf = BT656_STD_RAW;
	4804	+ u32 mode = INPUT_MODE_YUV;
	4805	+ v4l2_std_id std;
	4806	+ int ret;
	4807	+
	4808	+ ret = v4l2_subdev_call(sensor_info->sd, video, querystd, &std);
	4809	+ if (ret == 0) {
	4810	+ /* retrieve std from sensor if exist */
	4811	+ switch (std) {
	4812	+ case V4L2_STD_NTSC:
	4813	+ case V4L2_STD_PAL:
	4814	+ mode = INPUT_BT656_YUV422;
	4815	+ break;
	4816	+ case V4L2_STD_ATSC:
	4817	+ mode = INPUT_BT1120_YUV422;
	4818	+ break;
	4819	+ default:
	4820	+ v4l2_err(&dev->v4l2_dev,
	4821	+ "std: %lld is not supported", std);
	4822	+ }
	4823	+ mode \|= CSI_WRDDR_TYPE_RAW8 << 6;
	4824	+ } else {
	4825	+ /* determine input mode by mbus_code (fmt_type) */
	4826	+ switch (stream->cif_fmt_in->fmt_type) {
	4827	+ case CIF_FMT_TYPE_YUV:
	4828	+ if (sensor_info->mbus.type == V4L2_MBUS_BT656) {
	4829	+ if ((sensor_info->mbus.flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE)
	4830	+ mode = INPUT_BT1120_YUV422;
	4831	+ else
	4832	+ mode = INPUT_BT656_YUV422;
	4833	+ } else {
	4834	+ mode = INPUT_BT601_YUV422;
	4835	+ }
	4836	+ mode \|= CSI_WRDDR_TYPE_RAW8 << 6;
	4837	+ break;
	4838	+ case CIF_FMT_TYPE_RAW:
	4839	+ ret = v4l2_subdev_call(terminal_sensor->sd,
	4840	+ core, ioctl,
	4841	+ RKMODULE_GET_BT656_INTF_TYPE,
	4842	+ &intf);
	4843	+ if (!ret) {
	4844	+ if (intf == BT656_SONY_RAW)
	4845	+ mode = INPUT_SONY_RAW;
	4846	+ else
	4847	+ mode = INPUT_BT601_RAW;
	4848	+ } else {
	4849	+ mode = INPUT_BT601_RAW;
	4850	+ }
	4851	+ mode \|= stream->cif_fmt_in->csi_fmt_val << 6;
	4852	+ break;
	4853	+ }
	4854	+ }
	4855	+ if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
	4856	+ mode \|= TRANSMIT_PROGRESS_RK3588;
	4857	+ else
	4858	+ mode \|= TRANSMIT_INTERFACE_RK3588;
	4859	+ return mode;
	4860	+}
	4861	+
2591	4862	static inline u32 rkcif_scl_ctl(struct rkcif_stream *stream)
2592	4863	{
2593	4864	u32 fmt_type = stream->cif_fmt_in->fmt_type;
..	..	@@ -2612,15 +4883,21 @@
2612	4883	case V4L2_PIX_FMT_NV61:
2613	4884	case V4L2_PIX_FMT_NV12:
2614	4885	case V4L2_PIX_FMT_NV21:
2615		- case V4L2_PIX_FMT_YUYV:
2616		- case V4L2_PIX_FMT_YVYU:
2617		- case V4L2_PIX_FMT_UYVY:
2618		- case V4L2_PIX_FMT_VYUY:
2619	4886	case V4L2_PIX_FMT_GREY:
2620	4887	case V4L2_PIX_FMT_Y16:
2621	4888	bpp = fmt->bpp[plane_index];
2622	4889	break;
	4890	+ case V4L2_PIX_FMT_YUYV:
	4891	+ case V4L2_PIX_FMT_YVYU:
	4892	+ case V4L2_PIX_FMT_UYVY:
	4893	+ case V4L2_PIX_FMT_VYUY:
	4894	+ if (stream->cifdev->chip_id < CHIP_RK3588_CIF)
	4895	+ bpp = fmt->bpp[plane_index];
	4896	+ else
	4897	+ bpp = fmt->bpp[plane_index + 1];
	4898	+ break;
2623	4899	case V4L2_PIX_FMT_RGB24:
	4900	+ case V4L2_PIX_FMT_BGR24:
2624	4901	case V4L2_PIX_FMT_RGB565:
2625	4902	case V4L2_PIX_FMT_BGR666:
2626	4903	case V4L2_PIX_FMT_SRGGB8:
..	..	@@ -2636,8 +4913,13 @@
2636	4913	case V4L2_PIX_FMT_SGBRG12:
2637	4914	case V4L2_PIX_FMT_SBGGR12:
2638	4915	case V4L2_PIX_FMT_SBGGR16:
	4916	+ case V4L2_PIX_FMT_SGBRG16:
	4917	+ case V4L2_PIX_FMT_SGRBG16:
	4918	+ case V4L2_PIX_FMT_SRGGB16:
2639	4919	case V4l2_PIX_FMT_SPD16:
2640	4920	case V4l2_PIX_FMT_EBD8:
	4921	+ case V4L2_PIX_FMT_Y10:
	4922	+ case V4L2_PIX_FMT_Y12:
2641	4923	if (stream->cifdev->chip_id < CHIP_RV1126_CIF) {
2642	4924	bpp = max(fmt->bpp[plane_index], (u8)CIF_RAW_STORED_BIT_WIDTH);
2643	4925	cal = CIF_RAW_STORED_BIT_WIDTH;
..	..	@@ -2653,7 +4935,8 @@
2653	4935	}
2654	4936	break;
2655	4937	default:
2656		- pr_err("fourcc: %d is not supported!\n", fmt->fourcc);
	4938	+ v4l2_err(&stream->cifdev->v4l2_dev, "fourcc: %d is not supported!\n",
	4939	+ fmt->fourcc);
2657	4940	break;
2658	4941	}
2659	4942	}
..	..	@@ -2687,7 +4970,8 @@
2687	4970
2688	4971	if (dev->terminal_sensor.sd) {
2689	4972	input_sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
2690		-
	4973	+ input_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	4974	+ input_sel.pad = 0;
2691	4975	ret = v4l2_subdev_call(dev->terminal_sensor.sd,
2692	4976	pad, get_selection, NULL,
2693	4977	&input_sel);
..	..	@@ -2732,11 +5016,11 @@
2732	5016	struct rkcif_device *dev = stream->cifdev;
2733	5017	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
2734	5018	struct v4l2_rect input, *crop;
2735		- int vc;
2736	5019
2737	5020	if (dev->terminal_sensor.sd) {
2738	5021	stream->cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
2739		- &input, stream->id, &vc);
	5022	+ &input, stream->id,
	5023	+ &dev->channels[stream->id]);
2740	5024	if (!stream->cif_fmt_in) {
2741	5025	v4l2_err(v4l2_dev, "Input fmt is invalid\n");
2742	5026	return -EINVAL;
..	..	@@ -2746,7 +5030,6 @@
2746	5030	return -EINVAL;
2747	5031	}
2748	5032
2749		- stream->vc = vc;
2750	5033	if (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
2751	5034	stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8) {
2752	5035	stream->crop_enable = false;
..	..	@@ -2764,7 +5047,9 @@
2764	5047	return -EINVAL;
2765	5048	}
2766	5049
2767		- if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2) {
	5050	+ if (dev->active_sensor &&
	5051	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	5052	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY)) {
2768	5053	if (crop->left > 0) {
2769	5054	int align_x = get_csi_crop_align(stream->cif_fmt_in);
2770	5055
..	..	@@ -2775,7 +5060,7 @@
2775	5060	return -EINVAL;
2776	5061	}
2777	5062	}
2778		- } else if (dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) {
	5063	+ } else if (dev->active_sensor && dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) {
2779	5064	if (crop->left % 4 != 0 && crop->width % 4 != 0) {
2780	5065	v4l2_err(v4l2_dev,
2781	5066	"ERROR: lvds crop left and width must align %d\n", 4);
..	..	@@ -2807,8 +5092,8 @@
2807	5092	__func__, stream->id);
2808	5093	return -ENODEV;
2809	5094	}
2810		- ret = v4l2_subdev_call(sensor->sd, video, g_mbus_config,
2811		- &sensor->mbus);
	5095	+ ret = v4l2_subdev_call(sensor->sd, pad, get_mbus_config,
	5096	+ 0, &sensor->mbus);
2812	5097	if (ret && ret != -ENOIOCTLCMD) {
2813	5098	v4l2_err(&stream->cifdev->v4l2_dev,
2814	5099	"%s: get remote %s mbus failed!\n", __func__, sensor->sd->name);
..	..	@@ -2820,24 +5105,38 @@
2820	5105	terminal_sensor = &stream->cifdev->terminal_sensor;
2821	5106	get_remote_terminal_sensor(stream, &terminal_sensor->sd);
2822	5107	if (terminal_sensor->sd) {
2823		- ret = v4l2_subdev_call(terminal_sensor->sd, video, g_mbus_config,
2824		- &terminal_sensor->mbus);
	5108	+ ret = v4l2_subdev_call(terminal_sensor->sd, pad, get_mbus_config,
	5109	+ 0, &terminal_sensor->mbus);
2825	5110	if (ret && ret != -ENOIOCTLCMD) {
2826	5111	v4l2_err(&stream->cifdev->v4l2_dev,
2827	5112	"%s: get terminal %s mbus failed!\n",
2828	5113	__func__, terminal_sensor->sd->name);
2829	5114	return ret;
2830	5115	}
2831		- if (v4l2_subdev_call(terminal_sensor->sd, core, ioctl, RKMODULE_GET_CSI_DSI_INFO,
2832		- &terminal_sensor->dsi_input_en)) {
2833		- v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
2834		- "%s: get terminal %s CSI/DSI sel failed, default csi input!\n",
	5116	+ ret = v4l2_subdev_call(terminal_sensor->sd, video,
	5117	+ g_frame_interval, &terminal_sensor->fi);
	5118	+ if (ret) {
	5119	+ v4l2_err(&stream->cifdev->v4l2_dev,
	5120	+ "%s: get terminal %s g_frame_interval failed!\n",
2835	5121	__func__, terminal_sensor->sd->name);
	5122	+ return ret;
	5123	+ }
	5124	+ if (v4l2_subdev_call(terminal_sensor->sd, core, ioctl, RKMODULE_GET_CSI_DSI_INFO,
	5125	+ &terminal_sensor->dsi_input_en)) {
	5126	+ v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
	5127	+ "%s: get terminal %s CSI/DSI sel failed, default csi input!\n",
	5128	+ __func__, terminal_sensor->sd->name);
2836	5129	terminal_sensor->dsi_input_en = 0;
2837	5130	}
	5131	+ } else {
	5132	+ v4l2_err(&stream->cifdev->v4l2_dev,
	5133	+ "%s: stream[%d] get remote terminal sensor failed!\n",
	5134	+ __func__, stream->id);
	5135	+ return -ENODEV;
2838	5136	}
2839	5137
2840		- if (terminal_sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
	5138	+ if (terminal_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	5139	+ terminal_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
2841	5140	terminal_sensor->mbus.type == V4L2_MBUS_CCP2) {
2842	5141	switch (terminal_sensor->mbus.flags & V4L2_MBUS_CSI2_LANES) {
2843	5142	case V4L2_MBUS_CSI2_1_LANE:
..	..	@@ -2864,7 +5163,85 @@
2864	5163	return ret;
2865	5164	}
2866	5165
2867		-static int rkcif_stream_start(struct rkcif_stream *stream)
	5166	+static int rkcif_dvp_get_output_type_mask(struct rkcif_stream *stream)
	5167	+{
	5168	+ unsigned int mask;
	5169	+ const struct cif_output_fmt *fmt = stream->cif_fmt_out;
	5170	+
	5171	+ switch (fmt->fourcc) {
	5172	+ case V4L2_PIX_FMT_NV16:
	5173	+ mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << 11) \|
	5174	+ (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
	5175	+ break;
	5176	+ case V4L2_PIX_FMT_NV61:
	5177	+ mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << 11) \|
	5178	+ (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
	5179	+ break;
	5180	+ case V4L2_PIX_FMT_NV12:
	5181	+ mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << 11) \|
	5182	+ (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
	5183	+ break;
	5184	+ case V4L2_PIX_FMT_NV21:
	5185	+ mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << 11) \|
	5186	+ (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
	5187	+ break;
	5188	+ case V4L2_PIX_FMT_YUYV:
	5189	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) \|
	5190	+ (CSI_YUV_OUTPUT_ORDER_YUYV << 1);
	5191	+ break;
	5192	+ case V4L2_PIX_FMT_YVYU:
	5193	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) \|
	5194	+ (CSI_YUV_OUTPUT_ORDER_YVYU << 1);
	5195	+ break;
	5196	+ case V4L2_PIX_FMT_UYVY:
	5197	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) \|
	5198	+ (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
	5199	+ break;
	5200	+ case V4L2_PIX_FMT_VYUY:
	5201	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) \|
	5202	+ (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
	5203	+ break;
	5204	+ case V4L2_PIX_FMT_RGB24:
	5205	+ case V4L2_PIX_FMT_BGR24:
	5206	+ case V4L2_PIX_FMT_RGB565:
	5207	+ case V4L2_PIX_FMT_BGR666:
	5208	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
	5209	+ break;
	5210	+ case V4L2_PIX_FMT_SRGGB8:
	5211	+ case V4L2_PIX_FMT_SGRBG8:
	5212	+ case V4L2_PIX_FMT_SGBRG8:
	5213	+ case V4L2_PIX_FMT_SBGGR8:
	5214	+ case V4L2_PIX_FMT_SRGGB10:
	5215	+ case V4L2_PIX_FMT_SGRBG10:
	5216	+ case V4L2_PIX_FMT_SGBRG10:
	5217	+ case V4L2_PIX_FMT_SBGGR10:
	5218	+ case V4L2_PIX_FMT_SRGGB12:
	5219	+ case V4L2_PIX_FMT_SGRBG12:
	5220	+ case V4L2_PIX_FMT_SGBRG12:
	5221	+ case V4L2_PIX_FMT_SBGGR12:
	5222	+ case V4L2_PIX_FMT_GREY:
	5223	+ case V4L2_PIX_FMT_Y10:
	5224	+ case V4L2_PIX_FMT_Y12:
	5225	+ if (stream->is_compact)
	5226	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
	5227	+ else
	5228	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
	5229	+ break;
	5230	+ case V4L2_PIX_FMT_SBGGR16:
	5231	+ case V4L2_PIX_FMT_SGBRG16:
	5232	+ case V4L2_PIX_FMT_SGRBG16:
	5233	+ case V4L2_PIX_FMT_SRGGB16:
	5234	+ case V4L2_PIX_FMT_Y16:
	5235	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
	5236	+ break;
	5237	+ default:
	5238	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
	5239	+ break;
	5240	+ }
	5241	+ return mask;
	5242	+}
	5243	+
	5244	+static int rkcif_stream_start(struct rkcif_stream *stream, unsigned int mode)
2868	5245	{
2869	5246	u32 val, mbus_flags, href_pol, vsync_pol,
2870	5247	xfer_mode = 0, yc_swap = 0, inputmode = 0,
..	..	@@ -2873,20 +5250,66 @@
2873	5250	multi_id_mode = BT656_1120_MULTI_ID_MODE_1,
2874	5251	multi_id_sel = BT656_1120_MULTI_ID_SEL_LSB,
2875	5252	bt1120_edge_mode = BT1120_CLOCK_SINGLE_EDGES,
2876		- bt1120_flags = 0;
	5253	+ bt1120_flags = 0,
	5254	+ out_fmt_mask = 0,
	5255	+ in_fmt_yuv_order = 0;
2877	5256	struct rkmodule_bt656_mbus_info bt1120_info;
2878	5257	struct rkcif_device *dev = stream->cifdev;
2879	5258	struct rkcif_sensor_info *sensor_info;
2880	5259	struct v4l2_mbus_config *mbus;
2881	5260	struct rkcif_dvp_sof_subdev *sof_sd = &dev->dvp_sof_subdev;
2882	5261	const struct cif_output_fmt *fmt;
	5262	+ unsigned int dma_en = 0;
	5263	+ unsigned int dma_state = 0;
	5264	+ int i = 0;
	5265	+ u32 sav_detect = BT656_DETECT_SAV;
	5266	+ u32 reserved = 0;
2883	5267
2884		- if (stream->state != RKCIF_STATE_RESET_IN_STREAMING)
	5268	+ if (stream->state < RKCIF_STATE_STREAMING) {
2885	5269	stream->frame_idx = 0;
	5270	+ stream->buf_wake_up_cnt = 0;
	5271	+ stream->lack_buf_cnt = 0;
	5272	+ stream->frame_phase = 0;
	5273	+ stream->is_in_vblank = false;
	5274	+ stream->is_change_toisp = false;
	5275	+ }
2886	5276
2887	5277	sensor_info = dev->active_sensor;
2888	5278	mbus = &sensor_info->mbus;
2889	5279
	5280	+ dma_state = stream->dma_en;
	5281	+ if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE)
	5282	+ stream->dma_en \|= RKCIF_DMAEN_BY_VICAP;
	5283	+ else if ((mode & RKCIF_STREAM_MODE_TOISP_RDBK) == RKCIF_STREAM_MODE_TOISP_RDBK)
	5284	+ stream->dma_en \|= RKCIF_DMAEN_BY_ISP;
	5285	+ else if ((mode & RKCIF_STREAM_MODE_ROCKIT) == RKCIF_STREAM_MODE_ROCKIT)
	5286	+ stream->dma_en \|= RKCIF_DMAEN_BY_ROCKIT;
	5287	+
	5288	+ if (dma_state)
	5289	+ return 0;
	5290	+
	5291	+ mbus_flags = mbus->flags;
	5292	+ if ((mbus_flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE) {
	5293	+ bt1120_edge_mode = (dev->chip_id < CHIP_RK3588_CIF ?
	5294	+ BT1120_CLOCK_DOUBLE_EDGES : BT1120_CLOCK_DOUBLE_EDGES_RK3588);
	5295	+ rkcif_enable_dvp_clk_dual_edge(dev, true);
	5296	+ } else {
	5297	+ bt1120_edge_mode = dev->chip_id < CHIP_RK3588_CIF ?
	5298	+ BT1120_CLOCK_SINGLE_EDGES : BT1120_CLOCK_SINGLE_EDGES_RK3588;
	5299	+ rkcif_enable_dvp_clk_dual_edge(dev, false);
	5300	+ }
	5301	+
	5302	+ if (IS_ENABLED(CONFIG_CPU_RV1106))
	5303	+ rkcif_config_dvp_pin(dev, true);
	5304	+
	5305	+ if (mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
	5306	+ rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_RISING);
	5307	+ else
	5308	+ rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_FALLING);
	5309	+
	5310	+#if IS_ENABLED(CONFIG_CPU_RV1106)
	5311	+ rv1106_sdmmc_get_lock();
	5312	+#endif
2890	5313	if (sensor_info->sd && mbus->type == V4L2_MBUS_BT656) {
2891	5314	int ret;
2892	5315
..	..	@@ -2910,32 +5333,21 @@
2910	5333	multi_id_mode = BT656_1120_MULTI_ID_MODE_4;
2911	5334	else if (((bt1120_flags & RKMODULE_CAMERA_BT656_CHANNELS) >> 2) > 1)
2912	5335	multi_id_mode = BT656_1120_MULTI_ID_MODE_2;
2913		-
2914		- multi_id = DVP_SW_MULTI_ID(stream->id, stream->id, bt1120_info.id_en_bits);
	5336	+ for (i = 0; i < 4; i++)
	5337	+ multi_id \|= DVP_SW_MULTI_ID(i, i, bt1120_info.id_en_bits);
2915	5338	rkcif_write_register_or(dev, CIF_REG_DVP_MULTI_ID, multi_id);
2916	5339	}
2917	5340	}
2918		-
2919		- mbus_flags = mbus->flags;
2920		- if ((mbus_flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE) {
2921		- bt1120_edge_mode = BT1120_CLOCK_DOUBLE_EDGES;
2922		- rkcif_enable_dvp_clk_dual_edge(dev, true);
2923		- } else {
2924		- bt1120_edge_mode = BT1120_CLOCK_SINGLE_EDGES;
2925		- rkcif_enable_dvp_clk_dual_edge(dev, false);
2926		- }
2927		-
2928		- if (mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2929		- rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_RISING);
2930		- else
2931		- rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_FALLING);
2932	5341
2933	5342	href_pol = (mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) ?
2934	5343	HSY_HIGH_ACTIVE : HSY_LOW_ACTIVE;
2935	5344	vsync_pol = (mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) ?
2936	5345	VSY_HIGH_ACTIVE : VSY_LOW_ACTIVE;
2937	5346
2938		- inputmode = rkcif_determine_input_mode(stream);
	5347	+ if (dev->chip_id < CHIP_RK3588_CIF)
	5348	+ inputmode = rkcif_determine_input_mode(stream);
	5349	+ else
	5350	+ inputmode = rkcif_determine_input_mode_rk3588(stream);
2939	5351	if (dev->chip_id <= CHIP_RK1808_CIF) {
2940	5352	if (inputmode == INPUT_MODE_BT1120) {
2941	5353	if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
..	..	@@ -2945,7 +5357,7 @@
2945	5357	if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
2946	5358	yc_swap = BT1120_YC_SWAP;
2947	5359	}
2948		- } else {
	5360	+ } else if (dev->chip_id < CHIP_RK3588_CIF) {
2949	5361	if (sensor_info->mbus.type == V4L2_MBUS_BT656) {
2950	5362	if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
2951	5363	xfer_mode = BT1120_TRANSMIT_PROGRESS;
..	..	@@ -2957,9 +5369,14 @@
2957	5369	if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
2958	5370	yc_swap = BT1120_YC_SWAP;
2959	5371	}
	5372	+ } else {
	5373	+ if ((inputmode & INPUT_BT1120_YUV422) == INPUT_BT1120_YUV422)
	5374	+ if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
	5375	+ yc_swap = BT1120_YC_SWAP_RK3588;
2960	5376	}
2961	5377
2962		- if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2) {
	5378	+ if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	5379	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
2963	5380	inputmode = INPUT_MODE_MIPI;
2964	5381
2965	5382	/* if cif is linked with mipi,
..	..	@@ -2977,33 +5394,43 @@
2977	5394	mipimode = MIPI_MODE_32BITS_BYPASS;
2978	5395	}
2979	5396
2980		- val = vsync_pol \| href_pol \| inputmode \| mipimode
2981		- \| stream->cif_fmt_out->fmt_val
2982		- \| stream->cif_fmt_in->dvp_fmt_val
2983		- \| xfer_mode \| yc_swap \| multi_id_en
2984		- \| multi_id_sel \| multi_id_mode \| bt1120_edge_mode;
2985		-
2986		- if (stream->is_high_align)
2987		- val \|= CIF_HIGH_ALIGN;
2988		- else
2989		- val &= ~CIF_HIGH_ALIGN;
	5397	+ if (dev->chip_id < CHIP_RK3588_CIF) {
	5398	+ val = vsync_pol \| href_pol \| inputmode \| mipimode
	5399	+ \| stream->cif_fmt_out->fmt_val
	5400	+ \| stream->cif_fmt_in->dvp_fmt_val
	5401	+ \| xfer_mode \| yc_swap \| multi_id_en
	5402	+ \| multi_id_sel \| multi_id_mode \| bt1120_edge_mode;
	5403	+ if (stream->is_high_align)
	5404	+ val \|= CIF_HIGH_ALIGN;
	5405	+ else
	5406	+ val &= ~CIF_HIGH_ALIGN;
	5407	+ } else {
	5408	+ out_fmt_mask = rkcif_dvp_get_output_type_mask(stream);
	5409	+ in_fmt_yuv_order = rkcif_dvp_get_input_yuv_order(stream);
	5410	+ val = vsync_pol \| href_pol \| inputmode
	5411	+ \| yc_swap
	5412	+ \| out_fmt_mask
	5413	+ \| in_fmt_yuv_order
	5414	+ \| multi_id_en
	5415	+ \| sav_detect
	5416	+ \| multi_id_sel \| multi_id_mode \| bt1120_edge_mode;
	5417	+ if (stream->is_high_align)
	5418	+ val \|= CIF_HIGH_ALIGN_RK3588;
	5419	+ else
	5420	+ val &= ~CIF_HIGH_ALIGN_RK3588;
	5421	+ }
2990	5422	rkcif_write_register(dev, CIF_REG_DVP_FOR, val);
2991	5423
2992		- val = stream->pixm.width;
2993		- if (stream->cif_fmt_in->fmt_type == CIF_FMT_TYPE_RAW) {
2994		- fmt = find_output_fmt(stream, stream->pixm.pixelformat);
2995		- if (fmt->fourcc == V4L2_PIX_FMT_GREY \|\|
2996		- fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
2997		- fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
2998		- fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
2999		- fmt->fourcc == V4L2_PIX_FMT_SBGGR8)
	5424	+ if (dev->chip_id >= CHIP_RK3588_CIF) {
	5425	+ val = stream->pixm.plane_fmt[0].bytesperline;
	5426	+ } else {
	5427	+ fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
	5428	+ if (fmt->fmt_type == CIF_FMT_TYPE_RAW &&
	5429	+ fmt->csi_fmt_val == CSI_WRDDR_TYPE_RAW8)
3000	5430	val = ALIGN(stream->pixm.width * fmt->raw_bpp / 8, 256);
3001	5431	else
3002	5432	val = stream->pixm.width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
3003	5433	}
3004		- rkcif_write_register(dev, CIF_REG_DVP_VIR_LINE_WIDTH, val);
3005		- rkcif_write_register(dev, CIF_REG_DVP_SET_SIZE,
3006		- stream->pixm.width \| (stream->pixm.height << 16));
3007	5434
3008	5435	if (stream->crop_enable) {
3009	5436	dev->channels[stream->id].crop_en = 1;
..	..	@@ -3019,6 +5446,10 @@
3019	5446	dev->channels[stream->id].crop_en = 0;
3020	5447	}
3021	5448
	5449	+ rkcif_write_register(dev, CIF_REG_DVP_VIR_LINE_WIDTH, val);
	5450	+ rkcif_write_register(dev, CIF_REG_DVP_SET_SIZE,
	5451	+ dev->channels[stream->id].width \|
	5452	+ (dev->channels[stream->id].height << 16));
3022	5453	rkcif_write_register(dev, CIF_REG_DVP_CROP,
3023	5454	dev->channels[stream->id].crop_st_y << CIF_CROP_Y_SHIFT \|
3024	5455	dev->channels[stream->id].crop_st_x);
..	..	@@ -3026,17 +5457,44 @@
3026	5457	if (atomic_read(&dev->pipe.stream_cnt) <= 1)
3027	5458	rkcif_write_register(dev, CIF_REG_DVP_FRAME_STATUS, FRAME_STAT_CLS);
3028	5459
3029		- rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, INTSTAT_CLS);
3030		- rkcif_write_register(dev, CIF_REG_DVP_SCL_CTRL, rkcif_scl_ctl(stream));
	5460	+ if (dev->chip_id < CHIP_RK3588_CIF) {
	5461	+ rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, INTSTAT_CLS);
	5462	+ rkcif_write_register(dev, CIF_REG_DVP_SCL_CTRL, rkcif_scl_ctl(stream));
	5463	+ rkcif_write_register_or(dev, CIF_REG_DVP_INTEN,
	5464	+ DVP_DMA_END_INTSTAT(stream->id) \|
	5465	+ INTSTAT_ERR \| PST_INF_FRAME_END);
	5466	+ /* enable line int for sof */
	5467	+ rkcif_write_register(dev, CIF_REG_DVP_LINE_INT_NUM, 0x1);
	5468	+ rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, LINE_INT_EN);
	5469	+ } else {
	5470	+ if (dev->chip_id == CHIP_RV1106_CIF)
	5471	+ reserved = 0xfc3c0000;
	5472	+ else
	5473	+ reserved = 0;
	5474	+ rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, 0x3c3ffff \| reserved);
	5475	+ rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, 0x033ffff);//0x3c3ffff
	5476	+ }
3031	5477
3032		- if (dev->chip_id < CHIP_RK1808_CIF)
3033		- rkcif_assign_new_buffer_oneframe(stream,
3034		- RKCIF_YUV_ADDR_STATE_INIT);
3035		- else
3036		- rkcif_assign_new_buffer_pingpong(stream,
	5478	+ if (stream->dma_en) {
	5479	+ if (dev->chip_id < CHIP_RK1808_CIF) {
	5480	+ rkcif_assign_new_buffer_oneframe(stream,
	5481	+ RKCIF_YUV_ADDR_STATE_INIT);
	5482	+ } else {
	5483	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	5484	+ rkcif_assign_new_buffer_pingpong(stream,
3037	5485	RKCIF_YUV_ADDR_STATE_INIT,
3038	5486	stream->id);
3039		-
	5487	+ else if (mode == RKCIF_STREAM_MODE_TOISP \|\|
	5488	+ mode == RKCIF_STREAM_MODE_TOISP_RDBK)
	5489	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	5490	+ RKCIF_YUV_ADDR_STATE_INIT,
	5491	+ stream->id);
	5492	+ else if (mode == RKCIF_STREAM_MODE_ROCKIT)
	5493	+ rkcif_assign_new_buffer_pingpong_rockit(stream,
	5494	+ RKCIF_YUV_ADDR_STATE_INIT,
	5495	+ stream->id);
	5496	+ }
	5497	+ }
3040	5498	rkcif_write_register_or(dev, CIF_REG_DVP_INTEN,
3041	5499	DVP_DMA_END_INTSTAT(stream->id) \|
3042	5500	INTSTAT_ERR \| PST_INF_FRAME_END);
..	..	@@ -3052,14 +5510,47 @@
3052	5510	else
3053	5511	workmode = MODE_LINELOOP;
3054	5512
3055		- if (inputmode == INPUT_MODE_BT1120) {
	5513	+ if ((inputmode & INPUT_MODE_BT1120) == INPUT_MODE_BT1120) {
3056	5514	workmode = MODE_PINGPONG;
3057	5515	dev->workmode = RKCIF_WORKMODE_PINGPONG;
3058	5516	}
3059	5517
3060		- rkcif_write_register(dev, CIF_REG_DVP_CTRL,
3061		- AXI_BURST_16 \| workmode \| ENABLE_CAPTURE);
3062		-
	5518	+ if (dev->chip_id == CHIP_RK3588_CIF) {
	5519	+ if (stream->dma_en)
	5520	+ dma_en = DVP_DMA_EN;
	5521	+ if (stream->lack_buf_cnt == 2)
	5522	+ dma_en = 0;
	5523	+ rkcif_write_register(dev, CIF_REG_DVP_CTRL,
	5524	+ DVP_SW_WATER_LINE_25
	5525	+ \| dma_en
	5526	+ \| DVP_PRESS_EN
	5527	+ \| DVP_HURRY_EN
	5528	+ \| DVP_SW_WATER_LINE_25
	5529	+ \| DVP_SW_PRESS_VALUE(3)
	5530	+ \| DVP_SW_HURRY_VALUE(3)
	5531	+ \| ENABLE_CAPTURE);
	5532	+ } else if (dev->chip_id == CHIP_RV1106_CIF) {
	5533	+ if (stream->dma_en)
	5534	+ dma_en = DVP_SW_DMA_EN(stream->id);
	5535	+ if (stream->lack_buf_cnt == 2)
	5536	+ dma_en = 0;
	5537	+ rkcif_write_register(dev, CIF_REG_DVP_CTRL,
	5538	+ DVP_SW_WATER_LINE_25
	5539	+ \| DVP_PRESS_EN
	5540	+ \| DVP_HURRY_EN
	5541	+ \| DVP_SW_WATER_LINE_25
	5542	+ \| DVP_SW_PRESS_VALUE(3)
	5543	+ \| DVP_SW_HURRY_VALUE(3)
	5544	+ \| DVP_SW_CAP_EN(stream->id)
	5545	+ \| dma_en
	5546	+ \| ENABLE_CAPTURE);
	5547	+ } else {
	5548	+ rkcif_write_register(dev, CIF_REG_DVP_CTRL,
	5549	+ AXI_BURST_16 \| workmode \| ENABLE_CAPTURE);
	5550	+ }
	5551	+#if IS_ENABLED(CONFIG_CPU_RV1106)
	5552	+ rv1106_sdmmc_put_lock();
	5553	+#endif
3063	5554	atomic_set(&sof_sd->frm_sync_seq, 0);
3064	5555	stream->state = RKCIF_STATE_STREAMING;
3065	5556	stream->cifdev->dvp_sof_in_oneframe = 0;
..	..	@@ -3067,11 +5558,160 @@
3067	5558	return 0;
3068	5559	}
3069	5560
3070		-static int rkcif_start_streaming(struct vb2_queue *queue, unsigned int count)
	5561	+static void rkcif_attach_sync_mode(struct rkcif_device *cifdev)
3071	5562	{
3072		- struct rkcif_stream *stream = queue->drv_priv;
	5563	+ struct rkcif_hw *hw = cifdev->hw_dev;
	5564	+ struct rkcif_device *dev;
	5565	+ int i = 0, j = 0;
	5566	+ int ret = 0;
	5567	+ int count = 0;
	5568	+ int sync_type = NO_SYNC_MODE;
	5569	+ int sync_group = 0;
	5570	+ struct rkcif_sync_cfg sync_cfg;
	5571	+ struct rkcif_multi_sync_config *sync_config;
	5572	+
	5573	+ mutex_lock(&hw->dev_lock);
	5574	+ if (cifdev->sditf_cnt <= 1) {
	5575	+ ret = v4l2_subdev_call(cifdev->terminal_sensor.sd,
	5576	+ core, ioctl,
	5577	+ RKMODULE_GET_SYNC_MODE,
	5578	+ &sync_type);
	5579	+ if (!ret)
	5580	+ sync_cfg.type = sync_type;
	5581	+ else
	5582	+ sync_cfg.type = NO_SYNC_MODE;
	5583	+ ret = v4l2_subdev_call(cifdev->terminal_sensor.sd,
	5584	+ core, ioctl,
	5585	+ RKMODULE_GET_GROUP_ID,
	5586	+ &sync_group);
	5587	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	5588	+ sync_cfg.group = sync_group;
	5589	+ else
	5590	+ sync_cfg.group = 0;
	5591	+ } else {
	5592	+ for (j = 0; j < cifdev->sditf_cnt; j++) {
	5593	+ ret \|= v4l2_subdev_call(cifdev->sditf[j]->sensor_sd,
	5594	+ core, ioctl,
	5595	+ RKMODULE_GET_SYNC_MODE,
	5596	+ &sync_type);
	5597	+ if (!ret && sync_type)
	5598	+ break;
	5599	+ }
	5600	+ if (!ret)
	5601	+ sync_cfg.type = sync_type;
	5602	+ else
	5603	+ sync_cfg.type = NO_SYNC_MODE;
	5604	+ ret = v4l2_subdev_call(cifdev->sditf[j]->sensor_sd,
	5605	+ core, ioctl,
	5606	+ RKMODULE_GET_GROUP_ID,
	5607	+ &sync_group);
	5608	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	5609	+ sync_cfg.group = sync_group;
	5610	+ else
	5611	+ sync_cfg.group = 0;
	5612	+ }
	5613	+ if (sync_cfg.type == NO_SYNC_MODE \|\|
	5614	+ hw->sync_config[sync_cfg.group].is_attach) {
	5615	+ mutex_unlock(&hw->dev_lock);
	5616	+ return;
	5617	+ }
	5618	+ cifdev->sync_cfg = sync_cfg;
	5619	+
	5620	+ sync_config = &hw->sync_config[sync_cfg.group];
	5621	+ memset(sync_config, 0, sizeof(struct rkcif_multi_sync_config));
	5622	+ for (i = 0; i < hw->dev_num; i++) {
	5623	+ dev = hw->cif_dev[i];
	5624	+ if (dev->sditf_cnt <= 1) {
	5625	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	5626	+ core, ioctl,
	5627	+ RKMODULE_GET_SYNC_MODE,
	5628	+ &sync_type);
	5629	+ if (!ret)
	5630	+ sync_cfg.type = sync_type;
	5631	+ else
	5632	+ sync_cfg.type = NO_SYNC_MODE;
	5633	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	5634	+ core, ioctl,
	5635	+ RKMODULE_GET_GROUP_ID,
	5636	+ &sync_group);
	5637	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	5638	+ sync_cfg.group = sync_group;
	5639	+ else
	5640	+ sync_cfg.group = 0;
	5641	+ } else {
	5642	+ for (j = 0; j < dev->sditf_cnt; j++) {
	5643	+ ret \|= v4l2_subdev_call(dev->sditf[j]->sensor_sd,
	5644	+ core, ioctl,
	5645	+ RKMODULE_GET_SYNC_MODE,
	5646	+ &sync_type);
	5647	+ if (!ret && sync_type)
	5648	+ break;
	5649	+ }
	5650	+ if (!ret)
	5651	+ sync_cfg.type = sync_type;
	5652	+ else
	5653	+ sync_cfg.type = NO_SYNC_MODE;
	5654	+ ret = v4l2_subdev_call(dev->sditf[j]->sensor_sd,
	5655	+ core, ioctl,
	5656	+ RKMODULE_GET_GROUP_ID,
	5657	+ &sync_group);
	5658	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	5659	+ sync_cfg.group = sync_group;
	5660	+ else
	5661	+ sync_cfg.group = 0;
	5662	+ }
	5663	+ if (sync_cfg.group == cifdev->sync_cfg.group) {
	5664	+ if (sync_cfg.type == EXTERNAL_MASTER_MODE) {
	5665	+ count = sync_config->ext_master.count;
	5666	+ sync_config->ext_master.cif_dev[count] = dev;
	5667	+ sync_config->ext_master.count++;
	5668	+ sync_config->dev_cnt++;
	5669	+ sync_config->sync_mask \|= BIT(dev->csi_host_idx);
	5670	+ } else if (sync_cfg.type == INTERNAL_MASTER_MODE) {
	5671	+ count = sync_config->int_master.count;
	5672	+ sync_config->int_master.cif_dev[count] = dev;
	5673	+ sync_config->int_master.count++;
	5674	+ sync_config->dev_cnt++;
	5675	+ sync_config->sync_mask \|= BIT(dev->csi_host_idx);
	5676	+ } else if (sync_cfg.type == SLAVE_MODE) {
	5677	+ count = sync_config->slave.count;
	5678	+ sync_config->slave.cif_dev[count] = dev;
	5679	+ sync_config->slave.count++;
	5680	+ sync_config->dev_cnt++;
	5681	+ sync_config->sync_mask \|= BIT(dev->csi_host_idx);
	5682	+ }
	5683	+ dev->sync_cfg = sync_cfg;
	5684	+ }
	5685	+ }
	5686	+ if (sync_config->int_master.count == 1) {
	5687	+ if (sync_config->ext_master.count) {
	5688	+ sync_config->mode = RKCIF_MASTER_MASTER;
	5689	+ sync_config->is_attach = true;
	5690	+ } else if (sync_config->slave.count) {
	5691	+ sync_config->mode = RKCIF_MASTER_SLAVE;
	5692	+ sync_config->is_attach = true;
	5693	+ } else {
	5694	+ dev_info(hw->dev,
	5695	+ "Missing slave device, do not use sync mode\n");
	5696	+ }
	5697	+ if (sync_config->is_attach)
	5698	+ dev_info(hw->dev,
	5699	+ "group %d, int_master %d, ext_master %d, slave %d\n",
	5700	+ i,
	5701	+ sync_config->int_master.count,
	5702	+ sync_config->ext_master.count,
	5703	+ sync_config->slave.count);
	5704	+ }
	5705	+ mutex_unlock(&hw->dev_lock);
	5706	+}
	5707	+
	5708	+static void rkcif_monitor_reset_event(struct rkcif_device *dev);
	5709	+
	5710	+int rkcif_do_start_stream(struct rkcif_stream *stream, unsigned int mode)
	5711	+{
3073	5712	struct rkcif_vdev_node *node = &stream->vnode;
3074	5713	struct rkcif_device *dev = stream->cifdev;
	5714	+ struct rkcif_hw *hw_dev = dev->hw_dev;
3075	5715	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
3076	5716	struct rkcif_sensor_info *sensor_info = dev->active_sensor;
3077	5717	struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
..	..	@@ -3081,18 +5721,19 @@
3081	5721
3082	5722	v4l2_info(&dev->v4l2_dev, "stream[%d] start streaming\n", stream->id);
3083	5723
	5724	+ rkcif_attach_sync_mode(dev);
3084	5725	mutex_lock(&dev->stream_lock);
3085		-
3086		- if (WARN_ON(stream->state != RKCIF_STATE_READY)) {
	5726	+ if ((stream->cur_stream_mode & RKCIF_STREAM_MODE_CAPTURE) == mode) {
3087	5727	ret = -EBUSY;
3088	5728	v4l2_err(v4l2_dev, "stream in busy state\n");
3089	5729	goto destroy_buf;
3090	5730	}
	5731	+ if (stream->dma_en == 0)
	5732	+ stream->fs_cnt_in_single_frame = 0;
3091	5733	if (stream->is_line_wake_up)
3092	5734	stream->is_line_inten = true;
3093	5735	else
3094	5736	stream->is_line_inten = false;
3095		- stream->fs_cnt_in_single_frame = 0;
3096	5737
3097	5738	if (dev->active_sensor) {
3098	5739	ret = rkcif_update_sensor_info(stream);
..	..	@@ -3110,9 +5751,9 @@
3110	5751	RKMODULE_GET_HDR_CFG,
3111	5752	&hdr_cfg);
3112	5753	if (!ret)
3113		- dev->hdr.mode = hdr_cfg.hdr_mode;
	5754	+ dev->hdr = hdr_cfg;
3114	5755	else
3115		- dev->hdr.mode = NO_HDR;
	5756	+ dev->hdr.hdr_mode = NO_HDR;
3116	5757
3117	5758	ret = v4l2_subdev_call(terminal_sensor->sd,
3118	5759	video, g_frame_interval, &terminal_sensor->fi);
..	..	@@ -3133,94 +5774,95 @@
3133	5774	if (ret < 0)
3134	5775	goto destroy_buf;
3135	5776
	5777	+ mutex_lock(&hw_dev->dev_lock);
3136	5778	if (((dev->active_sensor && dev->active_sensor->mbus.type == V4L2_MBUS_BT656) \|\|
3137	5779	dev->is_use_dummybuf) &&
3138		- (!dev->dummy_buf.vaddr)) {
	5780	+ (!dev->hw_dev->dummy_buf.vaddr) &&
	5781	+ mode == RKCIF_STREAM_MODE_CAPTURE) {
3139	5782	ret = rkcif_create_dummy_buf(stream);
3140	5783	if (ret < 0) {
	5784	+ mutex_unlock(&hw_dev->dev_lock);
3141	5785	v4l2_err(v4l2_dev, "Failed to create dummy_buf, %d\n", ret);
3142	5786	goto destroy_buf;
3143	5787	}
3144	5788	}
	5789	+ mutex_unlock(&hw_dev->dev_lock);
3145	5790
3146		- /* enable clocks/power-domains */
3147		- ret = pm_runtime_get_sync(dev->dev);
3148		- if (ret < 0) {
3149		- v4l2_err(v4l2_dev, "Failed to get runtime pm, %d\n",
3150		- ret);
3151		- goto destroy_buf;
	5791	+ if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
	5792	+ tasklet_enable(&stream->vb_done_tasklet);
	5793	+ ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
	5794	+ if (ret < 0) {
	5795	+ v4l2_err(v4l2_dev, "open cif pipeline failed %d\n",
	5796	+ ret);
	5797	+ goto destroy_buf;
	5798	+ }
	5799	+
	5800	+ /*
	5801	+ * start sub-devices
	5802	+ * When use bt601, the sampling edge of cif is random,
	5803	+ * can be rising or fallling after powering on cif.
	5804	+ * To keep the coherence of edge, open sensor in advance.
	5805	+ */
	5806	+ if (sensor_info->mbus.type == V4L2_MBUS_PARALLEL \|\|
	5807	+ rkmodule_stream_seq == RKMODULE_START_STREAM_FRONT) {
	5808	+ ret = dev->pipe.set_stream(&dev->pipe, true);
	5809	+ if (ret < 0)
	5810	+ goto runtime_put;
	5811	+ }
3152	5812	}
3153		-
3154		- ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
3155		- if (ret < 0) {
3156		- v4l2_err(v4l2_dev, "open cif pipeline failed %d\n",
3157		- ret);
3158		- goto destroy_buf;
3159		- }
3160		-
3161		- /*
3162		- * start sub-devices
3163		- * When use bt601, the sampling edge of cif is random,
3164		- * can be rising or fallling after powering on cif.
3165		- * To keep the coherence of edge, open sensor in advance.
3166		- */
3167		- if (sensor_info->mbus.type == V4L2_MBUS_PARALLEL \|\|
3168		- rkmodule_stream_seq == RKMODULE_START_STREAM_FRONT) {
3169		- ret = dev->pipe.set_stream(&dev->pipe, true);
3170		- if (ret < 0)
3171		- goto runtime_put;
3172		- }
3173		-
3174	5813	if (dev->chip_id >= CHIP_RK1808_CIF) {
3175		- if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
3176		- dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)
3177		- ret = rkcif_csi_stream_start(stream);
	5814	+ if (dev->active_sensor &&
	5815	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	5816	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	5817	+ dev->active_sensor->mbus.type == V4L2_MBUS_CCP2))
	5818	+ ret = rkcif_csi_stream_start(stream, mode);
3178	5819	else
3179		- ret = rkcif_stream_start(stream);
	5820	+ ret = rkcif_stream_start(stream, mode);
3180	5821	} else {
3181		- ret = rkcif_stream_start(stream);
	5822	+ ret = rkcif_stream_start(stream, mode);
3182	5823	}
3183	5824
3184	5825	if (ret < 0)
3185	5826	goto runtime_put;
3186	5827
3187		- ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
3188		- if (ret < 0) {
3189		- v4l2_err(&dev->v4l2_dev, "start pipeline failed %d\n",
3190		- ret);
3191		- goto pipe_stream_off;
3192		- }
	5828	+ if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
	5829	+ ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
	5830	+ if (ret < 0) {
	5831	+ v4l2_err(&dev->v4l2_dev, "start pipeline failed %d\n",
	5832	+ ret);
	5833	+ goto pipe_stream_off;
	5834	+ }
3193	5835
3194		- if (sensor_info->mbus.type != V4L2_MBUS_PARALLEL &&
3195		- rkmodule_stream_seq != RKMODULE_START_STREAM_FRONT) {
3196		- ret = dev->pipe.set_stream(&dev->pipe, true);
3197		- if (ret < 0)
3198		- goto stop_stream;
	5836	+ if (sensor_info->mbus.type != V4L2_MBUS_PARALLEL &&
	5837	+ rkmodule_stream_seq != RKMODULE_START_STREAM_FRONT) {
	5838	+ ret = dev->pipe.set_stream(&dev->pipe, true);
	5839	+ if (ret < 0)
	5840	+ goto stop_stream;
	5841	+ }
3199	5842	}
3200		-
3201		- if (dev->hdr.mode == NO_HDR) {
3202		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING) {
3203		- rkcif_start_luma(&dev->luma_vdev,
	5843	+ if (dev->chip_id == CHIP_RV1126_CIF \|\|
	5844	+ dev->chip_id == CHIP_RV1126_CIF_LITE \|\|
	5845	+ dev->chip_id == CHIP_RK3568_CIF) {
	5846	+ if (dev->hdr.hdr_mode == NO_HDR) {
	5847	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING)
	5848	+ rkcif_start_luma(&dev->luma_vdev,
	5849	+ dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
	5850	+ } else if (dev->hdr.hdr_mode == HDR_X2) {
	5851	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
	5852	+ dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING)
	5853	+ rkcif_start_luma(&dev->luma_vdev,
	5854	+ dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
	5855	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
	5856	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
	5857	+ dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING &&
	5858	+ dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_STREAMING)
	5859	+ rkcif_start_luma(&dev->luma_vdev,
3204	5860	dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
3205	5861	}
3206		- } else if (dev->hdr.mode == HDR_X2) {
3207		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
3208		- dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING) {
3209		- rkcif_start_luma(&dev->luma_vdev,
3210		- dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
3211		- }
3212		- } else if (dev->hdr.mode == HDR_X3) {
3213		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
3214		- dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING &&
3215		- dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_STREAMING) {
3216		- rkcif_start_luma(&dev->luma_vdev,
3217		- dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
3218		- }
3219	5862	}
3220		-
3221	5863	dev->reset_work_cancel = false;
3222		- if (dev->hdr.mode == NO_HDR)
3223		- stream->streamon_timestamp = ktime_get_ns();
	5864	+ stream->cur_stream_mode \|= mode;
	5865	+ rkcif_monitor_reset_event(dev);
3224	5866	goto out;
3225	5867
3226	5868	stop_stream:
..	..	@@ -3250,6 +5892,15 @@
3250	5892	return ret;
3251	5893	}
3252	5894
	5895	+static int rkcif_start_streaming(struct vb2_queue *queue, unsigned int count)
	5896	+{
	5897	+ struct rkcif_stream *stream = queue->drv_priv;
	5898	+ int ret = 0;
	5899	+
	5900	+ ret = rkcif_do_start_stream(stream, RKCIF_STREAM_MODE_CAPTURE);
	5901	+ return ret;
	5902	+}
	5903	+
3253	5904	static struct vb2_ops rkcif_vb2_ops = {
3254	5905	.queue_setup = rkcif_queue_setup,
3255	5906	.buf_queue = rkcif_buf_queue,
..	..	@@ -3269,10 +5920,7 @@
3269	5920	q->io_modes = VB2_MMAP \| VB2_DMABUF;
3270	5921	q->drv_priv = stream;
3271	5922	q->ops = &rkcif_vb2_ops;
3272		- if (hw_dev->iommu_en)
3273		- q->mem_ops = &vb2_dma_sg_memops;
3274		- else
3275		- q->mem_ops = &vb2_dma_contig_memops;
	5923	+ q->mem_ops = hw_dev->mem_ops;
3276	5924	q->buf_struct_size = sizeof(struct rkcif_buffer);
3277	5925	if (stream->cifdev->is_use_dummybuf)
3278	5926	q->min_buffers_needed = 1;
..	..	@@ -3284,12 +5932,14 @@
3284	5932	q->allow_cache_hints = 1;
3285	5933	q->bidirectional = 1;
3286	5934	q->gfp_flags = GFP_DMA32;
	5935	+ if (hw_dev->is_dma_contig)
	5936	+ q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
3287	5937	return vb2_queue_init(q);
3288	5938	}
3289	5939
3290		-static void rkcif_set_fmt(struct rkcif_stream *stream,
3291		- struct v4l2_pix_format_mplane *pixm,
3292		- bool try)
	5940	+int rkcif_set_fmt(struct rkcif_stream *stream,
	5941	+ struct v4l2_pix_format_mplane *pixm,
	5942	+ bool try)
3293	5943	{
3294	5944	struct rkcif_device *dev = stream->cifdev;
3295	5945	const struct cif_output_fmt *fmt;
..	..	@@ -3299,9 +5949,12 @@
3299	5949	u32 xsubs = 1, ysubs = 1, i;
3300	5950	struct rkmodule_hdr_cfg hdr_cfg;
3301	5951	struct rkcif_extend_info *extend_line = &stream->extend_line;
3302		- int ret, vc;
	5952	+ int ret;
3303	5953
3304		- fmt = find_output_fmt(stream, pixm->pixelformat);
	5954	+ for (i = 0; i < RKCIF_MAX_PLANE; i++)
	5955	+ memset(&pixm->plane_fmt[i], 0, sizeof(struct v4l2_plane_pix_format));
	5956	+
	5957	+ fmt = rkcif_find_output_fmt(stream, pixm->pixelformat);
3305	5958	if (!fmt)
3306	5959	fmt = &out_fmts[0];
3307	5960
..	..	@@ -3310,9 +5963,18 @@
3310	5963
3311	5964	if (dev->terminal_sensor.sd) {
3312	5965	cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
3313		- &input_rect, stream->id, &vc);
	5966	+ &input_rect, stream->id,
	5967	+ &dev->channels[stream->id]);
3314	5968	stream->cif_fmt_in = cif_fmt_in;
	5969	+ } else {
	5970	+ v4l2_err(&stream->cifdev->v4l2_dev,
	5971	+ "terminal subdev does not exist\n");
	5972	+ return -EINVAL;
3315	5973	}
	5974	+
	5975	+ ret = rkcif_output_fmt_check(stream, fmt);
	5976	+ if (ret)
	5977	+ return -EINVAL;
3316	5978
3317	5979	if (dev->terminal_sensor.sd) {
3318	5980	ret = v4l2_subdev_call(dev->terminal_sensor.sd,
..	..	@@ -3320,9 +5982,9 @@
3320	5982	RKMODULE_GET_HDR_CFG,
3321	5983	&hdr_cfg);
3322	5984	if (!ret)
3323		- dev->hdr.mode = hdr_cfg.hdr_mode;
	5985	+ dev->hdr = hdr_cfg;
3324	5986	else
3325		- dev->hdr.mode = NO_HDR;
	5987	+ dev->hdr.hdr_mode = NO_HDR;
3326	5988
3327	5989	dev->terminal_sensor.raw_rect = input_rect;
3328	5990	}
..	..	@@ -3343,6 +6005,10 @@
3343	6005	fcc_xysubs(fmt->fourcc, &xsubs, &ysubs);
3344	6006
3345	6007	planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
	6008	+
	6009	+ if (cif_fmt_in && (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 \|\|
	6010	+ cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8))
	6011	+ stream->crop_enable = false;
3346	6012
3347	6013	for (i = 0; i < planes; i++) {
3348	6014	struct v4l2_plane_pix_format *plane_fmt;
..	..	@@ -3366,6 +6032,9 @@
3366	6032	}
3367	6033	}
3368	6034
	6035	+ if (dev->sditf_cnt > 1 && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	6036	+ height *= dev->sditf_cnt;
	6037	+
3369	6038	extend_line->pixm.height = height + RKMODULE_EXTEND_LINE;
3370	6039
3371	6040	/* compact mode need bytesperline 4bytes align,
..	..	@@ -3379,19 +6048,22 @@
3379	6048	}
3380	6049
3381	6050	if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
3382		- (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
	6051	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	6052	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
3383	6053	dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) &&
3384		- fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888) {
3385		- bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
3386		- } else if (fmt->fourcc == V4L2_PIX_FMT_GREY \|\|
3387		- fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
3388		- fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
3389		- fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
3390		- fmt->fourcc == V4L2_PIX_FMT_SBGGR8) {
	6054	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
	6055	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
3391	6056	bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
3392	6057	} else {
3393		- bpp = rkcif_align_bits_per_pixel(stream, fmt, i);
3394		- bpl = width * bpp / CIF_YUV_STORED_BIT_WIDTH;
	6058	+ if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
	6059	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
	6060	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565 &&
	6061	+ dev->chip_id >= CHIP_RK3588_CIF) {
	6062	+ bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
	6063	+ } else {
	6064	+ bpp = rkcif_align_bits_per_pixel(stream, fmt, i);
	6065	+ bpl = width * bpp / CIF_YUV_STORED_BIT_WIDTH;
	6066	+ }
3395	6067	}
3396	6068	size = bpl * height;
3397	6069	imagesize += size;
..	..	@@ -3431,6 +6103,7 @@
3431	6103	pixm->width, pixm->height,
3432	6104	stream->pixm.width, stream->pixm.height);
3433	6105	}
	6106	+ return 0;
3434	6107	}
3435	6108
3436	6109	void rkcif_stream_init(struct rkcif_device *dev, u32 id)
..	..	@@ -3445,6 +6118,9 @@
3445	6118	stream->cifdev = dev;
3446	6119
3447	6120	INIT_LIST_HEAD(&stream->buf_head);
	6121	+ INIT_LIST_HEAD(&stream->rx_buf_head);
	6122	+ INIT_LIST_HEAD(&stream->rx_buf_head_vicap);
	6123	+ INIT_LIST_HEAD(&stream->rockit_buf_head);
3448	6124	spin_lock_init(&stream->vbq_lock);
3449	6125	spin_lock_init(&stream->fps_lock);
3450	6126	stream->state = RKCIF_STATE_READY;
..	..	@@ -3480,6 +6156,7 @@
3480	6156	}
3481	6157
3482	6158	stream->is_high_align = false;
	6159	+ stream->is_finish_stop_dma = false;
3483	6160
3484	6161	if (dev->chip_id == CHIP_RV1126_CIF \|\|
3485	6162	dev->chip_id == CHIP_RV1126_CIF_LITE)
..	..	@@ -3499,7 +6176,14 @@
3499	6176	dev->wait_line_cache = 0;
3500	6177	dev->wait_line_bak = 0;
3501	6178	}
3502		-
	6179	+ stream->cur_stream_mode = 0;
	6180	+ stream->dma_en = 0;
	6181	+ stream->to_en_dma = 0;
	6182	+ stream->to_stop_dma = 0;
	6183	+ stream->to_en_scale = false;
	6184	+ stream->buf_owner = 0;
	6185	+ stream->buf_replace_cnt = 0;
	6186	+ stream->is_stop_capture = false;
3503	6187	}
3504	6188
3505	6189	static int rkcif_fh_open(struct file *filp)
..	..	@@ -3509,6 +6193,7 @@
3509	6193	struct rkcif_stream *stream = to_rkcif_stream(vnode);
3510	6194	struct rkcif_device *cifdev = stream->cifdev;
3511	6195	int ret;
	6196	+ int i = 0;
3512	6197
3513	6198	ret = rkcif_attach_hw(cifdev);
3514	6199	if (ret)
..	..	@@ -3524,31 +6209,35 @@
3524	6209	return ret;
3525	6210	}
3526	6211
3527		- /*
3528		- * Soft reset via CRU.
3529		- * Because CRU would reset iommu too, so there's not chance
3530		- * to reset cif once we hold buffers after buf queued
3531		- */
3532		- if (cifdev->chip_id == CHIP_RK1808_CIF \|\|
3533		- cifdev->chip_id == CHIP_RV1126_CIF \|\|
3534		- cifdev->chip_id == CHIP_RV1126_CIF_LITE \|\|
3535		- cifdev->chip_id == CHIP_RK3568_CIF) {
3536		- mutex_lock(&cifdev->stream_lock);
3537		- if (!atomic_read(&cifdev->fh_cnt))
3538		- rkcif_soft_reset(cifdev, true);
3539		- atomic_inc(&cifdev->fh_cnt);
3540		- mutex_unlock(&cifdev->stream_lock);
3541		- } else {
3542		- rkcif_soft_reset(cifdev, true);
	6212	+ ret = pm_runtime_resume_and_get(cifdev->dev);
	6213	+ if (ret < 0) {
	6214	+ v4l2_err(vdev, "Failed to get runtime pm, %d\n",
	6215	+ ret);
	6216	+ return ret;
3543	6217	}
3544	6218
3545	6219	ret = v4l2_fh_open(filp);
3546	6220	if (!ret) {
3547		- ret = v4l2_pipeline_pm_use(&vnode->vdev.entity, 1);
	6221	+ mutex_lock(&cifdev->stream_lock);
	6222	+ ret = v4l2_pipeline_pm_get(&vnode->vdev.entity);
	6223	+ v4l2_info(vdev, "open video, entity use_countt %d\n",
	6224	+ vnode->vdev.entity.use_count);
	6225	+ mutex_unlock(&cifdev->stream_lock);
3548	6226	if (ret < 0)
3549	6227	vb2_fop_release(filp);
3550	6228	}
3551		-
	6229	+ if (cifdev->sditf_cnt > 1) {
	6230	+ for (i = 0; i < cifdev->sditf_cnt; i++) {
	6231	+ if (cifdev->sditf[i]->sensor_sd)
	6232	+ ret \|= v4l2_subdev_call(cifdev->sditf[i]->sensor_sd,
	6233	+ core,
	6234	+ s_power,
	6235	+ 1);
	6236	+ }
	6237	+ if (ret < 0)
	6238	+ v4l2_err(vdev, "set sensor power on fail, ret %d\n",
	6239	+ ret);
	6240	+ }
3552	6241	return ret;
3553	6242	}
3554	6243
..	..	@@ -3559,22 +6248,30 @@
3559	6248	struct rkcif_stream *stream = to_rkcif_stream(vnode);
3560	6249	struct rkcif_device *cifdev = stream->cifdev;
3561	6250	int ret = 0;
	6251	+ int i = 0;
3562	6252
3563	6253	ret = vb2_fop_release(filp);
3564	6254	if (!ret) {
3565		- ret = v4l2_pipeline_pm_use(&vnode->vdev.entity, 0);
3566		- if (ret < 0)
3567		- v4l2_err(&cifdev->v4l2_dev,
3568		- "set pipeline power failed %d\n", ret);
	6255	+ mutex_lock(&cifdev->stream_lock);
	6256	+ v4l2_pipeline_pm_put(&vnode->vdev.entity);
	6257	+ v4l2_info(vdev, "close video, entity use_count %d\n",
	6258	+ vnode->vdev.entity.use_count);
	6259	+ mutex_unlock(&cifdev->stream_lock);
3569	6260	}
3570	6261
3571		- mutex_lock(&cifdev->stream_lock);
3572		- if (!atomic_dec_return(&cifdev->fh_cnt))
3573		- rkcif_soft_reset(cifdev, true);
3574		- else if (atomic_read(&cifdev->fh_cnt) < 0)
3575		- atomic_set(&cifdev->fh_cnt, 0);
3576		- mutex_unlock(&cifdev->stream_lock);
3577		-
	6262	+ pm_runtime_put_sync(cifdev->dev);
	6263	+ if (cifdev->sditf_cnt > 1) {
	6264	+ for (i = 0; i < cifdev->sditf_cnt; i++) {
	6265	+ if (cifdev->sditf[i]->sensor_sd)
	6266	+ ret \|= v4l2_subdev_call(cifdev->sditf[i]->sensor_sd,
	6267	+ core,
	6268	+ s_power,
	6269	+ 0);
	6270	+ }
	6271	+ if (ret < 0)
	6272	+ v4l2_err(vdev, "set sensor power on fail, ret %d\n",
	6273	+ ret);
	6274	+ }
3578	6275	return ret;
3579	6276	}
3580	6277
..	..	@@ -3584,6 +6281,9 @@
3584	6281	.unlocked_ioctl = video_ioctl2,
3585	6282	.poll = vb2_fop_poll,
3586	6283	.mmap = vb2_fop_mmap,
	6284	+#ifdef CONFIG_COMPAT
	6285	+ .compat_ioctl32 = video_ioctl2,
	6286	+#endif
3587	6287	};
3588	6288
3589	6289	static int rkcif_enum_input(struct file file, void priv,
..	..	@@ -3602,25 +6302,27 @@
3602	6302	struct v4l2_format *f)
3603	6303	{
3604	6304	struct rkcif_stream *stream = video_drvdata(file);
	6305	+ int ret = 0;
3605	6306
3606		- rkcif_set_fmt(stream, &f->fmt.pix_mp, true);
	6307	+ ret = rkcif_set_fmt(stream, &f->fmt.pix_mp, true);
3607	6308
3608		- return 0;
	6309	+ return ret;
3609	6310	}
3610	6311
3611	6312	static int rkcif_enum_framesizes(struct file file, void prov,
3612	6313	struct v4l2_frmsizeenum *fsize)
3613	6314	{
	6315	+ struct v4l2_frmsize_discrete *d = &fsize->discrete;
3614	6316	struct v4l2_frmsize_stepwise *s = &fsize->stepwise;
3615	6317	struct rkcif_stream *stream = video_drvdata(file);
3616	6318	struct rkcif_device *dev = stream->cifdev;
3617	6319	struct v4l2_rect input_rect;
3618		- int vc;
	6320	+ struct csi_channel_info csi_info;
3619	6321
3620	6322	if (fsize->index != 0)
3621	6323	return -EINVAL;
3622	6324
3623		- if (!find_output_fmt(stream, fsize->pixel_format))
	6325	+ if (!rkcif_find_output_fmt(stream, fsize->pixel_format))
3624	6326	return -EINVAL;
3625	6327
3626	6328	input_rect.width = RKCIF_DEFAULT_WIDTH;
..	..	@@ -3628,15 +6330,22 @@
3628	6330
3629	6331	if (dev->terminal_sensor.sd)
3630	6332	get_input_fmt(dev->terminal_sensor.sd,
3631		- &input_rect, stream->id, &vc);
	6333	+ &input_rect, stream->id,
	6334	+ &csi_info);
3632	6335
3633		- fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
3634		- s->min_width = CIF_MIN_WIDTH;
3635		- s->min_height = CIF_MIN_HEIGHT;
3636		- s->max_width = input_rect.width;
3637		- s->max_height = input_rect.height;
3638		- s->step_width = OUTPUT_STEP_WISE;
3639		- s->step_height = OUTPUT_STEP_WISE;
	6336	+ if (dev->hw_dev->adapt_to_usbcamerahal) {
	6337	+ fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
	6338	+ d->width = input_rect.width;
	6339	+ d->height = input_rect.height;
	6340	+ } else {
	6341	+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
	6342	+ s->min_width = CIF_MIN_WIDTH;
	6343	+ s->min_height = CIF_MIN_HEIGHT;
	6344	+ s->max_width = input_rect.width;
	6345	+ s->max_height = input_rect.height;
	6346	+ s->step_width = OUTPUT_STEP_WISE;
	6347	+ s->step_height = OUTPUT_STEP_WISE;
	6348	+ }
3640	6349
3641	6350	return 0;
3642	6351	}
..	..	@@ -3668,13 +6377,19 @@
3668	6377	fi.interval.denominator = 30;
3669	6378	}
3670	6379
3671		- fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
3672		- fival->stepwise.step.numerator = 1;
3673		- fival->stepwise.step.denominator = 1;
3674		- fival->stepwise.max.numerator = 1;
3675		- fival->stepwise.max.denominator = 1;
3676		- fival->stepwise.min.numerator = fi.interval.numerator;
3677		- fival->stepwise.min.denominator = fi.interval.denominator;
	6380	+ if (dev->hw_dev->adapt_to_usbcamerahal) {
	6381	+ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
	6382	+ fival->discrete.numerator = fi.interval.numerator;
	6383	+ fival->discrete.denominator = fi.interval.denominator;
	6384	+ } else {
	6385	+ fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
	6386	+ fival->stepwise.step.numerator = 1;
	6387	+ fival->stepwise.step.denominator = 1;
	6388	+ fival->stepwise.max.numerator = 1;
	6389	+ fival->stepwise.max.denominator = 1;
	6390	+ fival->stepwise.min.numerator = fi.interval.numerator;
	6391	+ fival->stepwise.min.denominator = fi.interval.denominator;
	6392	+ }
3678	6393
3679	6394	return 0;
3680	6395	}
..	..	@@ -3683,13 +6398,57 @@
3683	6398	struct v4l2_fmtdesc *f)
3684	6399	{
3685	6400	const struct cif_output_fmt *fmt = NULL;
	6401	+ struct rkcif_stream *stream = video_drvdata(file);
	6402	+ struct rkcif_device *dev = stream->cifdev;
	6403	+ const struct cif_input_fmt *cif_fmt_in = NULL;
	6404	+ struct v4l2_rect input_rect;
	6405	+ int i = 0;
	6406	+ int ret = 0;
	6407	+ int fource_idx = 0;
3686	6408
3687	6409	if (f->index >= ARRAY_SIZE(out_fmts))
3688	6410	return -EINVAL;
3689	6411
3690		- fmt = &out_fmts[f->index];
3691		- f->pixelformat = fmt->fourcc;
	6412	+ if (dev->terminal_sensor.sd) {
	6413	+ cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
	6414	+ &input_rect, stream->id,
	6415	+ &dev->channels[stream->id]);
	6416	+ stream->cif_fmt_in = cif_fmt_in;
	6417	+ } else {
	6418	+ v4l2_err(&stream->cifdev->v4l2_dev,
	6419	+ "terminal subdev does not exist\n");
	6420	+ return -EINVAL;
	6421	+ }
3692	6422
	6423	+ if (f->index != 0)
	6424	+ fource_idx = stream->new_fource_idx;
	6425	+
	6426	+ for (i = fource_idx; i < ARRAY_SIZE(out_fmts); i++) {
	6427	+ fmt = &out_fmts[i];
	6428	+ ret = rkcif_output_fmt_check(stream, fmt);
	6429	+ if (!ret) {
	6430	+ f->pixelformat = fmt->fourcc;
	6431	+ stream->new_fource_idx = i + 1;
	6432	+ break;
	6433	+ }
	6434	+ }
	6435	+ if (i == ARRAY_SIZE(out_fmts))
	6436	+ return -EINVAL;
	6437	+
	6438	+ switch (f->pixelformat) {
	6439	+ case V4l2_PIX_FMT_EBD8:
	6440	+ strscpy(f->description,
	6441	+ "Embedded data 8-bit",
	6442	+ sizeof(f->description));
	6443	+ break;
	6444	+ case V4l2_PIX_FMT_SPD16:
	6445	+ strscpy(f->description,
	6446	+ "Shield pix data 16-bit",
	6447	+ sizeof(f->description));
	6448	+ break;
	6449	+ default:
	6450	+ break;
	6451	+ }
3693	6452	return 0;
3694	6453	}
3695	6454
..	..	@@ -3698,15 +6457,16 @@
3698	6457	{
3699	6458	struct rkcif_stream *stream = video_drvdata(file);
3700	6459	struct rkcif_device *dev = stream->cifdev;
	6460	+ int ret = 0;
3701	6461
3702	6462	if (vb2_is_busy(&stream->vnode.buf_queue)) {
3703	6463	v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
3704	6464	return -EBUSY;
3705	6465	}
3706	6466
3707		- rkcif_set_fmt(stream, &f->fmt.pix_mp, false);
	6467	+ ret = rkcif_set_fmt(stream, &f->fmt.pix_mp, false);
3708	6468
3709		- return 0;
	6469	+ return ret;
3710	6470	}
3711	6471
3712	6472	static int rkcif_g_fmt_vid_cap_mplane(struct file file, void fh,
..	..	@@ -3733,8 +6493,8 @@
3733	6493	return 0;
3734	6494	}
3735	6495
3736		-static int rkcif_cropcap(struct file file, void fh,
3737		- struct v4l2_cropcap *cap)
	6496	+static __maybe_unused int rkcif_cropcap(struct file file, void fh,
	6497	+ struct v4l2_cropcap *cap)
3738	6498	{
3739	6499	struct rkcif_stream *stream = video_drvdata(file);
3740	6500	struct rkcif_device *dev = stream->cifdev;
..	..	@@ -3760,78 +6520,16 @@
3760	6520	return ret;
3761	6521	}
3762	6522
3763		-static int rkcif_s_crop(struct file file, void fh, const struct v4l2_crop *a)
3764		-{
3765		- struct rkcif_stream *stream = video_drvdata(file);
3766		- struct rkcif_device *dev = stream->cifdev;
3767		- const struct v4l2_rect *rect = &a->c;
3768		- struct v4l2_rect sensor_crop;
3769		- struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
3770		- int ret;
3771		-
3772		- ret = rkcif_sanity_check_fmt(stream, rect);
3773		- if (ret) {
3774		- v4l2_err(&dev->v4l2_dev, "set crop failed\n");
3775		- return ret;
3776		- }
3777		-
3778		- if (stream->crop_mask & CROP_SRC_SENSOR) {
3779		- sensor_crop = stream->crop[CROP_SRC_SENSOR];
3780		- if (rect->left + rect->width > sensor_crop.width \|\|
3781		- rect->top + rect->height > sensor_crop.height) {
3782		- v4l2_err(&dev->v4l2_dev,
3783		- "crop size is bigger than sensor input:left:%d, top:%d, width:%d, height:%d\n",
3784		- sensor_crop.left, sensor_crop.top, sensor_crop.width, sensor_crop.height);
3785		- return -EINVAL;
3786		- }
3787		- } else {
3788		- if (rect->left + rect->width > raw_rect->width \|\|
3789		- rect->top + rect->height > raw_rect->height) {
3790		- v4l2_err(&dev->v4l2_dev,
3791		- "crop size is bigger than sensor raw input:left:%d, top:%d, width:%d, height:%d\n",
3792		- raw_rect->left, raw_rect->top, raw_rect->width, raw_rect->height);
3793		- return -EINVAL;
3794		- }
3795		- }
3796		-
3797		- stream->crop[CROP_SRC_USR] = *rect;
3798		- stream->crop_enable = true;
3799		- stream->crop_mask \|= CROP_SRC_USR_MASK;
3800		- stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_USR];
3801		- if (stream->crop_mask & CROP_SRC_SENSOR) {
3802		- stream->crop[CROP_SRC_ACT].left = sensor_crop.left + stream->crop[CROP_SRC_USR].left;
3803		- stream->crop[CROP_SRC_ACT].top = sensor_crop.top + stream->crop[CROP_SRC_USR].top;
3804		- }
3805		-
3806		- if (stream->state == RKCIF_STATE_STREAMING) {
3807		- stream->crop_dyn_en = true;
3808		-
3809		- v4l2_info(&dev->v4l2_dev, "enable dynamic crop, S_CROP(%ux%u@%u:%u) type: %d\n",
3810		- rect->width, rect->height, rect->left, rect->top, a->type);
3811		- } else {
3812		- v4l2_info(&dev->v4l2_dev, "static crop, S_CROP(%ux%u@%u:%u) type: %d\n",
3813		- rect->width, rect->height, rect->left, rect->top, a->type);
3814		- }
3815		-
3816		- return ret;
3817		-}
3818		-
3819		-static int rkcif_g_crop(struct file file, void fh, struct v4l2_crop *a)
3820		-{
3821		- struct rkcif_stream *stream = video_drvdata(file);
3822		-
3823		- a->c = stream->crop[CROP_SRC_ACT];
3824		-
3825		- return 0;
3826		-}
3827		-
3828	6523	static int rkcif_s_selection(struct file file, void fh,
3829		- struct v4l2_selection *s)
	6524	+ struct v4l2_selection *s)
3830	6525	{
3831	6526	struct rkcif_stream *stream = video_drvdata(file);
3832	6527	struct rkcif_device *dev = stream->cifdev;
3833	6528	struct v4l2_subdev *sensor_sd;
3834	6529	struct v4l2_subdev_selection sd_sel;
	6530	+ const struct v4l2_rect *rect = &s->r;
	6531	+ struct v4l2_rect sensor_crop;
	6532	+ struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
3835	6533	u16 pad = 0;
3836	6534	int ret = 0;
3837	6535
..	..	@@ -3840,18 +6538,69 @@
3840	6538	goto err;
3841	6539	}
3842	6540
3843		- sensor_sd = get_remote_sensor(stream, &pad);
	6541	+ if (s->target == V4L2_SEL_TGT_CROP_BOUNDS) {
	6542	+ sensor_sd = get_remote_sensor(stream, &pad);
3844	6543
3845		- sd_sel.r = s->r;
3846		- sd_sel.pad = pad;
3847		- sd_sel.target = s->target;
3848		- sd_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	6544	+ sd_sel.r = s->r;
	6545	+ sd_sel.pad = pad;
	6546	+ sd_sel.target = s->target;
	6547	+ sd_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
3849	6548
3850		- ret = v4l2_subdev_call(sensor_sd, pad, set_selection, NULL, &sd_sel);
3851		- if (!ret) {
3852		- s->r = sd_sel.r;
3853		- v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s: pad:%d, which:%d, target:%d\n",
3854		- __func__, pad, sd_sel.which, sd_sel.target);
	6549	+ ret = v4l2_subdev_call(sensor_sd, pad, set_selection, NULL, &sd_sel);
	6550	+ if (!ret) {
	6551	+ s->r = sd_sel.r;
	6552	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s: pad:%d, which:%d, target:%d\n",
	6553	+ __func__, pad, sd_sel.which, sd_sel.target);
	6554	+ }
	6555	+ } else if (s->target == V4L2_SEL_TGT_CROP) {
	6556	+ ret = rkcif_sanity_check_fmt(stream, rect);
	6557	+ if (ret) {
	6558	+ v4l2_err(&dev->v4l2_dev, "set crop failed\n");
	6559	+ return ret;
	6560	+ }
	6561	+
	6562	+ if (stream->crop_mask & CROP_SRC_SENSOR) {
	6563	+ sensor_crop = stream->crop[CROP_SRC_SENSOR];
	6564	+ if (rect->left + rect->width > sensor_crop.width \|\|
	6565	+ rect->top + rect->height > sensor_crop.height) {
	6566	+ v4l2_err(&dev->v4l2_dev,
	6567	+ "crop size is bigger than sensor input:left:%d, top:%d, width:%d, height:%d\n",
	6568	+ sensor_crop.left, sensor_crop.top,
	6569	+ sensor_crop.width, sensor_crop.height);
	6570	+ return -EINVAL;
	6571	+ }
	6572	+ } else {
	6573	+ if (rect->left + rect->width > raw_rect->width \|\|
	6574	+ rect->top + rect->height > raw_rect->height) {
	6575	+ v4l2_err(&dev->v4l2_dev,
	6576	+ "crop size is bigger than sensor raw input:left:%d, top:%d, width:%d, height:%d\n",
	6577	+ raw_rect->left, raw_rect->top,
	6578	+ raw_rect->width, raw_rect->height);
	6579	+ return -EINVAL;
	6580	+ }
	6581	+ }
	6582	+
	6583	+ stream->crop[CROP_SRC_USR] = *rect;
	6584	+ stream->crop_enable = true;
	6585	+ stream->crop_mask \|= CROP_SRC_USR_MASK;
	6586	+ stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_USR];
	6587	+ if (stream->crop_mask & CROP_SRC_SENSOR) {
	6588	+ sensor_crop = stream->crop[CROP_SRC_SENSOR];
	6589	+ stream->crop[CROP_SRC_ACT].left = sensor_crop.left + stream->crop[CROP_SRC_USR].left;
	6590	+ stream->crop[CROP_SRC_ACT].top = sensor_crop.top + stream->crop[CROP_SRC_USR].top;
	6591	+ }
	6592	+
	6593	+ if (stream->state == RKCIF_STATE_STREAMING) {
	6594	+ stream->crop_dyn_en = true;
	6595	+
	6596	+ v4l2_info(&dev->v4l2_dev, "enable dynamic crop, S_SELECTION(%ux%u@%u:%u) target: %d\n",
	6597	+ rect->width, rect->height, rect->left, rect->top, s->target);
	6598	+ } else {
	6599	+ v4l2_info(&dev->v4l2_dev, "static crop, S_SELECTION(%ux%u@%u:%u) target: %d\n",
	6600	+ rect->width, rect->height, rect->left, rect->top, s->target);
	6601	+ }
	6602	+ } else {
	6603	+ goto err;
3855	6604	}
3856	6605
3857	6606	return ret;
..	..	@@ -3861,7 +6610,7 @@
3861	6610	}
3862	6611
3863	6612	static int rkcif_g_selection(struct file file, void fh,
3864		- struct v4l2_selection *s)
	6613	+ struct v4l2_selection *s)
3865	6614	{
3866	6615	struct rkcif_stream *stream = video_drvdata(file);
3867	6616	struct rkcif_device *dev = stream->cifdev;
..	..	@@ -3912,19 +6661,127 @@
3912	6661	return -EINVAL;
3913	6662	}
3914	6663
	6664	+static int rkcif_get_max_common_div(int a, int b)
	6665	+{
	6666	+ int remainder = a % b;
	6667	+
	6668	+ while (remainder != 0) {
	6669	+ a = b;
	6670	+ b = remainder;
	6671	+ remainder = a % b;
	6672	+ }
	6673	+ return b;
	6674	+}
	6675	+
	6676	+void rkcif_set_fps(struct rkcif_stream stream, struct rkcif_fps fps)
	6677	+{
	6678	+ struct rkcif_sensor_info *sensor = &stream->cifdev->terminal_sensor;
	6679	+ struct rkcif_device *cif_dev = stream->cifdev;
	6680	+ struct rkcif_stream *tmp_stream = NULL;
	6681	+ u32 numerator, denominator;
	6682	+ u32 def_fps = 0;
	6683	+ u32 cur_fps = 0;
	6684	+ int cap_m, skip_n;
	6685	+ int i = 0;
	6686	+ int max_common_div;
	6687	+ bool skip_en = false;
	6688	+ s32 vblank_def = 0;
	6689	+ s32 vblank_curr = 0;
	6690	+ int ret = 0;
	6691	+
	6692	+ if (!stream->cifdev->terminal_sensor.sd) {
	6693	+ ret = rkcif_update_sensor_info(stream);
	6694	+ if (ret) {
	6695	+ v4l2_err(&stream->cifdev->v4l2_dev,
	6696	+ "%s update sensor info fail\n",
	6697	+ __func__);
	6698	+ return;
	6699	+ }
	6700	+
	6701	+ }
	6702	+ if (!stream->cifdev->terminal_sensor.sd)
	6703	+ return;
	6704	+ numerator = sensor->fi.interval.numerator;
	6705	+ denominator = sensor->fi.interval.denominator;
	6706	+ def_fps = denominator / numerator;
	6707	+
	6708	+ vblank_def = rkcif_get_sensor_vblank_def(cif_dev);
	6709	+ vblank_curr = rkcif_get_sensor_vblank(cif_dev);
	6710	+ if (vblank_def)
	6711	+ cur_fps = def_fps * (u32)(vblank_def + sensor->raw_rect.height) /
	6712	+ (u32)(vblank_curr + sensor->raw_rect.height);
	6713	+ else
	6714	+ cur_fps = def_fps;
	6715	+
	6716	+ if (fps->fps == 0 \|\| fps->fps > cur_fps) {
	6717	+ v4l2_err(&stream->cifdev->v4l2_dev,
	6718	+ "set fps %d fps failed, current fps %d fps\n",
	6719	+ fps->fps, cur_fps);
	6720	+ return;
	6721	+ }
	6722	+ cap_m = fps->fps;
	6723	+ skip_n = cur_fps - fps->fps;
	6724	+ max_common_div = rkcif_get_max_common_div(cap_m, skip_n);
	6725	+ cap_m /= max_common_div;
	6726	+ skip_n /= max_common_div;
	6727	+ if (cap_m > 64) {
	6728	+ skip_n = skip_n / (cap_m / 64);
	6729	+ if (skip_n == 0)
	6730	+ skip_n = 1;
	6731	+ cap_m = 64;
	6732	+ }
	6733	+ if (skip_n > 7) {
	6734	+ cap_m = cap_m / (skip_n / 7);
	6735	+ if (cap_m == 0)
	6736	+ cap_m = 1;
	6737	+ skip_n = 7;
	6738	+ }
	6739	+
	6740	+ if (fps->fps == cur_fps)
	6741	+ skip_en = false;
	6742	+ else
	6743	+ skip_en = true;
	6744	+
	6745	+ if (fps->ch_num > 1 && fps->ch_num < 4) {
	6746	+ for (i = 0; i < fps->ch_num; i++) {
	6747	+ tmp_stream = &cif_dev->stream[i];
	6748	+ if (skip_en) {
	6749	+ tmp_stream->skip_info.skip_to_en = true;
	6750	+ tmp_stream->skip_info.cap_m = cap_m;
	6751	+ tmp_stream->skip_info.skip_n = skip_n;
	6752	+ } else {
	6753	+ tmp_stream->skip_info.skip_to_dis = true;
	6754	+ }
	6755	+ }
	6756	+ } else {
	6757	+ if (skip_en) {
	6758	+ stream->skip_info.skip_to_en = true;
	6759	+ stream->skip_info.cap_m = cap_m;
	6760	+ stream->skip_info.skip_n = skip_n;
	6761	+ } else {
	6762	+ stream->skip_info.skip_to_dis = true;
	6763	+ }
	6764	+ }
	6765	+ v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
	6766	+ "skip_to_en %d, cap_m %d, skip_n %d\n",
	6767	+ stream->skip_info.skip_to_en,
	6768	+ cap_m,
	6769	+ skip_n);
	6770	+}
	6771	+
3915	6772	static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
3916	6773	enum rkmodule_reset_src reset_src);
3917	6774
3918	6775	static long rkcif_ioctl_default(struct file file, void fh,
3919		- bool valid_prio, unsigned int cmd, void *arg)
	6776	+ bool valid_prio, unsigned int cmd, void *arg)
3920	6777	{
3921	6778	struct rkcif_stream *stream = video_drvdata(file);
3922	6779	struct rkcif_device *dev = stream->cifdev;
3923	6780	const struct cif_input_fmt *in_fmt;
3924	6781	struct v4l2_rect rect;
3925		- int vc = 0;
3926		- struct rkcif_reset_info *reset_info;
3927		- int reset_src = 0;
	6782	+ struct csi_channel_info csi_info;
	6783	+ struct rkcif_fps fps;
	6784	+ int reset_src;
3928	6785
3929	6786	switch (cmd) {
3930	6787	case RKCIF_CMD_GET_CSI_MEMORY_MODE:
..	..	@@ -3939,7 +6796,8 @@
3939	6796	break;
3940	6797	case RKCIF_CMD_SET_CSI_MEMORY_MODE:
3941	6798	if (dev->terminal_sensor.sd) {
3942		- in_fmt = get_input_fmt(dev->terminal_sensor.sd, &rect, 0, &vc);
	6799	+ in_fmt = get_input_fmt(dev->terminal_sensor.sd,
	6800	+ &rect, 0, &csi_info);
3943	6801	if (in_fmt == NULL) {
3944	6802	v4l2_err(&dev->v4l2_dev, "can't get sensor input format\n");
3945	6803	return -EINVAL;
..	..	@@ -3965,11 +6823,9 @@
3965	6823	stream->is_high_align = false;
3966	6824	}
3967	6825	break;
3968		- case RKCIF_CMD_GET_RESET_INFO:
3969		- reset_info = (struct rkcif_reset_info *)arg;
3970		- *reset_info = dev->hw_dev->reset_info;
3971		- if (dev->hw_dev->reset_info.is_need_reset)
3972		- dev->hw_dev->reset_info.is_need_reset = 0;
	6826	+ case RKCIF_CMD_SET_FPS:
	6827	+ fps = (struct rkcif_fps )arg;
	6828	+ rkcif_set_fps(stream, &fps);
3973	6829	break;
3974	6830	case RKCIF_CMD_SET_RESET:
3975	6831	reset_src = (int )arg;
..	..	@@ -3993,13 +6849,10 @@
3993	6849	.vidioc_streamoff = vb2_ioctl_streamoff,
3994	6850	.vidioc_enum_input = rkcif_enum_input,
3995	6851	.vidioc_try_fmt_vid_cap_mplane = rkcif_try_fmt_vid_cap_mplane,
3996		- .vidioc_enum_fmt_vid_cap_mplane = rkcif_enum_fmt_vid_cap_mplane,
	6852	+ .vidioc_enum_fmt_vid_cap = rkcif_enum_fmt_vid_cap_mplane,
3997	6853	.vidioc_s_fmt_vid_cap_mplane = rkcif_s_fmt_vid_cap_mplane,
3998	6854	.vidioc_g_fmt_vid_cap_mplane = rkcif_g_fmt_vid_cap_mplane,
3999	6855	.vidioc_querycap = rkcif_querycap,
4000		- .vidioc_cropcap = rkcif_cropcap,
4001		- .vidioc_s_crop = rkcif_s_crop,
4002		- .vidioc_g_crop = rkcif_g_crop,
4003	6856	.vidioc_s_selection = rkcif_s_selection,
4004	6857	.vidioc_g_selection = rkcif_g_selection,
4005	6858	.vidioc_enum_frameintervals = rkcif_enum_frameintervals,
..	..	@@ -4007,8 +6860,58 @@
4007	6860	.vidioc_default = rkcif_ioctl_default,
4008	6861	};
4009	6862
	6863	+void rkcif_vb_done_oneframe(struct rkcif_stream *stream,
	6864	+ struct vb2_v4l2_buffer *vb_done)
	6865	+{
	6866	+ const struct cif_output_fmt *fmt = stream->cif_fmt_out;
	6867	+ u32 i;
	6868	+
	6869	+ /* Dequeue a filled buffer */
	6870	+ for (i = 0; i < fmt->mplanes; i++) {
	6871	+ vb2_set_plane_payload(&vb_done->vb2_buf, i,
	6872	+ stream->pixm.plane_fmt[i].sizeimage);
	6873	+ }
	6874	+
	6875	+ vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE);
	6876	+ v4l2_dbg(2, rkcif_debug, &stream->cifdev->v4l2_dev,
	6877	+ "stream[%d] vb done, index: %d, sequence %d\n", stream->id,
	6878	+ vb_done->vb2_buf.index, vb_done->sequence);
	6879	+}
	6880	+
	6881	+static void rkcif_tasklet_handle(unsigned long data)
	6882	+{
	6883	+ struct rkcif_stream stream = (struct rkcif_stream )data;
	6884	+ struct rkcif_buffer *buf = NULL;
	6885	+ unsigned long flags = 0;
	6886	+ LIST_HEAD(local_list);
	6887	+
	6888	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	6889	+ list_replace_init(&stream->vb_done_list, &local_list);
	6890	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	6891	+
	6892	+ while (!list_empty(&local_list)) {
	6893	+ buf = list_first_entry(&local_list,
	6894	+ struct rkcif_buffer, queue);
	6895	+ list_del(&buf->queue);
	6896	+ rkcif_vb_done_oneframe(stream, &buf->vb);
	6897	+ }
	6898	+}
	6899	+
	6900	+void rkcif_vb_done_tasklet(struct rkcif_stream stream, struct rkcif_buffer buf)
	6901	+{
	6902	+ unsigned long flags = 0;
	6903	+
	6904	+ if (!stream \|\| !buf)
	6905	+ return;
	6906	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	6907	+ list_add_tail(&buf->queue, &stream->vb_done_list);
	6908	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	6909	+ tasklet_schedule(&stream->vb_done_tasklet);
	6910	+}
	6911	+
4010	6912	static void rkcif_unregister_stream_vdev(struct rkcif_stream *stream)
4011	6913	{
	6914	+ tasklet_kill(&stream->vb_done_tasklet);
4012	6915	media_entity_cleanup(&stream->vnode.vdev.entity);
4013	6916	video_unregister_device(&stream->vnode.vdev);
4014	6917	}
..	..	@@ -4042,6 +6945,7 @@
4042	6945	vdev_name = CIF_DVP_VDEV_NAME;
4043	6946	break;
4044	6947	default:
	6948	+ ret = -EINVAL;
4045	6949	v4l2_err(v4l2_dev, "Invalid stream\n");
4046	6950	goto unreg;
4047	6951	}
..	..	@@ -4064,6 +6968,7 @@
4064	6968	vdev_name = CIF_MIPI_ID3_VDEV_NAME;
4065	6969	break;
4066	6970	default:
	6971	+ ret = -EINVAL;
4067	6972	v4l2_err(v4l2_dev, "Invalid stream\n");
4068	6973	goto unreg;
4069	6974	}
..	..	@@ -4082,6 +6987,7 @@
4082	6987	vdev_name = CIF_DVP_ID3_VDEV_NAME;
4083	6988	break;
4084	6989	default:
	6990	+ ret = -EINVAL;
4085	6991	v4l2_err(v4l2_dev, "Invalid stream\n");
4086	6992	goto unreg;
4087	6993	}
..	..	@@ -4108,7 +7014,7 @@
4108	7014	V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
4109	7015	vdev->queue = &node->buf_queue;
4110	7016
4111		- ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
	7017	+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
4112	7018	if (ret < 0) {
4113	7019	v4l2_err(v4l2_dev,
4114	7020	"video_register_device failed with error %d\n", ret);
..	..	@@ -4119,6 +7025,11 @@
4119	7025	if (ret < 0)
4120	7026	goto unreg;
4121	7027
	7028	+ INIT_LIST_HEAD(&stream->vb_done_list);
	7029	+ tasklet_init(&stream->vb_done_tasklet,
	7030	+ rkcif_tasklet_handle,
	7031	+ (unsigned long)stream);
	7032	+ tasklet_disable(&stream->vb_done_tasklet);
4122	7033	return 0;
4123	7034	unreg:
4124	7035	video_unregister_device(vdev);
..	..	@@ -4151,7 +7062,7 @@
4151	7062	if (ret < 0)
4152	7063	goto err;
4153	7064	}
4154		-
	7065	+ dev->num_channels = stream_num;
4155	7066	return 0;
4156	7067	err:
4157	7068	for (j = 0; j < i; j++) {
..	..	@@ -4219,8 +7130,8 @@
4219	7130	}
4220	7131
4221	7132	static struct v4l2_rect rkcif_lvds_sd_get_crop(struct rkcif_lvds_subdev subdev,
4222		- struct v4l2_subdev_pad_config *cfg,
4223		- enum v4l2_subdev_format_whence which)
	7133	+ struct v4l2_subdev_pad_config *cfg,
	7134	+ enum v4l2_subdev_format_whence which)
4224	7135	{
4225	7136	if (which == V4L2_SUBDEV_FORMAT_TRY)
4226	7137	return v4l2_subdev_get_try_crop(&subdev->sd, cfg, RKCIF_LVDS_PAD_SINK);
..	..	@@ -4229,8 +7140,8 @@
4229	7140	}
4230	7141
4231	7142	static int rkcif_lvds_sd_set_selection(struct v4l2_subdev *sd,
4232		- struct v4l2_subdev_pad_config *cfg,
4233		- struct v4l2_subdev_selection *sel)
	7143	+ struct v4l2_subdev_pad_config *cfg,
	7144	+ struct v4l2_subdev_selection *sel)
4234	7145	{
4235	7146	struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
4236	7147	struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
..	..	@@ -4245,8 +7156,8 @@
4245	7156	}
4246	7157
4247	7158	static int rkcif_lvds_sd_get_selection(struct v4l2_subdev *sd,
4248		- struct v4l2_subdev_pad_config *cfg,
4249		- struct v4l2_subdev_selection *sel)
	7159	+ struct v4l2_subdev_pad_config *cfg,
	7160	+ struct v4l2_subdev_selection *sel)
4250	7161	{
4251	7162	struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
4252	7163	struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
..	..	@@ -4302,13 +7213,13 @@
4302	7213	return -EINVAL;
4303	7214	}
4304	7215
4305		-static int rkcif_lvds_g_mbus_config(struct v4l2_subdev *sd,
	7216	+static int rkcif_lvds_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
4306	7217	struct v4l2_mbus_config *mbus)
4307	7218	{
4308	7219	struct v4l2_subdev *sensor_sd = get_lvds_remote_sensor(sd);
4309	7220	int ret;
4310	7221
4311		- ret = v4l2_subdev_call(sensor_sd, video, g_mbus_config, mbus);
	7222	+ ret = v4l2_subdev_call(sensor_sd, pad, get_mbus_config, 0, mbus);
4312	7223	if (ret)
4313	7224	return ret;
4314	7225
..	..	@@ -4331,12 +7242,13 @@
4331	7242	}
4332	7243
4333	7244	static int rkcif_sof_subscribe_event(struct v4l2_subdev sd, struct v4l2_fh fh,
4334		- struct v4l2_event_subscription *sub)
	7245	+ struct v4l2_event_subscription *sub)
4335	7246	{
4336		- if (sub->type != V4L2_EVENT_FRAME_SYNC)
	7247	+ if (sub->type == V4L2_EVENT_FRAME_SYNC \|\|
	7248	+ sub->type == V4L2_EVENT_RESET_DEV)
	7249	+ return v4l2_event_subscribe(fh, sub, RKCIF_V4L2_EVENT_ELEMS, NULL);
	7250	+ else
4337	7251	return -EINVAL;
4338		-
4339		- return v4l2_event_subscribe(fh, sub, 0, NULL);
4340	7252	}
4341	7253
4342	7254	static const struct media_entity_operations rkcif_lvds_sd_media_ops = {
..	..	@@ -4349,10 +7261,10 @@
4349	7261	.get_fmt = rkcif_lvds_sd_get_fmt,
4350	7262	.set_selection = rkcif_lvds_sd_set_selection,
4351	7263	.get_selection = rkcif_lvds_sd_get_selection,
	7264	+ .get_mbus_config = rkcif_lvds_g_mbus_config,
4352	7265	};
4353	7266
4354	7267	static const struct v4l2_subdev_video_ops rkcif_lvds_sd_video_ops = {
4355		- .g_mbus_config = rkcif_lvds_g_mbus_config,
4356	7268	.s_stream = rkcif_lvds_sd_s_stream,
4357	7269	};
4358	7270
..	..	@@ -4390,10 +7302,12 @@
4390	7302	return 0;
4391	7303	}
4392	7304
4393		-static void rkcif_lvds_set_sof(struct rkcif_device *dev, u32 seq)
	7305	+static u32 rkcif_lvds_set_sof(struct rkcif_device *dev, u32 seq)
4394	7306	{
4395	7307	if (dev)
4396	7308	atomic_set(&dev->lvds_subdev.frm_sync_seq, seq);
	7309	+
	7310	+ return 0;
4397	7311	}
4398	7312
4399	7313	int rkcif_register_lvds_subdev(struct rkcif_device *dev)
..	..	@@ -4402,6 +7316,7 @@
4402	7316	struct rkcif_lvds_subdev *lvds_subdev = &dev->lvds_subdev;
4403	7317	struct v4l2_subdev *sd;
4404	7318	int ret;
	7319	+ int pad_num = 4;
4405	7320
4406	7321	memset(lvds_subdev, 0, sizeof(*lvds_subdev));
4407	7322	lvds_subdev->cifdev = dev;
..	..	@@ -4410,7 +7325,7 @@
4410	7325	v4l2_subdev_init(sd, &rkcif_lvds_sd_ops);
4411	7326	sd->flags \|= V4L2_SUBDEV_FL_HAS_DEVNODE \| V4L2_SUBDEV_FL_HAS_EVENTS;
4412	7327	sd->entity.ops = &rkcif_lvds_sd_media_ops;
4413		- if (dev->chip_id == CHIP_RV1126_CIF)
	7328	+ if (dev->chip_id != CHIP_RV1126_CIF_LITE)
4414	7329	snprintf(sd->name, sizeof(sd->name), "rkcif-lvds-subdev");
4415	7330	else
4416	7331	snprintf(sd->name, sizeof(sd->name), "rkcif-lite-lvds-subdev");
..	..	@@ -4421,6 +7336,13 @@
4421	7336	lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID1].flags = MEDIA_PAD_FL_SOURCE;
4422	7337	lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID2].flags = MEDIA_PAD_FL_SOURCE;
4423	7338	lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID3].flags = MEDIA_PAD_FL_SOURCE;
	7339	+ if (dev->chip_id == CHIP_RV1106_CIF) {
	7340	+ lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID0].flags = MEDIA_PAD_FL_SOURCE;
	7341	+ lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID1].flags = MEDIA_PAD_FL_SOURCE;
	7342	+ lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID2].flags = MEDIA_PAD_FL_SOURCE;
	7343	+ lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID3].flags = MEDIA_PAD_FL_SOURCE;
	7344	+ pad_num = RKCIF_LVDS_PAD_MAX;
	7345	+ }
4424	7346
4425	7347	lvds_subdev->in_fmt.width = RKCIF_DEFAULT_WIDTH;
4426	7348	lvds_subdev->in_fmt.height = RKCIF_DEFAULT_HEIGHT;
..	..	@@ -4429,7 +7351,7 @@
4429	7351	lvds_subdev->crop.width = RKCIF_DEFAULT_WIDTH;
4430	7352	lvds_subdev->crop.height = RKCIF_DEFAULT_HEIGHT;
4431	7353
4432		- ret = media_entity_pads_init(&sd->entity, RKCIF_LVDS_PAD_MAX,
	7354	+ ret = media_entity_pads_init(&sd->entity, pad_num,
4433	7355	lvds_subdev->pads);
4434	7356	if (ret < 0)
4435	7357	return ret;
..	..	@@ -4481,10 +7403,12 @@
4481	7403	return 0;
4482	7404	}
4483	7405
4484		-static void rkcif_dvp_set_sof(struct rkcif_device *dev, u32 seq)
	7406	+static u32 rkcif_dvp_set_sof(struct rkcif_device *dev, u32 seq)
4485	7407	{
4486	7408	if (dev)
4487	7409	atomic_set(&dev->dvp_sof_subdev.frm_sync_seq, seq);
	7410	+
	7411	+ return 0;
4488	7412	}
4489	7413
4490	7414	static const struct v4l2_subdev_core_ops rkcif_dvp_sof_sd_core_ops = {
..	..	@@ -4537,28 +7461,6 @@
4537	7461	v4l2_device_unregister_subdev(sd);
4538	7462	}
4539	7463
4540		-
4541		-static void rkcif_vb_done_oneframe(struct rkcif_stream *stream,
4542		- struct vb2_v4l2_buffer *vb_done)
4543		-{
4544		- const struct cif_output_fmt *fmt = stream->cif_fmt_out;
4545		- u32 i;
4546		-
4547		- /* Dequeue a filled buffer */
4548		- for (i = 0; i < fmt->mplanes; i++) {
4549		- vb2_set_plane_payload(&vb_done->vb2_buf, i,
4550		- stream->pixm.plane_fmt[i].sizeimage);
4551		- }
4552		-
4553		- if (stream->cifdev->hdr.mode == NO_HDR)
4554		- vb_done->vb2_buf.timestamp = ktime_get_ns();
4555		-
4556		- vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE);
4557		- v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
4558		- "stream[%d] vb done, index: %d, sequence %d\n", stream->id,
4559		- vb_done->vb2_buf.index, vb_done->sequence);
4560		-}
4561		-
4562	7464	void rkcif_irq_oneframe(struct rkcif_device *cif_dev)
4563	7465	{
4564	7466	/* TODO: xuhf-debug: add stream type */
..	..	@@ -4590,7 +7492,7 @@
4590	7492	}
4591	7493
4592	7494	if ((intstat & FRAME_END)) {
4593		- struct vb2_v4l2_buffer *vb_done = NULL;
	7495	+ struct rkcif_buffer *active_buf = NULL;
4594	7496
4595	7497	rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT,
4596	7498	FRAME_END_CLR);
..	..	@@ -4623,11 +7525,11 @@
4623	7525	if (frmid % 2 != 0) {
4624	7526	stream->frame_phase = CIF_CSI_FRAME0_READY;
4625	7527	if (stream->curr_buf)
4626		- vb_done = &stream->curr_buf->vb;
	7528	+ active_buf = stream->curr_buf;
4627	7529	} else {
4628	7530	stream->frame_phase = CIF_CSI_FRAME1_READY;
4629	7531	if (stream->next_buf)
4630		- vb_done = &stream->next_buf->vb;
	7532	+ active_buf = stream->next_buf;
4631	7533	}
4632	7534
4633	7535	/* In one-frame mode:
..	..	@@ -4640,46 +7542,28 @@
4640	7542	ret = rkcif_assign_new_buffer_oneframe(stream,
4641	7543	RKCIF_YUV_ADDR_STATE_UPDATE);
4642	7544
4643		- if (vb_done && (!ret)) {
4644		- vb_done->sequence = stream->frame_idx;
4645		- rkcif_vb_done_oneframe(stream, vb_done);
	7545	+ if (active_buf && (!ret)) {
	7546	+ active_buf->vb.sequence = stream->frame_idx - 1;
	7547	+ rkcif_vb_done_tasklet(stream, active_buf);
4646	7548	}
4647	7549
4648		- stream->frame_idx++;
4649		- cif_dev->irq_stats.all_frm_end_cnt++;
	7550	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
4650	7551	}
4651	7552	}
4652	7553
4653	7554	static int rkcif_csi_g_mipi_id(struct v4l2_device *v4l2_dev,
4654		- unsigned int intstat)
	7555	+ unsigned int intstat)
4655	7556	{
4656		- if (intstat & CSI_FRAME_END_ID0) {
4657		- if ((intstat & CSI_FRAME_END_ID0) ==
4658		- CSI_FRAME_END_ID0)
4659		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID0\n");
	7557	+ if (intstat & CSI_FRAME_END_ID0)
4660	7558	return RKCIF_STREAM_MIPI_ID0;
4661		- }
4662	7559
4663		- if (intstat & CSI_FRAME_END_ID1) {
4664		- if ((intstat & CSI_FRAME_END_ID1) ==
4665		- CSI_FRAME_END_ID1)
4666		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID1\n");
	7560	+ if (intstat & CSI_FRAME_END_ID1)
4667	7561	return RKCIF_STREAM_MIPI_ID1;
4668		- }
4669	7562
4670		- if (intstat & CSI_FRAME_END_ID2) {
4671		- if ((intstat & CSI_FRAME_END_ID2) ==
4672		- CSI_FRAME_END_ID2)
4673		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID2\n");
	7563	+ if (intstat & CSI_FRAME_END_ID2)
4674	7564	return RKCIF_STREAM_MIPI_ID2;
4675		- }
4676		-
4677		- if (intstat & CSI_FRAME_END_ID3) {
4678		- if ((intstat & CSI_FRAME_END_ID3) ==
4679		- CSI_FRAME_END_ID3)
4680		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID3\n");
	7565	+ if (intstat & CSI_FRAME_END_ID3)
4681	7566	return RKCIF_STREAM_MIPI_ID3;
4682		- }
4683	7567
4684	7568	return -EINVAL;
4685	7569	}
..	..	@@ -4688,38 +7572,42 @@
4688	7572	u32 *intstat, u32 frm_stat)
4689	7573	{
4690	7574	if (*intstat & DVP_FRAME_END_ID0) {
4691		- if ((frm_stat & DVP_CHANNEL0_FRM_READ) ==
4692		- DVP_CHANNEL0_FRM_READ)
4693		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID0\n");
4694		-
4695	7575	*intstat &= ~DVP_FRAME_END_ID0;
4696	7576	return RKCIF_STREAM_MIPI_ID0;
4697	7577	}
4698	7578
4699	7579	if (*intstat & DVP_FRAME_END_ID1) {
4700		- if ((frm_stat & DVP_CHANNEL1_FRM_READ) ==
4701		- DVP_CHANNEL1_FRM_READ)
4702		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID1\n");
4703		-
4704	7580	*intstat &= ~DVP_FRAME_END_ID1;
4705	7581	return RKCIF_STREAM_MIPI_ID1;
4706	7582	}
4707	7583
4708	7584	if (*intstat & DVP_FRAME_END_ID2) {
4709		- if ((frm_stat & DVP_CHANNEL2_FRM_READ) ==
4710		- DVP_CHANNEL2_FRM_READ)
4711		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID2\n");
4712	7585	*intstat &= ~DVP_FRAME_END_ID2;
4713	7586	return RKCIF_STREAM_MIPI_ID2;
4714	7587	}
4715	7588
4716	7589	if (*intstat & DVP_FRAME_END_ID3) {
4717		- if ((frm_stat & DVP_CHANNEL3_FRM_READ) ==
4718		- DVP_CHANNEL3_FRM_READ)
4719		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID3\n");
4720	7590	*intstat &= ~DVP_FRAME_END_ID3;
4721	7591	return RKCIF_STREAM_MIPI_ID3;
4722	7592	}
	7593	+
	7594	+ return -EINVAL;
	7595	+}
	7596	+
	7597	+static int rkcif_dvp_g_ch_id_by_fe(struct v4l2_device *v4l2_dev,
	7598	+ u32 intstat)
	7599	+{
	7600	+ if (intstat & DVP_ALL_END_ID0)
	7601	+ return RKCIF_STREAM_MIPI_ID0;
	7602	+
	7603	+ if (intstat & DVP_ALL_END_ID1)
	7604	+ return RKCIF_STREAM_MIPI_ID1;
	7605	+
	7606	+ if (intstat & DVP_ALL_END_ID2)
	7607	+ return RKCIF_STREAM_MIPI_ID2;
	7608	+
	7609	+ if (intstat & DVP_ALL_END_ID3)
	7610	+ return RKCIF_STREAM_MIPI_ID3;
4723	7611
4724	7612	return -EINVAL;
4725	7613	}
..	..	@@ -4730,7 +7618,6 @@
4730	7618	struct rkcif_device,
4731	7619	reset_watchdog_timer);
4732	7620	struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
4733		- struct rkcif_hw_timer *hw_timer = &dev->hw_dev->hw_timer;
4734	7621	bool is_triggered = false, is_assign_triggered = false, is_first_err = false;
4735	7622	unsigned long flags;
4736	7623	u64 cur_time, diff_time;
..	..	@@ -4741,7 +7628,7 @@
4741	7628	timer->csi2_err_cnt_odd != 0) {
4742	7629	timer->csi2_err_cnt_odd = 0;
4743	7630	timer->csi2_err_cnt_even = 0;
4744		- hw_timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
	7631	+ timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
4745	7632	timer->csi2_err_triggered_cnt++;
4746	7633	if (timer->csi2_err_triggered_cnt == 1) {
4747	7634	is_first_err = true;
..	..	@@ -4760,7 +7647,7 @@
4760	7647	cur_time = ktime_get_ns();
4761	7648	diff_time = cur_time - timer->csi2_first_err_timestamp;
4762	7649	diff_time = div_u64(diff_time, 1000000);
4763		- if (diff_time >= hw_timer->err_time_interval) {
	7650	+ if (diff_time >= timer->err_time_interval) {
4764	7651	is_triggered = true;
4765	7652	v4l2_info(&dev->v4l2_dev, "trigger reset for time out of csi err\n");
4766	7653	goto end_judge;
..	..	@@ -4780,19 +7667,10 @@
4780	7667	* when fs cnt is beyond 2, it indicates that frame end is not coming,
4781	7668	* or fs and fe had been not paired.
4782	7669	*/
4783		- if (hw_timer->monitor_mode != RKCIF_MONITOR_MODE_HOTPLUG &&
4784		- (stream->is_fs_fe_not_paired \|\|
4785		- stream->fs_cnt_in_single_frame > RKCIF_FS_DETECTED_NUM)) {
	7670	+ if (stream->is_fs_fe_not_paired \|\|
	7671	+ stream->fs_cnt_in_single_frame > RKCIF_FS_DETECTED_NUM) {
4786	7672	is_triggered = true;
4787	7673	v4l2_info(&dev->v4l2_dev, "reset for fs & fe not paired\n");
4788		- }
4789		- if (dev->irq_stats.csi_bwidth_lack_cnt) {
4790		- is_triggered = true;
4791		- dev->irq_stats.csi_bwidth_lack_cnt = 0;
4792		- }
4793		- if (dev->irq_stats.csi_overflow_cnt) {
4794		- is_triggered = true;
4795		- dev->irq_stats.csi_overflow_cnt = 0;
4796	7674	}
4797	7675	end_judge:
4798	7676	spin_unlock_irqrestore(&timer->csi2_err_lock, flags);
..	..	@@ -4800,7 +7678,30 @@
4800	7678	return is_triggered;
4801	7679	}
4802	7680
4803		-static s32 rkcif_get_sensor_vblank(struct rkcif_device *dev)
	7681	+static bool rkcif_is_triggered_monitoring(struct rkcif_device *dev)
	7682	+{
	7683	+ struct rkcif_timer *timer = &dev->reset_watchdog_timer;
	7684	+ struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
	7685	+ bool ret = false;
	7686	+
	7687	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
	7688	+ ret = false;
	7689	+
	7690	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE \|\|
	7691	+ timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
	7692	+ if (stream->frame_idx >= timer->triggered_frame_num)
	7693	+ ret = true;
	7694	+ }
	7695	+
	7696	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
	7697	+ timer->is_csi2_err_occurred = rkcif_is_csi2_err_trigger_reset(timer);
	7698	+ ret = timer->is_csi2_err_occurred;
	7699	+ }
	7700	+
	7701	+ return ret;
	7702	+}
	7703	+
	7704	+s32 rkcif_get_sensor_vblank(struct rkcif_device *dev)
4804	7705	{
4805	7706	struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
4806	7707	struct v4l2_subdev *sd = terminal_sensor->sd;
..	..	@@ -4817,7 +7718,7 @@
4817	7718	return 0;
4818	7719	}
4819	7720
4820		-static s32 rkcif_get_sensor_vblank_def(struct rkcif_device *dev)
	7721	+s32 rkcif_get_sensor_vblank_def(struct rkcif_device *dev)
4821	7722	{
4822	7723	struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
4823	7724	struct v4l2_subdev *sd = terminal_sensor->sd;
..	..	@@ -4843,7 +7744,7 @@
4843	7744	const struct cif_output_fmt *fmt;
4844	7745	u32 fourcc;
4845	7746
4846		- fmt = find_output_fmt(stream, stream->pixm.pixelformat);
	7747	+ fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
4847	7748	if (!fmt) {
4848	7749	v4l2_err(&dev->v4l2_dev, "can not find output format: 0x%x",
4849	7750	stream->pixm.pixelformat);
..	..	@@ -4859,13 +7760,14 @@
4859	7760	* writing of ddr, aliged with 256
4860	7761	*/
4861	7762	if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
4862		- fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888) {
	7763	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
	7764	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
4863	7765	crop_vwidth = ALIGN(raw_width fmt->raw_bpp / 8, 256);
4864	7766	} else {
4865	7767	crop_vwidth = ALIGN(raw_width fmt->bpp[0] / 8, 8);
4866	7768	}
4867	7769
4868		- if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
	7770	+ if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888 \|\| channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
4869	7771	crop_width = raw_width fmt->bpp[0] / 8;
4870	7772	/*
4871	7773	* rk cif don't support output yuyv fmt data
..	..	@@ -4893,12 +7795,15 @@
4893	7795	return;
4894	7796
4895	7797	mbus = &cif_dev->active_sensor->mbus;
4896		- if (mbus->type == V4L2_MBUS_CSI2 \|\|
	7798	+ if (mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	7799	+ mbus->type == V4L2_MBUS_CSI2_CPHY \|\|
4897	7800	mbus->type == V4L2_MBUS_CCP2) {
4898	7801	struct csi_channel_info *channel = &cif_dev->channels[stream->id];
4899	7802
4900	7803	if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
4901	7804	crop_x = 3 * stream->crop[CROP_SRC_ACT].left;
	7805	+ else if (channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
	7806	+ crop_x = 2 * stream->crop[CROP_SRC_ACT].left;
4902	7807	else
4903	7808	crop_x = stream->crop[CROP_SRC_ACT].left;
4904	7809
..	..	@@ -4940,15 +7845,8 @@
4940	7845	crop_y << CIF_CROP_Y_SHIFT \| crop_x);
4941	7846
4942	7847	if (stream->cif_fmt_in->fmt_type == CIF_FMT_TYPE_RAW) {
4943		- fmt = find_output_fmt(stream, stream->pixm.pixelformat);
4944		- if (fmt->fourcc == V4L2_PIX_FMT_GREY \|\|
4945		- fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
4946		- fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
4947		- fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
4948		- fmt->fourcc == V4L2_PIX_FMT_SBGGR8)
4949		- crop_vwidth = ALIGN(raw_width * fmt->raw_bpp / 8, 256);
4950		- else
4951		- crop_vwidth = raw_width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
	7848	+ fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
	7849	+ crop_vwidth = raw_width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
4952	7850	}
4953	7851	rkcif_write_register(cif_dev, CIF_REG_DVP_VIR_LINE_WIDTH, crop_vwidth);
4954	7852
..	..	@@ -4959,41 +7857,94 @@
4959	7857	stream->crop_dyn_en = false;
4960	7858	}
4961	7859
4962		-void rkcif_monitor_reset_event(struct rkcif_hw *hw)
	7860	+static void rkcif_monitor_reset_event(struct rkcif_device *dev)
4963	7861	{
4964		- struct rkcif_hw_timer *hw_timer = &hw->hw_timer;
4965		- struct rkcif_timer *timer = NULL;
4966		- struct rkcif_device *cif_dev = NULL;
4967	7862	struct rkcif_stream *stream = NULL;
4968		- unsigned long flags;
4969		- int i = 0, j = 0;
	7863	+ struct rkcif_timer *timer = &dev->reset_watchdog_timer;
	7864	+ unsigned int cycle = 0;
	7865	+ u64 fps, timestamp0, timestamp1;
	7866	+ unsigned long flags, fps_flags;
	7867	+ int i = 0;
4970	7868
4971		- if (hw_timer->is_running)
	7869	+ if (timer->is_running)
4972	7870	return;
4973	7871
4974		- if (hw_timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
	7872	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
4975	7873	return;
4976	7874
4977		- spin_lock_irqsave(&hw_timer->timer_lock, flags);
4978		- hw_timer->is_running = true;
4979		- for (j = 0; i < hw->dev_num; j++) {
4980		- cif_dev = hw->cif_dev[i];
4981		- timer = &cif_dev->reset_watchdog_timer;
4982		- for (i = 0; i < cif_dev->num_channels; i++) {
4983		- stream = &cif_dev->stream[i];
4984		- if (stream->state == RKCIF_STATE_STREAMING)
4985		- timer->last_buf_wakeup_cnt[i] = stream->frame_idx;
4986		- }
	7875	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	7876	+ stream = &dev->stream[i];
	7877	+ if (stream->state == RKCIF_STATE_STREAMING)
	7878	+ break;
4987	7879	}
4988		- hw_timer->cycle_jif = msecs_to_jiffies(hw_timer->monitor_cycle);
4989		- hw_timer->timer.expires = jiffies + hw_timer->cycle_jif;
4990		- mod_timer(&hw_timer->timer, hw_timer->timer.expires);
4991	7880
4992		- spin_unlock_irqrestore(&hw_timer->timer_lock, flags);
	7881	+ if (i >= RKCIF_MAX_STREAM_MIPI)
	7882	+ return;
4993	7883
4994		- v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
4995		- "start monitor timer, monitor cycle %d\n",
4996		- hw_timer->monitor_cycle);
	7884	+ timer->is_triggered = rkcif_is_triggered_monitoring(dev);
	7885	+
	7886	+ if (timer->is_triggered) {
	7887	+ struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
	7888	+ enum rkcif_monitor_mode mode;
	7889	+ s32 vblank = 0;
	7890	+ u32 vts = 0;
	7891	+ u64 numerator = 0;
	7892	+ u64 denominator = 0;
	7893	+
	7894	+ if (stream->frame_idx > 2) {
	7895	+ spin_lock_irqsave(&stream->fps_lock, fps_flags);
	7896	+ timestamp0 = stream->fps_stats.frm0_timestamp;
	7897	+ timestamp1 = stream->fps_stats.frm1_timestamp;
	7898	+ spin_unlock_irqrestore(&stream->fps_lock, fps_flags);
	7899	+
	7900	+ fps = timestamp0 > timestamp1 ?
	7901	+ timestamp0 - timestamp1 : timestamp1 - timestamp0;
	7902	+ fps = div_u64(fps, 1000);
	7903	+ } else {
	7904	+ numerator = dev->terminal_sensor.fi.interval.numerator;
	7905	+ denominator = dev->terminal_sensor.fi.interval.denominator;
	7906	+ fps = div_u64(1000000 * numerator, denominator);
	7907	+ }
	7908	+ spin_lock_irqsave(&timer->timer_lock, flags);
	7909	+
	7910	+ timer->frame_end_cycle_us = fps;
	7911	+
	7912	+ vblank = rkcif_get_sensor_vblank(dev);
	7913	+ timer->raw_height = raw_rect->height;
	7914	+ vts = timer->raw_height + vblank;
	7915	+ timer->vts = vts;
	7916	+
	7917	+ timer->line_end_cycle = div_u64(timer->frame_end_cycle_us, timer->vts);
	7918	+ fps = div_u64(timer->frame_end_cycle_us, 1000);
	7919	+ cycle = fps * timer->frm_num_of_monitor_cycle;
	7920	+ timer->cycle = msecs_to_jiffies(cycle);
	7921	+
	7922	+ timer->run_cnt = 0;
	7923	+ timer->is_running = true;
	7924	+ timer->is_buf_stop_update = false;
	7925	+ for (i = 0; i < dev->num_channels; i++) {
	7926	+ stream = &dev->stream[i];
	7927	+ if (stream->state == RKCIF_STATE_STREAMING)
	7928	+ timer->last_buf_wakeup_cnt[i] = stream->buf_wake_up_cnt;
	7929	+ }
	7930	+ /* in trigger mode, monitoring count is fps */
	7931	+ mode = timer->monitor_mode;
	7932	+ if (mode == RKCIF_MONITOR_MODE_CONTINUE \|\|
	7933	+ mode == RKCIF_MONITOR_MODE_HOTPLUG)
	7934	+ timer->max_run_cnt = 0xffffffff - CIF_TIMEOUT_FRAME_NUM;
	7935	+ else
	7936	+ timer->max_run_cnt = div_u64(1000, fps) * 1;
	7937	+
	7938	+ timer->timer.expires = jiffies + timer->cycle;
	7939	+ mod_timer(&timer->timer, timer->timer.expires);
	7940	+
	7941	+ spin_unlock_irqrestore(&timer->timer_lock, flags);
	7942	+
	7943	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	7944	+ "%s:mode:%d, raw height:%d,vblank:%d, cycle:%ld, fps:%llu\n",
	7945	+ __func__, timer->monitor_mode, raw_rect->height,
	7946	+ vblank, timer->cycle, div_u64(1000, fps));
	7947	+ }
4997	7948	}
4998	7949
4999	7950	static void rkcif_rdbk_frame_end(struct rkcif_stream *stream)
..	..	@@ -5003,13 +7954,15 @@
5003	7954	u32 denominator, numerator;
5004	7955	u64 l_ts, m_ts, s_ts, time = 30000000LL;
5005	7956	int ret, fps = -1;
	7957	+ int i = 0;
	7958	+ unsigned long flags;
5006	7959
5007		- if (dev->hdr.mode == HDR_X2) {
	7960	+ if (dev->hdr.hdr_mode == HDR_X2) {
5008	7961	if (stream->id != RKCIF_STREAM_MIPI_ID1 \|\|
5009	7962	dev->stream[RKCIF_STREAM_MIPI_ID0].state != RKCIF_STATE_STREAMING \|\|
5010	7963	dev->stream[RKCIF_STREAM_MIPI_ID1].state != RKCIF_STATE_STREAMING)
5011	7964	return;
5012		- } else if (dev->hdr.mode == HDR_X3) {
	7965	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
5013	7966	if (stream->id != RKCIF_STREAM_MIPI_ID2 \|\|
5014	7967	dev->stream[RKCIF_STREAM_MIPI_ID0].state != RKCIF_STATE_STREAMING \|\|
5015	7968	dev->stream[RKCIF_STREAM_MIPI_ID1].state != RKCIF_STATE_STREAMING \|\|
..	..	@@ -5022,13 +7975,13 @@
5022	7975	if (denominator && numerator)
5023	7976	time = numerator * 1000 / denominator * 1000 * 1000;
5024	7977
5025		- if (dev->hdr.mode == HDR_X3) {
	7978	+ if (dev->hdr.hdr_mode == HDR_X3) {
5026	7979	if (dev->rdbk_buf[RDBK_L] &&
5027	7980	dev->rdbk_buf[RDBK_M] &&
5028	7981	dev->rdbk_buf[RDBK_S]) {
5029		- l_ts = dev->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
5030		- m_ts = dev->rdbk_buf[RDBK_M]->vb.vb2_buf.timestamp;
5031		- s_ts = dev->rdbk_buf[RDBK_S]->vb.vb2_buf.timestamp;
	7982	+ l_ts = dev->rdbk_buf[RDBK_L]->fe_timestamp;
	7983	+ m_ts = dev->rdbk_buf[RDBK_M]->fe_timestamp;
	7984	+ s_ts = dev->rdbk_buf[RDBK_S]->fe_timestamp;
5032	7985
5033	7986	if (m_ts < l_ts \|\| s_ts < m_ts) {
5034	7987	v4l2_err(&dev->v4l2_dev,
..	..	@@ -5058,14 +8011,25 @@
5058	8011	goto RDBK_FRM_UNMATCH;
5059	8012	}
5060	8013	}
5061		- dev->rdbk_buf[RDBK_L]->vb.sequence = dev->rdbk_buf[RDBK_S]->vb.sequence;
5062		- dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_S]->vb.sequence;
5063		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID0],
5064		- &dev->rdbk_buf[RDBK_L]->vb);
5065		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID1],
5066		- &dev->rdbk_buf[RDBK_M]->vb);
5067		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID2],
5068		- &dev->rdbk_buf[RDBK_S]->vb);
	8014	+ dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
	8015	+ dev->rdbk_buf[RDBK_S]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
	8016	+ if (dev->is_support_tools &&
	8017	+ dev->stream[RKCIF_STREAM_MIPI_ID0].tools_vdev->state == RKCIF_STATE_STREAMING &&
	8018	+ dev->stream[RKCIF_STREAM_MIPI_ID1].tools_vdev->state == RKCIF_STATE_STREAMING &&
	8019	+ dev->stream[RKCIF_STREAM_MIPI_ID2].tools_vdev->state == RKCIF_STATE_STREAMING) {
	8020	+ for (i = 0; i < 3; i++) {
	8021	+ spin_lock_irqsave(&dev->stream[i].tools_vdev->vbq_lock, flags);
	8022	+ list_add_tail(&dev->rdbk_buf[i]->queue,
	8023	+ &dev->stream[i].tools_vdev->buf_done_head);
	8024	+ if (!work_busy(&dev->stream[i].tools_vdev->work))
	8025	+ schedule_work(&dev->stream[i].tools_vdev->work);
	8026	+ spin_unlock_irqrestore(&dev->stream[i].tools_vdev->vbq_lock, flags);
	8027	+ }
	8028	+ } else {
	8029	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID0], dev->rdbk_buf[RDBK_L]);
	8030	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID1], dev->rdbk_buf[RDBK_M]);
	8031	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID2], dev->rdbk_buf[RDBK_S]);
	8032	+ }
5069	8033	} else {
5070	8034	if (!dev->rdbk_buf[RDBK_L])
5071	8035	v4l2_err(&dev->v4l2_dev, "lost long frames\n");
..	..	@@ -5075,10 +8039,10 @@
5075	8039	v4l2_err(&dev->v4l2_dev, "lost short frames\n");
5076	8040	goto RDBK_FRM_UNMATCH;
5077	8041	}
5078		- } else if (dev->hdr.mode == HDR_X2) {
	8042	+ } else if (dev->hdr.hdr_mode == HDR_X2) {
5079	8043	if (dev->rdbk_buf[RDBK_L] && dev->rdbk_buf[RDBK_M]) {
5080		- l_ts = dev->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
5081		- s_ts = dev->rdbk_buf[RDBK_M]->vb.vb2_buf.timestamp;
	8044	+ l_ts = dev->rdbk_buf[RDBK_L]->fe_timestamp;
	8045	+ s_ts = dev->rdbk_buf[RDBK_M]->fe_timestamp;
5082	8046
5083	8047	if (s_ts < l_ts) {
5084	8048	v4l2_err(&dev->v4l2_dev,
..	..	@@ -5107,11 +8071,22 @@
5107	8071	goto RDBK_FRM_UNMATCH;
5108	8072	}
5109	8073	}
5110		- dev->rdbk_buf[RDBK_L]->vb.sequence = dev->rdbk_buf[RDBK_M]->vb.sequence;
5111		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID0],
5112		- &dev->rdbk_buf[RDBK_L]->vb);
5113		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID1],
5114		- &dev->rdbk_buf[RDBK_M]->vb);
	8074	+ dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
	8075	+ if (dev->is_support_tools &&
	8076	+ dev->stream[RKCIF_STREAM_MIPI_ID0].tools_vdev->state == RKCIF_STATE_STREAMING &&
	8077	+ dev->stream[RKCIF_STREAM_MIPI_ID1].tools_vdev->state == RKCIF_STATE_STREAMING) {
	8078	+ for (i = 0; i < 2; i++) {
	8079	+ spin_lock_irqsave(&dev->stream[i].tools_vdev->vbq_lock, flags);
	8080	+ list_add_tail(&dev->rdbk_buf[i]->queue,
	8081	+ &dev->stream[i].tools_vdev->buf_done_head);
	8082	+ if (!work_busy(&dev->stream[i].tools_vdev->work))
	8083	+ schedule_work(&dev->stream[i].tools_vdev->work);
	8084	+ spin_unlock_irqrestore(&dev->stream[i].tools_vdev->vbq_lock, flags);
	8085	+ }
	8086	+ } else {
	8087	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID0], dev->rdbk_buf[RDBK_L]);
	8088	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID1], dev->rdbk_buf[RDBK_M]);
	8089	+ }
5115	8090	} else {
5116	8091	if (!dev->rdbk_buf[RDBK_L])
5117	8092	v4l2_err(&dev->v4l2_dev, "lost long frames\n");
..	..	@@ -5119,8 +8094,6 @@
5119	8094	v4l2_err(&dev->v4l2_dev, "lost short frames\n");
5120	8095	goto RDBK_FRM_UNMATCH;
5121	8096	}
5122		- } else {
5123		- rkcif_vb_done_oneframe(stream, &dev->rdbk_buf[RDBK_S]->vb);
5124	8097	}
5125	8098
5126	8099	dev->rdbk_buf[RDBK_L] = NULL;
..	..	@@ -5147,10 +8120,26 @@
5147	8120	dev->rdbk_buf[RDBK_S] = NULL;
5148	8121	}
5149	8122
	8123	+static void rkcif_buf_done_with_tools(struct rkcif_stream *stream,
	8124	+ struct rkcif_buffer *active_buf)
	8125	+{
	8126	+ unsigned long flags;
	8127	+
	8128	+ spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
	8129	+ if (stream->tools_vdev->state == RKCIF_STATE_STREAMING) {
	8130	+ list_add_tail(&active_buf->queue, &stream->tools_vdev->buf_done_head);
	8131	+ if (!work_busy(&stream->tools_vdev->work))
	8132	+ schedule_work(&stream->tools_vdev->work);
	8133	+ } else {
	8134	+ rkcif_vb_done_tasklet(stream, active_buf);
	8135	+ }
	8136	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
	8137	+}
	8138	+
5150	8139	static void rkcif_buf_done_prepare(struct rkcif_stream *stream,
5151		- struct rkcif_buffer *active_buf,
5152		- int mipi_id,
5153		- u32 mode)
	8140	+ struct rkcif_buffer *active_buf,
	8141	+ int mipi_id,
	8142	+ u32 mode)
5154	8143	{
5155	8144	unsigned long flags;
5156	8145	struct vb2_v4l2_buffer *vb_done = NULL;
..	..	@@ -5158,8 +8147,9 @@
5158	8147
5159	8148	if (active_buf) {
5160	8149	vb_done = &active_buf->vb;
5161		- vb_done->vb2_buf.timestamp = ktime_get_ns();
5162		- vb_done->sequence = stream->frame_idx;
	8150	+ vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
	8151	+ vb_done->sequence = stream->frame_idx - 1;
	8152	+ active_buf->fe_timestamp = ktime_get_ns();
5163	8153	if (stream->is_line_wake_up) {
5164	8154	spin_lock_irqsave(&stream->fps_lock, flags);
5165	8155	if (mode)
..	..	@@ -5173,13 +8163,22 @@
5173	8163	vb_done->sequence /= 2;
5174	8164	}
5175	8165
5176		- if (cif_dev->hdr.mode == NO_HDR) {
	8166	+ if (cif_dev->hdr.hdr_mode == NO_HDR \|\| cif_dev->hdr.hdr_mode == HDR_COMPR) {
5177	8167	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
5178		- if (stream->frame_phase == CIF_CSI_FRAME1_READY && active_buf)
5179		- rkcif_vb_done_oneframe(stream, vb_done);
	8168	+ if (stream->frame_phase == CIF_CSI_FRAME1_READY && active_buf) {
	8169	+
	8170	+ if (cif_dev->is_support_tools && stream->tools_vdev)
	8171	+ rkcif_buf_done_with_tools(stream, active_buf);
	8172	+ else
	8173	+ rkcif_vb_done_tasklet(stream, active_buf);
	8174	+ }
5180	8175	} else {
5181		- if (active_buf)
5182		- rkcif_vb_done_oneframe(stream, vb_done);
	8176	+ if (active_buf) {
	8177	+ if (cif_dev->is_support_tools && stream->tools_vdev)
	8178	+ rkcif_buf_done_with_tools(stream, active_buf);
	8179	+ else
	8180	+ rkcif_vb_done_tasklet(stream, active_buf);
	8181	+ }
5183	8182	}
5184	8183	} else {
5185	8184	if (cif_dev->is_start_hdr) {
..	..	@@ -5188,11 +8187,12 @@
5188	8187	if (cif_dev->rdbk_buf[RDBK_L]) {
5189	8188	v4l2_err(&cif_dev->v4l2_dev,
5190	8189	"multiple long data in %s frame,frm_idx:%d,state:0x%x\n",
5191		- cif_dev->hdr.mode == HDR_X2 ? "hdr_x2" : "hdr_x3",
	8190	+ cif_dev->hdr.hdr_mode == HDR_X2 ? "hdr_x2" : "hdr_x3",
5192	8191	stream->frame_idx,
5193	8192	cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state);
5194	8193	cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
5195	8194	rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf);
	8195	+ cif_dev->rdbk_buf[RDBK_L] = NULL;
5196	8196	}
5197	8197	if (active_buf)
5198	8198	cif_dev->rdbk_buf[RDBK_L] = active_buf;
..	..	@@ -5200,29 +8200,31 @@
5200	8200	if (cif_dev->rdbk_buf[RDBK_M]) {
5201	8201	v4l2_err(&cif_dev->v4l2_dev,
5202	8202	"multiple %s frame,frm_idx:%d,state:0x%x\n",
5203		- cif_dev->hdr.mode == HDR_X2 ? "short data in hdr_x2" : "medium data in hdr_x3",
	8203	+ cif_dev->hdr.hdr_mode == HDR_X2 ? "short data in hdr_x2" : "medium data in hdr_x3",
5204	8204	stream->frame_idx,
5205	8205	cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state);
5206	8206	cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
5207	8207	rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf);
	8208	+ cif_dev->rdbk_buf[RDBK_M] = NULL;
5208	8209	}
5209	8210	if (active_buf)
5210	8211	cif_dev->rdbk_buf[RDBK_M] = active_buf;
5211		- if (cif_dev->hdr.mode == HDR_X2)
	8212	+ if (cif_dev->hdr.hdr_mode == HDR_X2)
5212	8213	rkcif_rdbk_frame_end(stream);
5213	8214	} else if (mipi_id == RKCIF_STREAM_MIPI_ID2) {
5214	8215	if (cif_dev->rdbk_buf[RDBK_S]) {
5215	8216	v4l2_err(&cif_dev->v4l2_dev,
5216	8217	"multiple %s frame, frm_idx:%d,state:0x%x\n",
5217		- cif_dev->hdr.mode == HDR_X2 ? "err short data in hdr_x3" : "short data in hdr_x3",
	8218	+ cif_dev->hdr.hdr_mode == HDR_X2 ? "err short data in hdr_x3" : "short data in hdr_x3",
5218	8219	stream->frame_idx,
5219	8220	cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state);
5220	8221	cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
5221	8222	rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf);
	8223	+ cif_dev->rdbk_buf[RDBK_S] = NULL;
5222	8224	}
5223	8225	if (active_buf)
5224	8226	cif_dev->rdbk_buf[RDBK_S] = active_buf;
5225		- if (cif_dev->hdr.mode == HDR_X3)
	8227	+ if (cif_dev->hdr.hdr_mode == HDR_X3)
5226	8228	rkcif_rdbk_frame_end(stream);
5227	8229	}
5228	8230	spin_unlock_irqrestore(&cif_dev->hdr_lock, flags);
..	..	@@ -5265,12 +8267,125 @@
5265	8267	}
5266	8268	ret = rkcif_get_new_buffer_wake_up_mode(stream);
5267	8269	if (ret)
5268		- goto end_wake_up;
5269		-
	8270	+ return;
5270	8271	rkcif_buf_done_prepare(stream, active_buf, mipi_id, mode);
5271		-end_wake_up:
5272		- stream->frame_idx++;
	8272	+}
5273	8273
	8274	+static void rkcif_store_last_buf_for_online(struct rkcif_stream *stream,
	8275	+ struct rkcif_rx_buffer *buf)
	8276	+{
	8277	+ struct rkcif_device *dev = stream->cifdev;
	8278	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	8279	+ u32 frm0_addr_y, frm1_addr_y;
	8280	+
	8281	+ INIT_LIST_HEAD(&stream->rx_buf_head);
	8282	+ stream->curr_buf_toisp = buf;
	8283	+ stream->next_buf_toisp = buf;
	8284	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	8285	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	8286	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	8287	+ frm0_addr_y = get_reg_index_of_frm0_y_addr(stream->id);
	8288	+ frm1_addr_y = get_reg_index_of_frm1_y_addr(stream->id);
	8289	+ } else {
	8290	+ frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(stream->id);
	8291	+ frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(stream->id);
	8292	+ }
	8293	+ rkcif_write_register(dev, frm0_addr_y,
	8294	+ buf->dummy.dma_addr);
	8295	+ rkcif_write_register(dev, frm1_addr_y,
	8296	+ buf->dummy.dma_addr);
	8297	+}
	8298	+
	8299	+static void rkcif_release_unnecessary_buf_for_online(struct rkcif_stream *stream,
	8300	+ struct rkcif_rx_buffer *buf)
	8301	+{
	8302	+ struct rkcif_device *dev = stream->cifdev;
	8303	+ struct sditf_priv *priv = dev->sditf[0];
	8304	+ struct rkcif_rx_buffer *rx_buf = NULL;
	8305	+ unsigned long flags;
	8306	+ int i = 0;
	8307	+
	8308	+ spin_lock_irqsave(&priv->cif_dev->buffree_lock, flags);
	8309	+ for (i = 0; i < priv->buf_num; i++) {
	8310	+ rx_buf = &stream->rx_buf[i];
	8311	+ if (rx_buf && (!rx_buf->dummy.is_free) && rx_buf != buf)
	8312	+ list_add_tail(&rx_buf->list_free, &priv->buf_free_list);
	8313	+ }
	8314	+ spin_unlock_irqrestore(&priv->cif_dev->buffree_lock, flags);
	8315	+ schedule_work(&priv->buffree_work.work);
	8316	+}
	8317	+
	8318	+static void rkcif_line_wake_up_rdbk(struct rkcif_stream *stream, int mipi_id)
	8319	+{
	8320	+ u32 mode;
	8321	+ struct rkcif_rx_buffer *active_buf = NULL;
	8322	+ struct sditf_priv *priv = NULL;
	8323	+ unsigned long flags;
	8324	+ int ret = 0;
	8325	+
	8326	+ mode = stream->line_int_cnt % 2;
	8327	+ if (mode) {
	8328	+ if (stream->curr_buf_toisp)
	8329	+ active_buf = stream->curr_buf_toisp;
	8330	+ stream->frame_phase = CIF_CSI_FRAME0_READY;
	8331	+ } else {
	8332	+ if (stream->next_buf_toisp)
	8333	+ active_buf = stream->next_buf_toisp;
	8334	+ stream->frame_phase = CIF_CSI_FRAME1_READY;
	8335	+ }
	8336	+
	8337	+ if (!active_buf) {
	8338	+ v4l2_err(&stream->cifdev->v4l2_dev,
	8339	+ "err buffer state in %s\n",
	8340	+ __func__);
	8341	+ return;
	8342	+ }
	8343	+
	8344	+ if (stream->stopping) {
	8345	+ stream->is_can_stop = true;
	8346	+ return;
	8347	+ }
	8348	+ ret = rkcif_get_new_buffer_wake_up_mode_rdbk(stream);
	8349	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	8350	+ "%d frame_idx %d, last_rx_buf_idx %d cur dma buf %x\n",
	8351	+ __LINE__, stream->frame_idx, stream->last_rx_buf_idx,
	8352	+ (u32)active_buf->dummy.dma_addr);
	8353	+ if (!ret) {
	8354	+ priv = stream->cifdev->sditf[0];
	8355	+ if (stream->cur_stream_mode & RKCIF_STREAM_MODE_TOISP_RDBK) {
	8356	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	8357	+ if (stream->cifdev->is_thunderboot &&
	8358	+ (stream->frame_idx - 1) == stream->last_rx_buf_idx &&
	8359	+ stream->cifdev->is_rdbk_to_online) {
	8360	+ stream->cur_stream_mode &= ~RKCIF_STREAM_MODE_TOISP_RDBK;
	8361	+ stream->cur_stream_mode \|= RKCIF_STREAM_MODE_TOISP;
	8362	+ stream->cifdev->wait_line = 0;
	8363	+ stream->is_line_wake_up = false;
	8364	+ if (stream->cifdev->hdr.hdr_mode == NO_HDR \|\|
	8365	+ (priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	8366	+ (priv->hdr_cfg.hdr_mode == HDR_X3 && stream->id == 2)) {
	8367	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	8368	+ rkcif_stop_dma_capture(stream);
	8369	+ }
	8370	+ active_buf->dbufs.is_switch = true;
	8371	+ if ((priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id != 1) \|\|
	8372	+ (priv->hdr_cfg.hdr_mode == HDR_X3 && stream->id != 2)) {
	8373	+ rkcif_store_last_buf_for_online(stream, active_buf);
	8374	+ stream->is_change_toisp = true;
	8375	+ }
	8376	+ }
	8377	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	8378	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	8379	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	8380	+ active_buf->fe_timestamp = ktime_get_ns();
	8381	+ stream->last_frame_idx = stream->frame_idx;
	8382	+ if (stream->cifdev->hdr.hdr_mode == NO_HDR)
	8383	+ rkcif_s_rx_buffer(stream->cifdev, &active_buf->dbufs);
	8384	+ else
	8385	+ rkcif_rdbk_frame_end_toisp(stream, active_buf);
	8386	+ stream->buf_num_toisp--;
	8387	+ }
	8388	+ }
5274	8389	}
5275	8390
5276	8391	static void rkcif_deal_readout_time(struct rkcif_stream *stream)
..	..	@@ -5281,17 +8396,24 @@
5281	8396
5282	8397	spin_lock_irqsave(&stream->fps_lock, flags);
5283	8398	stream->readout.fe_timestamp = ktime_get_ns();
	8399	+
	8400	+ if (cif_dev->inf_id == RKCIF_DVP) {
	8401	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	8402	+ return;
	8403	+ }
	8404	+
5284	8405	if (stream->id == RKCIF_STREAM_MIPI_ID0)
5285	8406	detect_stream->readout.readout_time = stream->readout.fe_timestamp - stream->readout.fs_timestamp;
5286	8407
5287		- if ((cif_dev->hdr.mode == NO_HDR) && (stream->id == RKCIF_STREAM_MIPI_ID0)) {
	8408	+ if ((cif_dev->hdr.hdr_mode == NO_HDR \|\| cif_dev->hdr.hdr_mode == HDR_COMPR) &&
	8409	+ (stream->id == RKCIF_STREAM_MIPI_ID0)) {
5288	8410	detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
5289	8411
5290		- } else if ((cif_dev->hdr.mode == HDR_X2) && (stream->id == RKCIF_STREAM_MIPI_ID1)) {
	8412	+ } else if ((cif_dev->hdr.hdr_mode == HDR_X2) && (stream->id == RKCIF_STREAM_MIPI_ID1)) {
5291	8413	detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
5292	8414	detect_stream->readout.total_time = stream->readout.fe_timestamp - detect_stream->readout.fe_timestamp;
5293	8415	detect_stream->readout.total_time += detect_stream->readout.readout_time;
5294		- } else if ((cif_dev->hdr.mode == HDR_X3) && (stream->id == RKCIF_STREAM_MIPI_ID2)) {
	8416	+ } else if ((cif_dev->hdr.hdr_mode == HDR_X3) && (stream->id == RKCIF_STREAM_MIPI_ID2)) {
5295	8417	detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
5296	8418	detect_stream->readout.total_time = stream->readout.fe_timestamp - detect_stream->readout.fe_timestamp;
5297	8419	detect_stream->readout.total_time += detect_stream->readout.readout_time;
..	..	@@ -5310,11 +8432,8 @@
5310	8432	int ret = 0;
5311	8433
5312	8434	if (stream->frame_phase == (CIF_CSI_FRAME0_READY \| CIF_CSI_FRAME1_READY)) {
5313		-
5314		- v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
5315		- stream->id, stream->frame_idx);
5316		-
5317		- stream->frame_idx++;
	8435	+ cif_dev->err_state \|= (RKCIF_ERR_ID0_TRIG_SIMULT << stream->id);
	8436	+ cif_dev->irq_stats.trig_simult_cnt[stream->id]++;
5318	8437	return;
5319	8438	}
5320	8439	if (!stream->is_line_wake_up) {
..	..	@@ -5332,99 +8451,176 @@
5332	8451	spin_unlock_irqrestore(&stream->fps_lock, flags);
5333	8452	}
5334	8453
5335		- if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
5336		- rkcif_deal_readout_time(stream);
5337		-
5338		- if (cif_dev->chip_id == CHIP_RV1126_CIF \|\|
5339		- cif_dev->chip_id == CHIP_RV1126_CIF_LITE \|\|
5340		- cif_dev->chip_id == CHIP_RK3568_CIF)
5341		- rkcif_luma_isr(&cif_dev->luma_vdev, mipi_id, stream->frame_idx);
	8454	+ rkcif_deal_readout_time(stream);
5342	8455
5343	8456	if (!stream->is_line_wake_up) {
5344	8457	ret = rkcif_assign_new_buffer_pingpong(stream,
5345	8458	RKCIF_YUV_ADDR_STATE_UPDATE,
5346	8459	mipi_id);
5347		- if (ret)
5348		- goto end;
	8460	+ if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
	8461	+ return;
5349	8462	} else {
5350	8463	ret = rkcif_update_new_buffer_wake_up_mode(stream);
5351		- if (ret)
	8464	+ if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
5352	8465	return;
5353	8466	}
5354		- if (!stream->is_line_wake_up)
	8467	+ if (!stream->is_line_wake_up && stream->dma_en & RKCIF_DMAEN_BY_VICAP)
5355	8468	rkcif_buf_done_prepare(stream, active_buf, mipi_id, 0);
5356	8469
5357		-end:
5358		- if (!stream->is_line_wake_up)
5359		- stream->frame_idx++;
	8470	+ if (cif_dev->chip_id == CHIP_RV1126_CIF \|\|
	8471	+ cif_dev->chip_id == CHIP_RV1126_CIF_LITE \|\|
	8472	+ cif_dev->chip_id == CHIP_RK3568_CIF)
	8473	+ rkcif_luma_isr(&cif_dev->luma_vdev, mipi_id, cif_dev->stream[0].frame_idx - 1);
5360	8474	}
5361	8475
5362		-u32 rkcif_get_sof(struct rkcif_device *cif_dev)
	8476	+static void rkcif_update_stream_toisp(struct rkcif_device *cif_dev,
	8477	+ struct rkcif_stream *stream,
	8478	+ int mipi_id)
	8479	+{
	8480	+ if (stream->frame_phase == (CIF_CSI_FRAME0_READY \| CIF_CSI_FRAME1_READY)) {
	8481	+
	8482	+ v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
	8483	+ stream->id, stream->frame_idx);
	8484	+ return;
	8485	+ }
	8486	+
	8487	+ spin_lock(&stream->fps_lock);
	8488	+ if (stream->frame_phase & CIF_CSI_FRAME0_READY)
	8489	+ stream->fps_stats.frm0_timestamp = ktime_get_ns();
	8490	+ else if (stream->frame_phase & CIF_CSI_FRAME1_READY)
	8491	+ stream->fps_stats.frm1_timestamp = ktime_get_ns();
	8492	+ spin_unlock(&stream->fps_lock);
	8493	+
	8494	+ if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
	8495	+ rkcif_deal_readout_time(stream);
	8496	+
	8497	+ if (!stream->is_line_wake_up)
	8498	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	8499	+ RKCIF_YUV_ADDR_STATE_UPDATE,
	8500	+ mipi_id);
	8501	+}
	8502	+
	8503	+static void rkcif_update_stream_rockit(struct rkcif_device *cif_dev,
	8504	+ struct rkcif_stream *stream,
	8505	+ int mipi_id)
	8506	+{
	8507	+ struct rkcif_buffer *active_buf = NULL;
	8508	+ unsigned long flags;
	8509	+ int ret = 0;
	8510	+
	8511	+ if (stream->frame_phase == (CIF_CSI_FRAME0_READY \| CIF_CSI_FRAME1_READY)) {
	8512	+
	8513	+ v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
	8514	+ stream->id, stream->frame_idx);
	8515	+ return;
	8516	+ }
	8517	+ if (!stream->is_line_wake_up) {
	8518	+
	8519	+ spin_lock_irqsave(&stream->fps_lock, flags);
	8520	+ if (stream->frame_phase & CIF_CSI_FRAME0_READY) {
	8521	+ if (stream->curr_buf_rockit)
	8522	+ active_buf = stream->curr_buf_rockit;
	8523	+ stream->fps_stats.frm0_timestamp = ktime_get_ns();
	8524	+ } else if (stream->frame_phase & CIF_CSI_FRAME1_READY) {
	8525	+ if (stream->next_buf_rockit)
	8526	+ active_buf = stream->next_buf_rockit;
	8527	+ stream->fps_stats.frm1_timestamp = ktime_get_ns();
	8528	+ }
	8529	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	8530	+ }
	8531	+
	8532	+ if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
	8533	+ rkcif_deal_readout_time(stream);
	8534	+
	8535	+ ret = rkcif_assign_new_buffer_pingpong_rockit(stream,
	8536	+ RKCIF_YUV_ADDR_STATE_UPDATE,
	8537	+ mipi_id);
	8538	+ if (ret)
	8539	+ return;
	8540	+
	8541	+ if (active_buf) {
	8542	+ active_buf->vb.vb2_buf.timestamp = stream->readout.fs_timestamp;
	8543	+ active_buf->vb.sequence = stream->frame_idx - 1;
	8544	+ rkcif_rockit_buf_done(stream, active_buf);
	8545	+ }
	8546	+}
	8547	+
	8548	+static u32 rkcif_get_sof(struct rkcif_device *cif_dev)
5363	8549	{
5364	8550	u32 val = 0x0;
5365	8551	struct rkcif_sensor_info *sensor = cif_dev->active_sensor;
	8552	+ struct csi2_dev *csi;
5366	8553
5367		- if (sensor->mbus.type == V4L2_MBUS_CSI2)
5368		- val = rkcif_csi2_get_sof();
5369		- else if (sensor->mbus.type == V4L2_MBUS_CCP2)
	8554	+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	8555	+ sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
	8556	+ csi = container_of(sensor->sd, struct csi2_dev, sd);
	8557	+ val = rkcif_csi2_get_sof(csi);
	8558	+ } else if (sensor->mbus.type == V4L2_MBUS_CCP2) {
5370	8559	val = rkcif_lvds_get_sof(cif_dev);
5371		- else if (sensor->mbus.type == V4L2_MBUS_PARALLEL \|\|
5372		- sensor->mbus.type == V4L2_MBUS_BT656)
	8560	+ } else if (sensor->mbus.type == V4L2_MBUS_PARALLEL \|\|
	8561	+ sensor->mbus.type == V4L2_MBUS_BT656) {
5373	8562	val = rkcif_dvp_get_sof(cif_dev);
5374		-
	8563	+ }
5375	8564	return val;
5376	8565	}
5377	8566
5378	8567	static void rkcif_set_sof(struct rkcif_device *cif_dev, u32 seq)
5379	8568	{
5380	8569	struct rkcif_sensor_info *sensor = cif_dev->active_sensor;
	8570	+ struct csi2_dev *csi;
5381	8571
5382		- if (sensor->mbus.type == V4L2_MBUS_CSI2)
5383		- rkcif_csi2_set_sof(seq);
5384		- else if (sensor->mbus.type == V4L2_MBUS_CCP2)
	8572	+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	8573	+ sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
	8574	+ csi = container_of(sensor->sd, struct csi2_dev, sd);
	8575	+ rkcif_csi2_set_sof(csi, seq);
	8576	+ } else if (sensor->mbus.type == V4L2_MBUS_CCP2) {
5385	8577	rkcif_lvds_set_sof(cif_dev, seq);
5386		- else if (sensor->mbus.type == V4L2_MBUS_PARALLEL \|\|
5387		- sensor->mbus.type == V4L2_MBUS_BT656)
	8578	+ } else if (sensor->mbus.type == V4L2_MBUS_PARALLEL \|\|
	8579	+ sensor->mbus.type == V4L2_MBUS_BT656) {
5388	8580	rkcif_dvp_set_sof(cif_dev, seq);
	8581	+ }
5389	8582	}
5390	8583
5391		-static int rkcif_streamoff_in_reset(struct rkcif_device *cif_dev,
5392		- struct rkcif_stream *resume_stream[],
5393		- struct rkcif_resume_info *resume_info,
5394		- enum rkmodule_reset_src reset_src)
	8584	+static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
	8585	+ enum rkmodule_reset_src reset_src)
5395	8586	{
5396		- struct rkcif_stream *stream = NULL;
5397	8587	struct rkcif_pipeline *p = &cif_dev->pipe;
	8588	+ struct rkcif_stream *stream = NULL;
	8589	+ struct rkcif_stream *resume_stream[RKCIF_MAX_STREAM_MIPI] = { NULL };
5398	8590	struct rkcif_sensor_info *terminal_sensor = &cif_dev->terminal_sensor;
5399		- u32 on, sof_cnt;
	8591	+ struct rkcif_resume_info *resume_info = &cif_dev->reset_work.resume_info;
	8592	+ struct rkcif_timer *timer = &cif_dev->reset_watchdog_timer;
5400	8593	int i, j, ret = 0;
5401		- int stream_off_cnt = 0;
	8594	+ u32 on, sof_cnt;
	8595	+ int capture_mode = 0;
	8596	+
	8597	+ mutex_lock(&cif_dev->stream_lock);
	8598	+ if (cif_dev->reset_work_cancel) {
	8599	+ ret = 0;
	8600	+ goto unlock_stream;
	8601	+ }
	8602	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset\n");
5402	8603
5403	8604	for (i = 0, j = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
5404	8605	stream = &cif_dev->stream[i];
5405		- mutex_lock(&cif_dev->stream_lock);
	8606	+
5406	8607	if (stream->state == RKCIF_STATE_STREAMING) {
5407		- stream_off_cnt++;
5408	8608
5409	8609	v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
5410	8610	"stream[%d] stopping\n", stream->id);
5411	8611
5412	8612	rkcif_stream_stop(stream);
5413	8613
5414		- atomic_dec(&p->stream_cnt);
5415		-
5416	8614	if (stream->id == RKCIF_STREAM_MIPI_ID0) {
5417	8615	sof_cnt = rkcif_get_sof(cif_dev);
5418		- v4l2_err(&cif_dev->v4l2_dev,
	8616	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
5419	8617	"%s: stream[%d] sync frmid & csi_sof, frm_id:%d, csi_sof:%d\n",
5420	8618	__func__,
5421	8619	stream->id,
5422	8620	stream->frame_idx,
5423	8621	sof_cnt);
5424	8622
5425		- resume_info->frm_sync_seq = sof_cnt;
5426		- if (stream->frame_idx != sof_cnt)
5427		- stream->frame_idx = sof_cnt;
	8623	+ resume_info->frm_sync_seq = stream->frame_idx;
5428	8624	}
5429	8625
5430	8626	stream->state = RKCIF_STATE_RESET_IN_STREAMING;
..	..	@@ -5435,59 +8631,61 @@
5435	8631
5436	8632	v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
5437	8633	"%s stop stream[%d] in streaming, frm_id:%d, csi_sof:%d\n",
5438		- __func__, stream->id, stream->frame_idx, rkcif_csi2_get_sof());
	8634	+ __func__, stream->id, stream->frame_idx, rkcif_get_sof(cif_dev));
5439	8635
5440	8636	}
5441		- mutex_unlock(&cif_dev->stream_lock);
5442	8637	}
5443		- if (!stream_off_cnt)
5444		- return 0;
5445	8638
5446	8639	on = 0;
5447	8640	for (i = 0; i < p->num_subdevs; i++) {
5448	8641
5449	8642	if (p->subdevs[i] == terminal_sensor->sd) {
5450	8643
5451		- if (reset_src == RKCIF_RESET_SRC_ERR_CSI2 \|\|
5452		- reset_src == RKCIF_RESET_SRC_ERR_HOTPLUG \|\|
5453		- reset_src == RKICF_RESET_SRC_ERR_CUTOFF) {
5454		-
	8644	+ if (reset_src != RKCIF_RESET_SRC_ERR_APP) {
5455	8645	ret = v4l2_subdev_call(p->subdevs[i], core, ioctl,
5456	8646	RKMODULE_SET_QUICK_STREAM, &on);
5457	8647	if (ret)
5458		- v4l2_err(&cif_dev->v4l2_dev, "quick stream off subdev:%s failed\n",
	8648	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	8649	+ "quick stream off subdev:%s failed\n",
5459	8650	p->subdevs[i]->name);
5460	8651	}
	8652	+ } else {
	8653	+ ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
5461	8654	}
5462		-
5463	8655	if (ret)
5464		- v4l2_err(&cif_dev->v4l2_dev, "%s:stream %s subdev:%s failed\n",
	8656	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	8657	+ "%s:stream %s subdev:%s failed\n",
5465	8658	__func__, on ? "on" : "off", p->subdevs[i]->name);
5466		-
5467	8659	}
5468		- return ret;
5469		-}
5470	8660
5471		-static int rkcif_streamon_in_reset(struct rkcif_device *cif_dev,
5472		- struct rkcif_stream *resume_stream[],
5473		- struct rkcif_resume_info *resume_info,
5474		- enum rkmodule_reset_src reset_src)
5475		-{
5476		- struct rkcif_timer *timer = &cif_dev->reset_watchdog_timer;
5477		- struct rkcif_stream *stream = NULL;
5478		- struct rkcif_pipeline *p = &cif_dev->pipe;
5479		- struct rkcif_sensor_info *terminal_sensor = &cif_dev->terminal_sensor;
5480		- int i = 0;
5481		- int ret = 0;
5482		- int on = 0;
5483		- int stream_on_cnt = 0;
	8661	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	8662	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
	8663	+ ret = v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
	8664	+ RKMODULE_SET_QUICK_STREAM, &on);
	8665	+ }
5484	8666
5485		- for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	8667	+ rockchip_clear_system_status(SYS_STATUS_CIF0);
	8668	+
	8669	+ if (cif_dev->chip_id >= CHIP_RK3588_CIF) {
	8670	+ rkcif_do_soft_reset(cif_dev);
	8671	+ } else {
	8672	+
	8673	+ rkcif_do_cru_reset(cif_dev);
	8674	+
	8675	+ rkcif_disable_sys_clk(cif_dev->hw_dev);
	8676	+
	8677	+ udelay(5);
	8678	+
	8679	+ ret = rkcif_enable_sys_clk(cif_dev->hw_dev);
	8680	+
	8681	+ if (ret < 0) {
	8682	+ v4l2_err(&cif_dev->v4l2_dev, "%s:resume cif clk failed\n", __func__);
	8683	+ goto unlock_stream;
	8684	+ }
	8685	+ }
	8686	+
	8687	+ for (i = 0; i < j; i++) {
5486	8688	stream = resume_stream[i];
5487		- if (stream == NULL \|\| stream->state != RKCIF_STATE_RESET_IN_STREAMING)
5488		- break;
5489		- mutex_lock(&cif_dev->stream_lock);
5490		- stream_on_cnt++;
5491	8689	stream->fs_cnt_in_single_frame = 0;
5492	8690	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
5493	8691	if (stream->curr_buf == stream->next_buf) {
..	..	@@ -5502,26 +8700,35 @@
5502	8700	stream->curr_buf = NULL;
5503	8701	stream->next_buf = NULL;
5504	8702	}
5505		- if (cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
5506		- cif_dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)
5507		- ret = rkcif_csi_stream_start(stream);
	8703	+ if (!cif_dev->sditf[0] \|\| cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AIQ)
	8704	+ capture_mode = RKCIF_STREAM_MODE_CAPTURE;
	8705	+ else {
	8706	+ if (cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	8707	+ capture_mode = RKCIF_STREAM_MODE_TOISP;
	8708	+ else
	8709	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	8710	+ }
	8711	+ if (cif_dev->active_sensor &&
	8712	+ (cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	8713	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	8714	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_CCP2))
	8715	+ ret = rkcif_csi_stream_start(stream, capture_mode);
5508	8716	else
5509		- ret = rkcif_stream_start(stream);
	8717	+ ret = rkcif_stream_start(stream, capture_mode);
5510	8718	if (ret) {
5511	8719	v4l2_err(&cif_dev->v4l2_dev, "%s:resume stream[%d] failed\n",
5512	8720	__func__, stream->id);
5513	8721	goto unlock_stream;
5514	8722	}
5515		- atomic_inc(&p->stream_cnt);
5516		- stream->streamon_timestamp = ktime_get_ns();
5517		- mutex_unlock(&cif_dev->stream_lock);
	8723	+
5518	8724	v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
5519	8725	"resume stream[%d], frm_idx:%d, csi_sof:%d\n",
5520	8726	stream->id, stream->frame_idx,
5521	8727	rkcif_get_sof(cif_dev));
5522	8728	}
5523		- if (!stream_on_cnt)
5524		- return 0;
	8729	+
	8730	+ rockchip_set_system_status(SYS_STATUS_CIF0);
	8731	+
5525	8732	on = 1;
5526	8733	for (i = 0; i < p->num_subdevs; i++) {
5527	8734
..	..	@@ -5529,9 +8736,7 @@
5529	8736
5530	8737	rkcif_set_sof(cif_dev, resume_info->frm_sync_seq);
5531	8738
5532		- if (reset_src == RKCIF_RESET_SRC_ERR_CSI2 \|\|
5533		- reset_src == RKCIF_RESET_SRC_ERR_HOTPLUG \|\|
5534		- reset_src == RKICF_RESET_SRC_ERR_CUTOFF) {
	8739	+ if (reset_src != RKCIF_RESET_SRC_ERR_APP) {
5535	8740	ret = v4l2_subdev_call(p->subdevs[i], core, ioctl,
5536	8741	RKMODULE_SET_QUICK_STREAM, &on);
5537	8742	if (ret)
..	..	@@ -5539,6 +8744,11 @@
5539	8744	"quick stream on subdev:%s failed\n",
5540	8745	p->subdevs[i]->name);
5541	8746	}
	8747	+ } else {
	8748	+ if (p->subdevs[i] == terminal_sensor->sd)
	8749	+ rkcif_set_sof(cif_dev, resume_info->frm_sync_seq);
	8750	+
	8751	+ ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
5542	8752	}
5543	8753
5544	8754	if (ret)
..	..	@@ -5546,71 +8756,26 @@
5546	8756	p->subdevs[i]->name);
5547	8757	}
5548	8758
5549		- rkcif_start_luma(&cif_dev->luma_vdev, resume_stream[0]->cif_fmt_in);
	8759	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	8760	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
	8761	+ v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
	8762	+ RKMODULE_SET_QUICK_STREAM, &on);
	8763	+ }
	8764	+
	8765	+ if (cif_dev->chip_id < CHIP_RK3588_CIF)
	8766	+ rkcif_start_luma(&cif_dev->luma_vdev,
	8767	+ cif_dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
5550	8768
5551	8769	timer->csi2_err_triggered_cnt = 0;
	8770	+ rkcif_monitor_reset_event(cif_dev);
5552	8771
5553	8772	v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset successfully!\n");
5554		-
5555	8773	mutex_unlock(&cif_dev->stream_lock);
5556	8774	return 0;
5557	8775
5558	8776	unlock_stream:
5559	8777	mutex_unlock(&cif_dev->stream_lock);
5560	8778	return ret;
5561		-}
5562		-
5563		-static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
5564		- enum rkmodule_reset_src reset_src)
5565		-{
5566		- struct rkcif_stream *resume_stream[RKCIF_MAX_DEV][RKCIF_MAX_STREAM_MIPI] = {0};
5567		- struct rkcif_resume_info *resume_info[RKCIF_MAX_DEV];
5568		- struct rkcif_hw *hw = cif_dev->hw_dev;
5569		- struct rkcif_device *cifdev = NULL;
5570		- int i = 0;
5571		- int ret = 0;
5572		-
5573		- v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset\n");
5574		-
5575		- for (i = 0; i < hw->dev_num; i++) {
5576		- cifdev = hw->cif_dev[i];
5577		- resume_info[i] = &cifdev->reset_work.resume_info;
5578		- ret \|= rkcif_streamoff_in_reset(cifdev,
5579		- resume_stream[i],
5580		- resume_info[i],
5581		- reset_src);
5582		- }
5583		-
5584		- rockchip_clear_system_status(SYS_STATUS_CIF0);
5585		-
5586		- rkcif_do_cru_reset(cif_dev);
5587		-
5588		- rkcif_disable_sys_clk(cif_dev->hw_dev);
5589		-
5590		- udelay(5);
5591		-
5592		- ret \|= rkcif_enable_sys_clk(cif_dev->hw_dev);
5593		- if (ret < 0)
5594		- v4l2_err(&cif_dev->v4l2_dev, "%s:resume cif clk failed\n", __func__);
5595		-
5596		- for (i = 0; i < hw->dev_num; i++) {
5597		- cifdev = hw->cif_dev[i];
5598		- resume_info[i] = &cifdev->reset_work.resume_info;
5599		- ret \|= rkcif_streamon_in_reset(cifdev,
5600		- resume_stream[i],
5601		- resume_info[i],
5602		- reset_src);
5603		- }
5604		-
5605		- rockchip_set_system_status(SYS_STATUS_CIF0);
5606		-
5607		- hw->hw_timer.is_running = false;
5608		- rkcif_monitor_reset_event(cif_dev->hw_dev);
5609		-
5610		- v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset successfully!\n");
5611		-
5612		- return ret;
5613		-
5614	8779	}
5615	8780
5616	8781	void rkcif_reset_work(struct work_struct *work)
..	..	@@ -5628,128 +8793,183 @@
5628	8793	v4l2_info(&dev->v4l2_dev, "do reset work failed!\n");
5629	8794	}
5630	8795
5631		-static bool rkcif_is_stream_stop_output(struct rkcif_stream *stream)
	8796	+static bool rkcif_is_reduced_frame_rate(struct rkcif_device *dev)
5632	8797	{
5633		- struct rkcif_device *dev = stream->cifdev;
5634		- struct rkcif_hw_timer *hw_timer = &dev->hw_dev->hw_timer;
5635		- struct rkcif_stream *tmp_stream = NULL;
	8798	+ struct rkcif_timer *timer = &dev->reset_watchdog_timer;
	8799	+ struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
5636	8800	struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
5637		- u64 fps, diff_time;
5638		- unsigned int i;
5639		- s64 vblank_def = 0;
5640		- s32 vblank = 0;
5641		- u64 numerator = 0;
5642		- u64 denominator = 0;
5643		- u64 cur_timestamp = 0;
	8801	+ u64 fps, timestamp0, timestamp1, diff_time;
	8802	+ unsigned long fps_flags;
	8803	+ unsigned int deviation = 1;
	8804	+ bool is_reduced = false;
	8805	+ u64 cur_time = 0;
	8806	+ u64 time_distance = 0;
5644	8807
5645		- if (dev->hdr.mode == HDR_X3) {
5646		- for (i = 0; i < 3; i++) {
5647		- tmp_stream = &dev->stream[i];
5648		- if (tmp_stream->state != RKCIF_STATE_STREAMING)
5649		- return false;
5650		- }
5651		- } else if (dev->hdr.mode == HDR_X2) {
5652		- for (i = 0; i < 2; i++) {
5653		- tmp_stream = &dev->stream[i];
5654		- if (tmp_stream->state != RKCIF_STATE_STREAMING)
5655		- return false;
5656		- }
5657		- }
	8808	+ spin_lock_irqsave(&stream->fps_lock, fps_flags);
	8809	+ timestamp0 = stream->fps_stats.frm0_timestamp;
	8810	+ timestamp1 = stream->fps_stats.frm1_timestamp;
	8811	+ spin_unlock_irqrestore(&stream->fps_lock, fps_flags);
5658	8812
5659		- vblank_def = rkcif_get_sensor_vblank_def(dev);
5660		- vblank = rkcif_get_sensor_vblank(dev);
5661		- numerator = dev->terminal_sensor.fi.interval.numerator;
5662		- denominator = dev->terminal_sensor.fi.interval.denominator;
5663		- fps = div_u64(1000 * numerator, denominator);
5664		- fps *= (raw_rect->height + vblank);
5665		- fps = div_u64((raw_rect->height + vblank_def), fps);
	8813	+ fps = timestamp0 > timestamp1 ?
	8814	+ timestamp0 - timestamp1 : timestamp1 - timestamp0;
	8815	+ fps = div_u64(fps, 1000);
	8816	+ diff_time = fps > timer->frame_end_cycle_us ?
	8817	+ fps - timer->frame_end_cycle_us : 0;
	8818	+ deviation = DIV_ROUND_UP(timer->vts, 100);
5666	8819
5667		- if (fps > hw_timer->monitor_cycle) {
5668		- v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "camera work in long expsure, not to check stream loss\n");
	8820	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "diff_time:%lld,devi_t:%ld,devi_h:%d\n",
	8821	+ diff_time, timer->line_end_cycle * deviation, deviation);
	8822	+
	8823	+ cur_time = ktime_get_ns();
	8824	+ time_distance = timestamp0 > timestamp1 ?
	8825	+ cur_time - timestamp0 : cur_time - timestamp1;
	8826	+ time_distance = div_u64(time_distance, 1000);
	8827	+ if (time_distance > fps * 2)
5669	8828	return false;
	8829	+
	8830	+ if (diff_time > timer->line_end_cycle * deviation) {
	8831	+ s32 vblank = 0;
	8832	+ unsigned int vts;
	8833	+
	8834	+ is_reduced = true;
	8835	+ vblank = rkcif_get_sensor_vblank(dev);
	8836	+ vts = vblank + timer->raw_height;
	8837	+
	8838	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "old vts:%d,new vts:%d\n", timer->vts, vts);
	8839	+
	8840	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	8841	+ "reduce frame rate,vblank:%d, height(raw output):%d, fps:%lld, frm_end_t:%ld, line_t:%ld, diff:%lld\n",
	8842	+ rkcif_get_sensor_vblank(dev),
	8843	+ raw_rect->height,
	8844	+ fps,
	8845	+ timer->frame_end_cycle_us,
	8846	+ timer->line_end_cycle,
	8847	+ diff_time);
	8848	+
	8849	+ timer->vts = vts;
	8850	+ timer->frame_end_cycle_us = fps;
	8851	+ timer->line_end_cycle = div_u64(timer->frame_end_cycle_us, timer->vts);
	8852	+ } else {
	8853	+ is_reduced = false;
5670	8854	}
5671	8855
5672		- cur_timestamp = ktime_get_ns();
5673		- diff_time = cur_timestamp - stream->streamon_timestamp;
5674		- diff_time = div_u64(diff_time, 1000000);
5675		- if (diff_time > hw_timer->monitor_cycle + 10)
5676		- return true;
	8856	+ timer->frame_end_cycle_us = fps;
5677	8857
5678		- return false;
	8858	+ fps = div_u64(fps, 1000);
	8859	+ fps = fps * timer->frm_num_of_monitor_cycle;
	8860	+ timer->cycle = msecs_to_jiffies(fps);
	8861	+ timer->timer.expires = jiffies + timer->cycle;
	8862	+
	8863	+ return is_reduced;
	8864	+
5679	8865	}
5680	8866
5681		-static void rkcif_init_reset_work(struct rkcif_hw_timer *hw_timer)
	8867	+static void rkcif_dvp_event_reset_pipe(struct rkcif_device *dev, int reset_src)
5682	8868	{
5683		- struct rkcif_hw *hw = container_of(hw_timer,
5684		- struct rkcif_hw,
5685		- hw_timer);
5686		- struct rkcif_device *dev = NULL;
	8869	+ struct rkcif_dvp_sof_subdev *subdev = &dev->dvp_sof_subdev;
	8870	+
	8871	+ if (subdev) {
	8872	+ struct v4l2_event event = {
	8873	+ .type = V4L2_EVENT_RESET_DEV,
	8874	+ .reserved[0] = reset_src,
	8875	+ };
	8876	+ v4l2_event_queue(subdev->sd.devnode, &event);
	8877	+ }
	8878	+}
	8879	+
	8880	+static void rkcif_lvds_event_reset_pipe(struct rkcif_device *dev, int reset_src)
	8881	+{
	8882	+ struct rkcif_lvds_subdev *subdev = &dev->lvds_subdev;
	8883	+
	8884	+ if (subdev) {
	8885	+ struct v4l2_event event = {
	8886	+ .type = V4L2_EVENT_RESET_DEV,
	8887	+ .reserved[0] = reset_src,
	8888	+ };
	8889	+ v4l2_event_queue(subdev->sd.devnode, &event);
	8890	+ }
	8891	+}
	8892	+
	8893	+static void rkcif_send_reset_event(struct rkcif_device *cif_dev, int reset_src)
	8894	+{
	8895	+ struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
	8896	+ struct csi2_dev *csi;
	8897	+
	8898	+ if (mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	8899	+ mbus->type == V4L2_MBUS_CSI2_CPHY) {
	8900	+ csi = container_of(cif_dev->active_sensor->sd, struct csi2_dev, sd);
	8901	+ rkcif_csi2_event_reset_pipe(csi, reset_src);
	8902	+ } else if (mbus->type == V4L2_MBUS_CCP2) {
	8903	+ rkcif_lvds_event_reset_pipe(cif_dev, reset_src);
	8904	+ } else {
	8905	+ rkcif_dvp_event_reset_pipe(cif_dev, reset_src);
	8906	+ }
	8907	+ v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
	8908	+ "send reset event,bus type 0x%x\n",
	8909	+ mbus->type);
	8910	+}
	8911	+
	8912	+static void rkcif_init_reset_work(struct rkcif_timer *timer)
	8913	+{
	8914	+ struct rkcif_device *dev = container_of(timer,
	8915	+ struct rkcif_device,
	8916	+ reset_watchdog_timer);
5687	8917	struct rkcif_stream *stream = NULL;
5688		- struct rkcif_timer *timer;
5689	8918	unsigned long flags;
5690		- int i = 0, j = 0;
	8919	+ int i = 0;
5691	8920
5692	8921	v4l2_info(&dev->v4l2_dev,
5693	8922	"do reset work schedule, run_cnt:%d, reset source:%d\n",
5694		- hw_timer->run_cnt, hw_timer->reset_src);
	8923	+ timer->run_cnt, timer->reset_src);
5695	8924
5696		- for (j = 0; j < hw->dev_num; j++) {
5697		- dev = hw->cif_dev[j];
5698		- timer = &dev->reset_watchdog_timer;
5699		- spin_lock_irqsave(&timer->csi2_err_lock, flags);
5700		- timer->is_triggered = false;
5701		- timer->csi2_err_cnt_odd = 0;
5702		- timer->csi2_err_cnt_even = 0;
5703		- timer->csi2_err_fs_fe_cnt = 0;
5704		- timer->notifer_called_cnt = 0;
5705		- for (i = 0; i < dev->num_channels; i++) {
5706		- stream = &dev->stream[i];
5707		- if (stream->state == RKCIF_STATE_STREAMING)
5708		- timer->last_buf_wakeup_cnt[stream->id] = stream->frame_idx;
5709		- }
5710		- spin_unlock_irqrestore(&timer->csi2_err_lock, flags);
	8925	+ spin_lock_irqsave(&timer->timer_lock, flags);
	8926	+ timer->is_running = false;
	8927	+ timer->is_triggered = false;
	8928	+ timer->csi2_err_cnt_odd = 0;
	8929	+ timer->csi2_err_cnt_even = 0;
	8930	+ timer->csi2_err_fs_fe_cnt = 0;
	8931	+ timer->notifer_called_cnt = 0;
	8932	+ for (i = 0; i < dev->num_channels; i++) {
	8933	+ stream = &dev->stream[i];
	8934	+ if (stream->state == RKCIF_STATE_STREAMING)
	8935	+ timer->last_buf_wakeup_cnt[stream->id] = stream->buf_wake_up_cnt;
5711	8936	}
5712		- if (hw_timer->is_reset_by_user) {
5713		- hw->reset_info.is_need_reset = 1;
5714		- hw->reset_info.reset_src = hw_timer->reset_src;
	8937	+ spin_unlock_irqrestore(&timer->timer_lock, flags);
	8938	+ if (timer->is_ctrl_by_user) {
	8939	+ rkcif_send_reset_event(dev, timer->reset_src);
5715	8940	} else {
5716		- dev->reset_work.reset_src = hw_timer->reset_src;
5717		- if (schedule_work(&dev->reset_work.work)) {
	8941	+ if (!schedule_work(&dev->reset_work.work))
5718	8942	v4l2_info(&dev->v4l2_dev,
5719		- "schedule reset work successfully\n");
5720		- } else {
5721		- v4l2_info(&dev->v4l2_dev,
5722		- "schedule reset work failed\n");
5723		- }
	8943	+ "schedule reset work failed\n");
	8944	+ dev->reset_work.reset_src = timer->reset_src;
5724	8945	}
5725	8946	}
5726	8947
5727	8948	static int rkcif_detect_reset_event(struct rkcif_stream *stream,
5728	8949	struct rkcif_timer *timer,
5729		- int *check_cnt,
	8950	+ int check_cnt,
5730	8951	bool *is_mod_timer)
5731	8952	{
5732	8953	struct rkcif_device *dev = stream->cifdev;
5733	8954	struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
5734		- struct rkcif_hw_timer *hw_timer = &dev->hw_dev->hw_timer;
	8955	+ unsigned long flags;
5735	8956	int ret, is_reset = 0;
5736	8957	struct rkmodule_vicap_reset_info rst_info;
5737	8958
5738		- v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
5739		- "info: frame end still update(%d, %d), detect cnt: %d, mode:%d check_cnt:%d\n",
5740		- timer->last_buf_wakeup_cnt[stream->id], stream->frame_idx,
5741		- hw_timer->run_cnt, hw_timer->monitor_mode, *check_cnt);
	8959	+ if (timer->last_buf_wakeup_cnt[stream->id] < stream->buf_wake_up_cnt &&
	8960	+ check_cnt == 0) {
5742	8961
5743		- if (timer->last_buf_wakeup_cnt[stream->id] < stream->frame_idx) {
5744		- *check_cnt += 1;
5745	8962	v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
5746		- "info: frame end still update(%d, %d), detect cnt: %d, mode:%d\n",
	8963	+ "info: frame end still update(%d, %d) in detecting cnt:%d, mode:%d\n",
5747	8964	timer->last_buf_wakeup_cnt[stream->id], stream->frame_idx,
5748		- hw_timer->run_cnt, hw_timer->monitor_mode);
	8965	+ timer->run_cnt, timer->monitor_mode);
5749	8966
5750		- timer->last_buf_wakeup_cnt[stream->id] = stream->frame_idx;
	8967	+ timer->last_buf_wakeup_cnt[stream->id] = stream->buf_wake_up_cnt;
5751	8968
5752		- if (hw_timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
	8969	+ if (stream->frame_idx > 2)
	8970	+ rkcif_is_reduced_frame_rate(dev);
	8971	+
	8972	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
5753	8973	ret = v4l2_subdev_call(terminal_sensor->sd,
5754	8974	core, ioctl,
5755	8975	RKMODULE_GET_VICAP_RST_INFO,
..	..	@@ -5759,144 +8979,139 @@
5759	8979	else
5760	8980	is_reset = rst_info.is_reset;
5761	8981	rst_info.is_reset = 0;
5762		- hw_timer->reset_src = RKCIF_RESET_SRC_ERR_HOTPLUG;
	8982	+ if (is_reset)
	8983	+ timer->reset_src = RKCIF_RESET_SRC_ERR_HOTPLUG;
5763	8984	v4l2_subdev_call(terminal_sensor->sd, core, ioctl,
5764	8985	RKMODULE_SET_VICAP_RST_INFO, &rst_info);
5765		- if (!is_reset && stream->cifdev->inf_id == RKCIF_MIPI_LVDS)
	8986	+ if (!is_reset) {
5766	8987	is_reset = rkcif_is_csi2_err_trigger_reset(timer);
5767		- } else if (hw_timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE) {
5768		- if (stream->cifdev->inf_id == RKCIF_MIPI_LVDS)
5769		- is_reset = rkcif_is_csi2_err_trigger_reset(timer);
5770		- } else if (hw_timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
5771		- if (stream->cifdev->inf_id == RKCIF_MIPI_LVDS) {
5772		- is_reset = timer->is_csi2_err_occurred;
5773	8988	if (is_reset)
5774		- hw_timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
5775		- timer->is_csi2_err_occurred = false;
	8989	+ timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
5776	8990	}
	8991	+ } else if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE) {
	8992	+ is_reset = rkcif_is_csi2_err_trigger_reset(timer);
	8993	+ } else if (timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
	8994	+ is_reset = timer->is_csi2_err_occurred;
	8995	+ if (is_reset)
	8996	+ timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
	8997	+ timer->is_csi2_err_occurred = false;
5777	8998	}
5778	8999
5779	9000	if (is_reset) {
5780		- rkcif_init_reset_work(hw_timer);
	9001	+ rkcif_init_reset_work(timer);
5781	9002	return is_reset;
5782	9003	}
5783		- *is_mod_timer = true;
5784		- } else if (timer->last_buf_wakeup_cnt[stream->id] == stream->frame_idx) {
5785		- bool is_loss_stream = false;
5786	9004
5787		- *check_cnt += 1;
5788		- if (hw_timer->run_cnt > 4)
5789		- is_loss_stream = rkcif_is_stream_stop_output(stream);
5790		-
5791		- if (is_loss_stream) {
5792		- v4l2_info(&dev->v4l2_dev,
5793		- "do reset work due to frame end is stopped, run_cnt:%d\n",
5794		- hw_timer->run_cnt);
5795		-
5796		- hw_timer->reset_src = RKICF_RESET_SRC_ERR_CUTOFF;
5797		- is_reset = true;
5798		- rkcif_init_reset_work(hw_timer);
	9005	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE \|\|
	9006	+ timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
	9007	+ if (timer->run_cnt == timer->max_run_cnt)
	9008	+ timer->run_cnt = 0x0;
	9009	+ *is_mod_timer = true;
5799	9010	} else {
	9011	+ if (timer->run_cnt <= timer->max_run_cnt) {
	9012	+ *is_mod_timer = true;
	9013	+ } else {
	9014	+ spin_lock_irqsave(&timer->timer_lock, flags);
	9015	+ timer->is_triggered = false;
	9016	+ timer->is_running = false;
	9017	+ spin_unlock_irqrestore(&timer->timer_lock, flags);
	9018	+ v4l2_info(&dev->v4l2_dev, "stop reset detecting!\n");
	9019	+ }
	9020	+ }
	9021	+ } else if (timer->last_buf_wakeup_cnt[stream->id] == stream->buf_wake_up_cnt) {
	9022	+
	9023	+ bool is_reduced = false;
	9024	+
	9025	+ if (stream->frame_idx > 2)
	9026	+ is_reduced = rkcif_is_reduced_frame_rate(dev);
	9027	+ else if (timer->run_cnt < 20)
	9028	+ is_reduced = true;
	9029	+
	9030	+ if (is_reduced) {
5800	9031	*is_mod_timer = true;
5801	9032	v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s fps is reduced\n", __func__);
	9033	+ } else {
	9034	+
	9035	+ v4l2_info(&dev->v4l2_dev,
	9036	+ "do reset work due to frame end is stopped, run_cnt:%d\n",
	9037	+ timer->run_cnt);
	9038	+
	9039	+ timer->reset_src = RKICF_RESET_SRC_ERR_CUTOFF;
	9040	+ rkcif_init_reset_work(timer);
	9041	+ is_reset = true;
5802	9042	}
5803	9043	}
5804	9044
5805		- return is_reset;
5806		-
5807		-}
5808		-
5809		-static int rkcif_dvp_err_trigger_reset(struct rkcif_device *dev)
5810		-{
5811		- int is_reset = 0;
5812		-
5813		- if (dev->irq_stats.dvp_overflow_cnt) {
5814		- dev->irq_stats.dvp_overflow_cnt = 0;
5815		- is_reset = 1;
5816		- }
5817		- return is_reset;
5818		-}
5819		-
5820		-static int rkcif_detect_reset_event_all_dev(struct rkcif_device *dev,
5821		- int *check_cnt,
5822		- bool *is_mod_timer)
5823		-{
5824		- struct rkcif_timer *timer = &dev->reset_watchdog_timer;
5825		- struct rkcif_stream *stream = NULL;
5826		- int i = 0;
5827		- int is_reset = 0;
5828		- int check_cnt_local = 0;
5829		-
5830		- for (i = 0; i < dev->num_channels; i++) {
5831		- stream = &dev->stream[i];
5832		- if (stream->state == RKCIF_STATE_STREAMING) {
5833		- is_reset = rkcif_detect_reset_event(stream,
5834		- timer,
5835		- &check_cnt_local,
5836		- is_mod_timer);
5837		- if (is_reset)
5838		- break;
5839		- }
5840		- }
5841		- if (!is_reset && dev->inf_id == RKCIF_DVP)
5842		- is_reset = rkcif_dvp_err_trigger_reset(dev);
5843		-
5844		- if (check_cnt_local)
5845		- *check_cnt += 1;
5846	9045	return is_reset;
5847	9046
5848	9047	}
5849	9048
5850	9049	void rkcif_reset_watchdog_timer_handler(struct timer_list *t)
5851	9050	{
5852		- struct rkcif_hw_timer *hw_timer = container_of(t, struct rkcif_hw_timer, timer);
5853		- struct rkcif_hw *hw = container_of(hw_timer,
5854		- struct rkcif_hw,
5855		- hw_timer);
5856		- struct rkcif_device *dev = NULL;
	9051	+ struct rkcif_timer *timer = container_of(t, struct rkcif_timer, timer);
	9052	+ struct rkcif_device *dev = container_of(timer,
	9053	+ struct rkcif_device,
	9054	+ reset_watchdog_timer);
	9055	+ struct rkcif_stream *stream = NULL;
5857	9056	unsigned long flags;
5858	9057	unsigned int i;
5859	9058	int is_reset = 0;
5860	9059	int check_cnt = 0;
5861	9060	bool is_mod_timer = false;
5862	9061
5863		- for (i = 0; i < hw->dev_num; i++) {
5864		- dev = hw->cif_dev[i];
5865		- is_reset = rkcif_detect_reset_event_all_dev(dev,
5866		- &check_cnt,
	9062	+ for (i = 0; i < dev->num_channels; i++) {
	9063	+ stream = &dev->stream[i];
	9064	+ if (stream->state == RKCIF_STATE_STREAMING) {
	9065	+ is_reset = rkcif_detect_reset_event(stream,
	9066	+ timer,
	9067	+ check_cnt,
5867	9068	&is_mod_timer);
5868		- if (is_reset)
5869		- break;
5870		-
	9069	+ check_cnt++;
	9070	+ if (is_reset)
	9071	+ break;
	9072	+ }
5871	9073	}
5872		-
5873	9074	if (!is_reset && is_mod_timer)
5874		- mod_timer(&hw_timer->timer, jiffies + hw_timer->cycle_jif);
	9075	+ mod_timer(&timer->timer, jiffies + timer->cycle);
5875	9076
5876		- hw_timer->run_cnt += 1;
	9077	+ timer->run_cnt += 1;
5877	9078
5878		- if (!check_cnt && !is_reset) {
5879		- spin_lock_irqsave(&hw_timer->timer_lock, flags);
5880		- hw_timer->is_running = false;
5881		- spin_unlock_irqrestore(&hw_timer->timer_lock, flags);
	9079	+ if (!check_cnt) {
	9080	+ spin_lock_irqsave(&timer->timer_lock, flags);
	9081	+ timer->is_triggered = false;
	9082	+ timer->is_running = false;
	9083	+ spin_unlock_irqrestore(&timer->timer_lock, flags);
5882	9084
5883		- dev_info(hw->dev,
5884		- "all stream is stopped, stop reset detect!\n");
	9085	+ v4l2_info(&dev->v4l2_dev,
	9086	+ "all stream is stopped, stop reset detect!\n");
5885	9087	}
5886	9088	}
5887	9089
5888	9090	int rkcif_reset_notifier(struct notifier_block *nb,
5889	9091	unsigned long action, void *data)
5890	9092	{
5891		- struct rkcif_device *dev = container_of(nb, struct rkcif_device, reset_notifier);
5892		- struct rkcif_timer *timer = &dev->reset_watchdog_timer;
5893		- struct rkcif_hw_timer *hw_timer = &dev->hw_dev->hw_timer;
	9093	+ struct rkcif_hw *hw = container_of(nb, struct rkcif_hw, reset_notifier);
	9094	+ struct rkcif_device *dev = NULL;
	9095	+ struct rkcif_timer *timer = NULL;
5894	9096	unsigned long flags, val;
	9097	+ u32 *csi_idx = data;
	9098	+ int i = 0;
	9099	+ bool is_match_dev = false;
5895	9100
5896		- if (hw_timer->is_running) {
	9101	+ for (i = 0; i < hw->dev_num; i++) {
	9102	+ dev = hw->cif_dev[i];
	9103	+ if (*csi_idx == dev->csi_host_idx) {
	9104	+ is_match_dev = true;
	9105	+ break;
	9106	+ }
	9107	+ }
	9108	+ if (!is_match_dev)
	9109	+ return -EINVAL;
	9110	+ timer = &dev->reset_watchdog_timer;
	9111	+ if (timer->is_running) {
5897	9112	val = action & CSI2_ERR_COUNT_ALL_MASK;
5898	9113	spin_lock_irqsave(&timer->csi2_err_lock, flags);
5899		- if ((val % hw_timer->err_ref_cnt) == 0) {
	9114	+ if ((val % timer->csi2_err_ref_cnt) == 0) {
5900	9115	timer->notifer_called_cnt++;
5901	9116	if ((timer->notifer_called_cnt % 2) == 0)
5902	9117	timer->csi2_err_cnt_even = val;
..	..	@@ -5914,7 +9129,12 @@
5914	9129	static void rkcif_modify_line_int(struct rkcif_stream *stream, bool en)
5915	9130	{
5916	9131	struct rkcif_device *cif_dev = stream->cifdev;
	9132	+ u32 line_intr_en = 0;
5917	9133
	9134	+ if (cif_dev->chip_id >= CHIP_RK3588_CIF)
	9135	+ line_intr_en = CSI_LINE_INTEN_RK3588(stream->id);
	9136	+ else
	9137	+ line_intr_en = CSI_LINE_INTEN(stream->id);
5918	9138	if (en) {
5919	9139	if (cif_dev->wait_line_bak != cif_dev->wait_line) {
5920	9140	cif_dev->wait_line_bak = cif_dev->wait_line;
..	..	@@ -5924,44 +9144,73 @@
5924	9144	cif_dev->wait_line << 16 \| cif_dev->wait_line);
5925	9145	}
5926	9146	rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
5927		- CSI_LINE_INTEN(stream->id));
	9147	+ line_intr_en);
	9148	+ stream->is_line_inten = true;
5928	9149	} else {
5929	9150	rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
5930		- ~(CSI_LINE_INTEN(stream->id)));
	9151	+ ~line_intr_en);
5931	9152	}
5932	9153	}
5933	9154
5934	9155	static void rkcif_detect_wake_up_mode_change(struct rkcif_stream *stream)
5935	9156	{
5936	9157	struct rkcif_device *cif_dev = stream->cifdev;
	9158	+ struct sditf_priv *priv = cif_dev->sditf[0];
	9159	+ bool is_change = false;
	9160	+ int ch = 0;
	9161	+ int i = 0;
	9162	+
	9163	+ if (!priv \|\| priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	9164	+ return;
	9165	+
	9166	+ if ((cif_dev->hdr.hdr_mode == NO_HDR \|\| cif_dev->hdr.hdr_mode == HDR_COMPR) &&
	9167	+ stream->id == RKCIF_STREAM_MIPI_ID0) {
	9168	+ if (cif_dev->wait_line != cif_dev->wait_line_cache)
	9169	+ cif_dev->wait_line = cif_dev->wait_line_cache;
	9170	+ } else if (cif_dev->hdr.hdr_mode == HDR_X2 && stream->id == RKCIF_STREAM_MIPI_ID1) {
	9171	+ if (cif_dev->wait_line != cif_dev->wait_line_cache)
	9172	+ cif_dev->wait_line = cif_dev->wait_line_cache;
	9173	+ } else if (cif_dev->hdr.hdr_mode == HDR_X3 && stream->id == RKCIF_STREAM_MIPI_ID2) {
	9174	+ if (cif_dev->wait_line != cif_dev->wait_line_cache)
	9175	+ cif_dev->wait_line = cif_dev->wait_line_cache;
	9176	+ }
5937	9177
5938	9178	if (cif_dev->wait_line && (!stream->is_line_wake_up)) {
	9179	+ is_change = true;
5939	9180	stream->is_line_wake_up = true;
5940	9181	if (stream->frame_phase == CIF_CSI_FRAME0_READY)
5941	9182	stream->line_int_cnt = 1;
5942	9183	else if (stream->frame_phase == CIF_CSI_FRAME1_READY)
5943	9184	stream->line_int_cnt = 0;
	9185	+ if (cif_dev->hdr.hdr_mode == HDR_X2) {
	9186	+ cif_dev->stream[0].is_line_wake_up = true;
	9187	+ cif_dev->stream[0].line_int_cnt = stream->line_int_cnt;
	9188	+ } else if (cif_dev->hdr.hdr_mode == HDR_X3) {
	9189	+ cif_dev->stream[0].is_line_wake_up = true;
	9190	+ cif_dev->stream[1].is_line_wake_up = true;
	9191	+ cif_dev->stream[0].line_int_cnt = stream->line_int_cnt;
	9192	+ cif_dev->stream[1].line_int_cnt = stream->line_int_cnt;
	9193	+ }
5944	9194	} else if ((cif_dev->wait_line == 0) && stream->is_line_wake_up) {
5945	9195	stream->is_line_wake_up = false;
5946	9196	}
5947	9197	if (stream->is_line_wake_up) {
5948		- rkcif_modify_line_int(stream, true);
5949		- stream->is_line_inten = true;
5950		- }
5951		-
5952		- if (cif_dev->hdr.mode == NO_HDR && stream->id == RKCIF_STREAM_MIPI_ID0) {
5953		- if (cif_dev->wait_line != cif_dev->wait_line_cache)
5954		- cif_dev->wait_line = cif_dev->wait_line_cache;
5955		- } else if (cif_dev->hdr.mode == HDR_X2 && stream->id == RKCIF_STREAM_MIPI_ID1) {
5956		- if (cif_dev->wait_line != cif_dev->wait_line_cache)
5957		- cif_dev->wait_line = cif_dev->wait_line_cache;
5958		- } else if (cif_dev->hdr.mode == HDR_X3 && stream->id == RKCIF_STREAM_MIPI_ID2) {
5959		- if (cif_dev->wait_line != cif_dev->wait_line_cache)
5960		- cif_dev->wait_line = cif_dev->wait_line_cache;
	9198	+ if (is_change) {
	9199	+ if (cif_dev->hdr.hdr_mode == HDR_X2)
	9200	+ ch = 2;
	9201	+ else if (cif_dev->hdr.hdr_mode == HDR_X3)
	9202	+ ch = 3;
	9203	+ else
	9204	+ ch = 1;
	9205	+ for (i = 0; i < ch; i++)
	9206	+ rkcif_modify_line_int(&cif_dev->stream[i], true);
	9207	+ } else {
	9208	+ rkcif_modify_line_int(stream, true);
	9209	+ }
5961	9210	}
5962	9211	}
5963	9212
5964		-static u32 rkisp_mbus_pixelcode_to_v4l2(u32 pixelcode)
	9213	+u32 rkcif_mbus_pixelcode_to_v4l2(u32 pixelcode)
5965	9214	{
5966	9215	u32 pixelformat;
5967	9216
..	..	@@ -6050,13 +9299,14 @@
6050	9299	v4l2_subdev_call(cif_dev->terminal_sensor.sd, pad, get_fmt, NULL, &fmt);
6051	9300
6052	9301	memset(&pixm, 0, sizeof(pixm));
6053		- pixm.pixelformat = rkisp_mbus_pixelcode_to_v4l2(fmt.format.code);
	9302	+ pixm.pixelformat = rkcif_mbus_pixelcode_to_v4l2(fmt.format.code);
6054	9303	pixm.width = fmt.format.width;
6055	9304	pixm.height = fmt.format.height;
6056	9305
6057	9306	memset(&input_sel, 0, sizeof(input_sel));
6058	9307	input_sel.pad = i;
6059	9308	input_sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
	9309	+ input_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
6060	9310	ret = v4l2_subdev_call(cif_dev->terminal_sensor.sd,
6061	9311	pad, get_selection, NULL,
6062	9312	&input_sel);
..	..	@@ -6069,12 +9319,880 @@
6069	9319	}
6070	9320	}
6071	9321
	9322	+void rkcif_enable_dma_capture(struct rkcif_stream *stream, bool is_only_enable)
	9323	+{
	9324	+ struct rkcif_device *cif_dev = stream->cifdev;
	9325	+ struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
	9326	+ struct csi_channel_info *channel = &cif_dev->channels[stream->id];
	9327	+ u32 val = 0;
	9328	+
	9329	+ if (stream->buf_owner == RKCIF_DMAEN_BY_ISP)
	9330	+ stream->buf_owner = RKCIF_DMAEN_BY_ISP_TO_VICAP;
	9331	+
	9332	+ if (stream->dma_en) {
	9333	+ stream->dma_en \|= stream->to_en_dma;
	9334	+ stream->to_en_dma = 0;
	9335	+ return;
	9336	+ }
	9337	+
	9338	+ stream->dma_en \|= stream->to_en_dma;
	9339	+ if (!is_only_enable) {
	9340	+ if (stream->to_en_dma == RKCIF_DMAEN_BY_VICAP) {
	9341	+ rkcif_assign_new_buffer_pingpong(stream,
	9342	+ RKCIF_YUV_ADDR_STATE_INIT,
	9343	+ stream->id);
	9344	+ rkcif_write_register(cif_dev, get_reg_index_of_frm0_y_vlw(stream->id),
	9345	+ channel->virtual_width);
	9346	+ } else if (stream->to_en_dma == RKCIF_DMAEN_BY_ISP) {
	9347	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	9348	+ RKCIF_YUV_ADDR_STATE_INIT,
	9349	+ stream->id);
	9350	+ }
	9351	+ }
	9352	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	9353	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
	9354	+ rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_CTRL, 0x00010000);
	9355	+ else
	9356	+ rkcif_write_register_or(cif_dev, CIF_REG_DVP_CTRL, 0x00010000);
	9357	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	9358	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY) {
	9359	+ val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
	9360	+ if (!stream->is_compact)
	9361	+ val \|= CSI_WRDDR_TYPE_RAW_UNCOMPACT;
	9362	+ else
	9363	+ val &= ~CSI_WRDDR_TYPE_RAW_UNCOMPACT;
	9364	+ val \|= CSI_DMA_ENABLE;
	9365	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id), val);
	9366	+ } else if (mbus_cfg->type == V4L2_MBUS_CCP2) {
	9367	+ val = rkcif_read_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id));
	9368	+ if (!stream->is_compact)
	9369	+ val \|= CSI_WRDDR_TYPE_RAW_UNCOMPACT << 17;
	9370	+ else
	9371	+ val &= ~(CSI_WRDDR_TYPE_RAW_UNCOMPACT << 17);
	9372	+ val \|= LVDS_DMAEN_RV1106;
	9373	+ rkcif_write_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id), val);
	9374	+ } else {
	9375	+ val = rkcif_read_register(cif_dev, CIF_REG_DVP_FOR);
	9376	+ if (!stream->is_compact)
	9377	+ val \|= CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
	9378	+ else
	9379	+ val &= ~(CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11);
	9380	+ rkcif_write_register(cif_dev, CIF_REG_DVP_FOR, val);
	9381	+ val = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
	9382	+ if (cif_dev->chip_id == CHIP_RK3588_CIF)
	9383	+ val \|= DVP_DMA_EN;
	9384	+ else if (cif_dev->chip_id == CHIP_RV1106_CIF)
	9385	+ val \|= DVP_SW_DMA_EN(stream->id);
	9386	+ rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
	9387	+ }
	9388	+
	9389	+ stream->to_en_dma = 0;
	9390	+}
	9391	+
	9392	+static int rkcif_stop_dma_capture(struct rkcif_stream *stream)
	9393	+{
	9394	+ struct rkcif_device *cif_dev = stream->cifdev;
	9395	+ struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
	9396	+ u32 val = 0;
	9397	+
	9398	+ if (stream->buf_replace_cnt)
	9399	+ return -EINVAL;
	9400	+
	9401	+ stream->dma_en &= ~stream->to_stop_dma;
	9402	+
	9403	+ if (stream->dma_en != 0) {
	9404	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
	9405	+ stream->buf_owner = RKCIF_DMAEN_BY_ISP;
	9406	+ stream->to_stop_dma = 0;
	9407	+ return 0;
	9408	+ }
	9409	+
	9410	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	9411	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY) {
	9412	+ val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
	9413	+ val &= ~CSI_DMA_ENABLE;
	9414	+ if (stream->is_stop_capture) {
	9415	+ val &= ~CSI_ENABLE_CAPTURE;
	9416	+ stream->is_stop_capture = false;
	9417	+ }
	9418	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id), val);
	9419	+ } else if (mbus_cfg->type == V4L2_MBUS_CCP2) {
	9420	+ val = rkcif_read_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id));
	9421	+ val &= ~LVDS_DMAEN_RV1106;
	9422	+ if (stream->is_stop_capture) {
	9423	+ val &= ~ENABLE_CAPTURE;
	9424	+ stream->is_stop_capture = false;
	9425	+ }
	9426	+ rkcif_write_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id), val);
	9427	+ } else {
	9428	+ val = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
	9429	+ if (cif_dev->chip_id == CHIP_RK3588_CIF)
	9430	+ val &= ~DVP_DMA_EN;
	9431	+ else if (cif_dev->chip_id == CHIP_RV1106_CIF)
	9432	+ val &= ~(DVP_SW_DMA_EN(stream->id));
	9433	+ if (stream->is_stop_capture) {
	9434	+ val &= ~ENABLE_CAPTURE;
	9435	+ stream->is_stop_capture = false;
	9436	+ }
	9437	+ rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
	9438	+ }
	9439	+ stream->to_stop_dma = 0;
	9440	+ return 0;
	9441	+}
	9442	+
	9443	+static void rkcif_send_sof(struct rkcif_device *cif_dev)
	9444	+{
	9445	+ struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
	9446	+ struct csi2_dev *csi;
	9447	+
	9448	+ if (mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	9449	+ mbus->type == V4L2_MBUS_CSI2_CPHY) {
	9450	+ csi = container_of(cif_dev->active_sensor->sd, struct csi2_dev, sd);
	9451	+ rkcif_csi2_event_inc_sof(csi);
	9452	+ } else if (mbus->type == V4L2_MBUS_CCP2) {
	9453	+ rkcif_lvds_event_inc_sof(cif_dev);
	9454	+ } else {
	9455	+ rkcif_dvp_event_inc_sof(cif_dev);
	9456	+ }
	9457	+}
	9458	+
	9459	+static int rkcif_g_toisp_ch(unsigned int intstat_glb, int index)
	9460	+{
	9461	+ if (intstat_glb & TOISP_END_CH0(index))
	9462	+ return RKCIF_TOISP_CH0;
	9463	+ if (intstat_glb & TOISP_END_CH1(index))
	9464	+ return RKCIF_TOISP_CH1;
	9465	+ if (intstat_glb & TOISP_END_CH2(index))
	9466	+ return RKCIF_TOISP_CH2;
	9467	+
	9468	+ return -EINVAL;
	9469	+}
	9470	+
	9471	+static int rkcif_g_toisp_fs(unsigned int intstat_glb, int index)
	9472	+{
	9473	+ if (intstat_glb & TOISP_FS_CH0(index))
	9474	+ return RKCIF_TOISP_CH0;
	9475	+ if (intstat_glb & TOISP_FS_CH1(index))
	9476	+ return RKCIF_TOISP_CH1;
	9477	+ if (intstat_glb & TOISP_FS_CH2(index))
	9478	+ return RKCIF_TOISP_CH2;
	9479	+
	9480	+ return -EINVAL;
	9481	+}
	9482	+
	9483	+static void rkcif_toisp_check_stop_status(struct sditf_priv *priv,
	9484	+ unsigned int intstat_glb,
	9485	+ int index)
	9486	+{
	9487	+ int ch = 0;
	9488	+ struct rkcif_stream *stream;
	9489	+ int src_id = 0;
	9490	+ int i = 0;
	9491	+ u32 val = 0;
	9492	+ u64 cur_time = 0;
	9493	+
	9494	+ for (i = 0; i < TOISP_CH_MAX; i++) {
	9495	+ ch = rkcif_g_toisp_ch(intstat_glb, index);
	9496	+ if (ch >= 0) {
	9497	+ src_id = priv->toisp_inf.ch_info[ch].id;
	9498	+ if (src_id == 24)
	9499	+ stream = &priv->cif_dev->stream[0];
	9500	+ else
	9501	+ stream = &priv->cif_dev->stream[src_id % 4];
	9502	+ if (stream->stopping) {
	9503	+ v4l2_dbg(3, rkcif_debug, &priv->cif_dev->v4l2_dev,
	9504	+ "stream[%d] stop\n",
	9505	+ stream->id);
	9506	+ rkcif_stream_stop(stream);
	9507	+ stream->stopping = false;
	9508	+ wake_up(&stream->wq_stopped);
	9509	+ }
	9510	+
	9511	+ if (stream->cifdev->chip_id >= CHIP_RV1106_CIF)
	9512	+ rkcif_modify_frame_skip_config(stream);
	9513	+ if (stream->cifdev->rdbk_debug &&
	9514	+ stream->frame_idx < 15)
	9515	+ v4l2_info(&priv->cif_dev->v4l2_dev,
	9516	+ "stream[%d] toisp fe %d\n",
	9517	+ stream->id,
	9518	+ stream->frame_idx - 1);
	9519	+
	9520	+ switch (ch) {
	9521	+ case RKCIF_TOISP_CH0:
	9522	+ val = TOISP_END_CH0(index);
	9523	+ intstat_glb = intstat_glb & (~val);
	9524	+ break;
	9525	+ case RKCIF_TOISP_CH1:
	9526	+ val = TOISP_END_CH1(index);
	9527	+ intstat_glb = intstat_glb & (~val);
	9528	+ break;
	9529	+ case RKCIF_TOISP_CH2:
	9530	+ val = TOISP_END_CH2(index);
	9531	+ intstat_glb = intstat_glb & (~val);
	9532	+ break;
	9533	+ default:
	9534	+ break;
	9535	+ }
	9536	+ }
	9537	+ ch = rkcif_g_toisp_fs(intstat_glb, index);
	9538	+ if (ch >= 0) {
	9539	+ src_id = priv->toisp_inf.ch_info[ch].id;
	9540	+ if (src_id == 24)
	9541	+ stream = &priv->cif_dev->stream[0];
	9542	+ else
	9543	+ stream = &priv->cif_dev->stream[src_id % 4];
	9544	+ if (stream->id == 0)
	9545	+ rkcif_send_sof(stream->cifdev);
	9546	+ stream->frame_idx++;
	9547	+ cur_time = ktime_get_ns();
	9548	+ stream->readout.readout_time = cur_time - stream->readout.fs_timestamp;
	9549	+ stream->readout.fs_timestamp = cur_time;
	9550	+ if (stream->cifdev->rdbk_debug &&
	9551	+ stream->frame_idx < 15)
	9552	+ v4l2_info(&priv->cif_dev->v4l2_dev,
	9553	+ "stream[%d] toisp sof seq %d\n",
	9554	+ stream->id,
	9555	+ stream->frame_idx - 1);
	9556	+ if (stream->to_en_dma)
	9557	+ rkcif_enable_dma_capture(stream, false);
	9558	+ if (stream->to_en_scale) {
	9559	+ stream->to_en_scale = false;
	9560	+ rkcif_scale_start(stream->scale_vdev);
	9561	+ }
	9562	+ switch (ch) {
	9563	+ case RKCIF_TOISP_CH0:
	9564	+ val = TOISP_FS_CH0(index);
	9565	+ intstat_glb = intstat_glb & (~val);
	9566	+ break;
	9567	+ case RKCIF_TOISP_CH1:
	9568	+ val = TOISP_FS_CH1(index);
	9569	+ intstat_glb = intstat_glb & (~val);
	9570	+ break;
	9571	+ case RKCIF_TOISP_CH2:
	9572	+ val = TOISP_FS_CH2(index);
	9573	+ intstat_glb = intstat_glb & (~val);
	9574	+ break;
	9575	+ default:
	9576	+ break;
	9577	+ }
	9578	+ }
	9579	+ }
	9580	+}
	9581	+
	9582	+void rkcif_irq_handle_toisp(struct rkcif_device *cif_dev, unsigned int intstat_glb)
	9583	+{
	9584	+ int i = 0;
	9585	+ bool to_check = false;
	9586	+ struct sditf_priv *priv = cif_dev->sditf[0];
	9587	+
	9588	+ if (!priv \|\| priv->mode.rdbk_mode != RKISP_VICAP_ONLINE)
	9589	+ return;
	9590	+
	9591	+ for (i = 0; i < 2; i++) {
	9592	+ if (priv->toisp_inf.link_mode == TOISP0 &&
	9593	+ i == 0) {
	9594	+ to_check = true;
	9595	+ } else if (priv->toisp_inf.link_mode == TOISP1 &&
	9596	+ i == 1) {
	9597	+ to_check = true;
	9598	+ } else if (priv->toisp_inf.link_mode == TOISP_UNITE &&
	9599	+ i == 1) {
	9600	+ to_check = true;
	9601	+ }
	9602	+ if (to_check)
	9603	+ rkcif_toisp_check_stop_status(priv, intstat_glb, i);
	9604	+ }
	9605	+}
	9606	+
	9607	+static int rkcif_check_group_sync_state(struct rkcif_device *cif_dev)
	9608	+{
	9609	+ struct rkcif_stream *detect_stream = &cif_dev->stream[0];
	9610	+ struct rkcif_stream *next_stream = NULL;
	9611	+ struct rkcif_hw *hw = cif_dev->hw_dev;
	9612	+ u64 fs_interval = 0;
	9613	+ int i = 0;
	9614	+ int ret = 0;
	9615	+ struct rkcif_multi_sync_config *sync_config;
	9616	+
	9617	+ sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
	9618	+ sync_config->sync_code \|= BIT(cif_dev->csi_host_idx);
	9619	+ if (sync_config->sync_code != sync_config->sync_mask)
	9620	+ return -EINVAL;
	9621	+
	9622	+ v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
	9623	+ "sync code 0x%x, mask 0x%x, update 0x%x, cache 0x%x\n",
	9624	+ sync_config->sync_code,
	9625	+ sync_config->sync_mask,
	9626	+ sync_config->update_code,
	9627	+ sync_config->update_cache);
	9628	+
	9629	+ for (i = 0; i < sync_config->dev_cnt; i++) {
	9630	+ if (sync_config->mode == RKCIF_MASTER_MASTER) {
	9631	+ if (i < sync_config->ext_master.count)
	9632	+ next_stream = &sync_config->ext_master.cif_dev[i]->stream
	9633	+ [0];
	9634	+ else
	9635	+ next_stream = &sync_config->int_master.cif_dev[0]->stream
	9636	+ [0];
	9637	+ } else if (sync_config->mode == RKCIF_MASTER_SLAVE) {
	9638	+ if (i < sync_config->slave.count)
	9639	+ next_stream = &sync_config->slave.cif_dev[i]->stream
	9640	+ [0];
	9641	+ else
	9642	+ next_stream = &sync_config->int_master.cif_dev[0]->stream
	9643	+ [0];
	9644	+ } else {
	9645	+ v4l2_err(&cif_dev->v4l2_dev,
	9646	+ "ERROR: invalid group sync mode\n");
	9647	+ ret = -EINVAL;
	9648	+ break;
	9649	+ }
	9650	+ if (detect_stream == next_stream)
	9651	+ continue;
	9652	+ fs_interval = abs(detect_stream->readout.fs_timestamp - next_stream->readout.fs_timestamp);
	9653	+ if (fs_interval > RKCIF_MAX_INTERVAL_NS) {
	9654	+ ret = -EINVAL;
	9655	+ break;
	9656	+ }
	9657	+ }
	9658	+ return ret;
	9659	+}
	9660	+
	9661	+static void rkcif_deal_sof(struct rkcif_device *cif_dev)
	9662	+{
	9663	+ struct rkcif_stream *detect_stream = &cif_dev->stream[0];
	9664	+ struct rkcif_hw *hw = cif_dev->hw_dev;
	9665	+ struct rkcif_device *tmp_dev = NULL;
	9666	+ unsigned long flags;
	9667	+ int i = 0;
	9668	+ int ret = 0;
	9669	+
	9670	+ if (cif_dev->chip_id < CHIP_RK3588_CIF)
	9671	+ detect_stream->fs_cnt_in_single_frame++;
	9672	+ spin_lock_irqsave(&detect_stream->fps_lock, flags);
	9673	+ detect_stream->readout.fs_timestamp = ktime_get_ns();
	9674	+ spin_unlock_irqrestore(&detect_stream->fps_lock, flags);
	9675	+
	9676	+ if (cif_dev->sync_cfg.type != RKCIF_NOSYNC_MODE) {
	9677	+ struct rkcif_multi_sync_config *sync_config;
	9678	+
	9679	+ sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
	9680	+ ret = rkcif_check_group_sync_state(cif_dev);
	9681	+ if (!ret) {
	9682	+ sync_config->sync_code = 0;
	9683	+ sync_config->frame_idx++;
	9684	+ spin_lock_irqsave(&hw->group_lock, flags);
	9685	+ sync_config->update_cache = sync_config->sync_mask;
	9686	+ if (!sync_config->update_code) {
	9687	+ sync_config->update_code = sync_config->update_cache;
	9688	+ sync_config->update_cache = 0;
	9689	+ }
	9690	+ spin_unlock_irqrestore(&hw->group_lock, flags);
	9691	+ for (i = 0; i < sync_config->dev_cnt; i++) {
	9692	+ if (sync_config->mode == RKCIF_MASTER_MASTER) {
	9693	+ if (i < sync_config->ext_master.count)
	9694	+ tmp_dev = sync_config->ext_master.cif_dev[i];
	9695	+ else
	9696	+ tmp_dev = sync_config->int_master.cif_dev[0];
	9697	+ } else if (sync_config->mode == RKCIF_MASTER_SLAVE) {
	9698	+ if (i < sync_config->slave.count)
	9699	+ tmp_dev = sync_config->slave.cif_dev[i];
	9700	+ else
	9701	+ tmp_dev = sync_config->int_master.cif_dev[0];
	9702	+ } else {
	9703	+ v4l2_err(&cif_dev->v4l2_dev,
	9704	+ "ERROR: invalid group sync mode\n");
	9705	+ }
	9706	+ if (tmp_dev) {
	9707	+ rkcif_send_sof(tmp_dev);
	9708	+ tmp_dev->stream[0].frame_idx = sync_config->frame_idx;
	9709	+ }
	9710	+ }
	9711	+ }
	9712	+ } else {
	9713	+ if (!cif_dev->sditf[0] \|\| cif_dev->sditf[0]->mode.rdbk_mode) {
	9714	+ rkcif_send_sof(cif_dev);
	9715	+ detect_stream->frame_idx++;
	9716	+ }
	9717	+ if (detect_stream->cifdev->rdbk_debug &&
	9718	+ detect_stream->frame_idx < 15 &&
	9719	+ (!cif_dev->sditf[0] \|\| cif_dev->sditf[0]->mode.rdbk_mode))
	9720	+ v4l2_info(&cif_dev->v4l2_dev,
	9721	+ "stream[%d] sof %d %lld\n",
	9722	+ detect_stream->id,
	9723	+ detect_stream->frame_idx - 1,
	9724	+ ktime_get_ns());
	9725	+ }
	9726	+}
	9727	+
	9728	+unsigned int rkcif_irq_global(struct rkcif_device *cif_dev)
	9729	+{
	9730	+ unsigned int intstat_glb = 0;
	9731	+
	9732	+ intstat_glb = rkcif_read_register(cif_dev, CIF_REG_GLB_INTST);
	9733	+ if (intstat_glb)
	9734	+ v4l2_dbg(2, rkcif_debug, &cif_dev->v4l2_dev,
	9735	+ "intstat_glb 0x%x\n",
	9736	+ intstat_glb);
	9737	+ else
	9738	+ return intstat_glb;
	9739	+
	9740	+ if (intstat_glb & SCALE_TOISP_AXI0_ERR) {
	9741	+ v4l2_err(&cif_dev->v4l2_dev,
	9742	+ "ERROR: scale channel, AXI0 bus err intstat_glb:0x%x !!\n",
	9743	+ intstat_glb);
	9744	+ return 0;
	9745	+ }
	9746	+ if (intstat_glb & SCALE_TOISP_AXI1_ERR) {
	9747	+ v4l2_err(&cif_dev->v4l2_dev,
	9748	+ "ERROR: scale channel, AXI1 bus err intstat_glb:0x%x !!\n",
	9749	+ intstat_glb);
	9750	+ return 0;
	9751	+ }
	9752	+ rkcif_irq_handle_scale(cif_dev, intstat_glb);
	9753	+ return intstat_glb;
	9754	+}
	9755	+
	9756	+static bool rkcif_check_buffer_prepare(struct rkcif_stream *stream)
	9757	+{
	9758	+ struct rkcif_device *cif_dev = stream->cifdev;
	9759	+ unsigned long flags;
	9760	+ bool is_update = false;
	9761	+ struct rkcif_multi_sync_config *sync_config;
	9762	+
	9763	+ spin_lock_irqsave(&cif_dev->hw_dev->group_lock, flags);
	9764	+ sync_config = &cif_dev->hw_dev->sync_config[cif_dev->sync_cfg.group];
	9765	+ if (stream->id == 0 &&
	9766	+ sync_config->update_code & BIT(cif_dev->csi_host_idx)) {
	9767	+ is_update = true;
	9768	+ sync_config->update_code &= ~(BIT(cif_dev->csi_host_idx));
	9769	+ if (!sync_config->update_code &&
	9770	+ sync_config->update_cache) {
	9771	+ sync_config->update_code = sync_config->update_cache;
	9772	+ sync_config->update_cache = 0;
	9773	+ }
	9774	+ } else {
	9775	+ if (cif_dev->rdbk_buf[RDBK_L])
	9776	+ is_update = true;
	9777	+ }
	9778	+
	9779	+ spin_unlock_irqrestore(&cif_dev->hw_dev->group_lock, flags);
	9780	+ return is_update;
	9781	+}
	9782	+
	9783	+void rkcif_err_print_work(struct work_struct *work)
	9784	+{
	9785	+ struct rkcif_err_state_work *err_state_work = container_of(work,
	9786	+ struct rkcif_err_state_work,
	9787	+ work);
	9788	+ struct rkcif_device *dev = container_of(err_state_work,
	9789	+ struct rkcif_device,
	9790	+ err_state_work);
	9791	+ u32 err_state = 0;
	9792	+ int intstat = 0;
	9793	+ int lastline = 0;
	9794	+ int lastpixel = 0;
	9795	+ u64 cur_time = 0;
	9796	+ bool is_print = false;
	9797	+
	9798	+ cur_time = ktime_get_ns();
	9799	+ if (err_state_work->last_timestamp == 0) {
	9800	+ is_print = true;
	9801	+ } else {
	9802	+ if (cur_time - err_state_work->last_timestamp > 500000000)
	9803	+ is_print = true;
	9804	+ }
	9805	+ err_state_work->last_timestamp = cur_time;
	9806	+ err_state = err_state_work->err_state;
	9807	+ intstat = err_state_work->intstat;
	9808	+ lastline = err_state_work->lastline;
	9809	+ lastpixel = err_state_work->lastpixel;
	9810	+ if (err_state & RKCIF_ERR_ID0_NOT_BUF && is_print)
	9811	+ v4l2_err(&dev->v4l2_dev,
	9812	+ "stream[0] not active buffer, frame num %d, cnt %llu\n",
	9813	+ dev->stream[0].frame_idx, dev->irq_stats.not_active_buf_cnt[0]);
	9814	+ if (err_state & RKCIF_ERR_ID1_NOT_BUF && is_print)
	9815	+ v4l2_err(&dev->v4l2_dev,
	9816	+ "stream[1] not active buffer, frame num %d, cnt %llu\n",
	9817	+ dev->stream[1].frame_idx, dev->irq_stats.not_active_buf_cnt[1]);
	9818	+ if (err_state & RKCIF_ERR_ID2_NOT_BUF && is_print)
	9819	+ v4l2_err(&dev->v4l2_dev,
	9820	+ "stream[2] not active buffer, frame num %d, cnt %llu\n",
	9821	+ dev->stream[2].frame_idx, dev->irq_stats.not_active_buf_cnt[2]);
	9822	+ if (err_state & RKCIF_ERR_ID3_NOT_BUF && is_print)
	9823	+ v4l2_err(&dev->v4l2_dev,
	9824	+ "stream[3] not active buffer, frame num %d, cnt %llu\n",
	9825	+ dev->stream[3].frame_idx, dev->irq_stats.not_active_buf_cnt[3]);
	9826	+ if (err_state & RKCIF_ERR_ID0_TRIG_SIMULT && is_print)
	9827	+ v4l2_err(&dev->v4l2_dev,
	9828	+ "stream[0], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
	9829	+ dev->stream[0].frame_idx, dev->irq_stats.trig_simult_cnt[0]);
	9830	+ if (err_state & RKCIF_ERR_ID1_TRIG_SIMULT && is_print)
	9831	+ v4l2_err(&dev->v4l2_dev,
	9832	+ "stream[1], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
	9833	+ dev->stream[1].frame_idx, dev->irq_stats.trig_simult_cnt[1]);
	9834	+ if (err_state & RKCIF_ERR_ID2_TRIG_SIMULT && is_print)
	9835	+ v4l2_err(&dev->v4l2_dev,
	9836	+ "stream[2], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
	9837	+ dev->stream[2].frame_idx, dev->irq_stats.trig_simult_cnt[2]);
	9838	+ if (err_state & RKCIF_ERR_ID3_TRIG_SIMULT && is_print)
	9839	+ v4l2_err(&dev->v4l2_dev,
	9840	+ "stream[3], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
	9841	+ dev->stream[3].frame_idx, dev->irq_stats.trig_simult_cnt[3]);
	9842	+ if (err_state & RKCIF_ERR_SIZE)
	9843	+ v4l2_err(&dev->v4l2_dev,
	9844	+ "ERROR: csi size err, intstat:0x%x, lastline:0x%x, cnt %llu\n",
	9845	+ intstat, lastline, dev->irq_stats.csi_size_err_cnt);
	9846	+ if (err_state & RKCIF_ERR_OVERFLOW)
	9847	+ v4l2_err(&dev->v4l2_dev,
	9848	+ "ERROR: csi fifo overflow, intstat:0x%x, lastline:0x%x, cnt %llu\n",
	9849	+ intstat, lastline, dev->irq_stats.csi_overflow_cnt);
	9850	+ if (err_state & RKCIF_ERR_BANDWIDTH_LACK)
	9851	+ v4l2_err(&dev->v4l2_dev,
	9852	+ "ERROR: csi bandwidth lack, intstat:0x%x, lastline:0x%x, cnt %llu\n",
	9853	+ intstat, lastline, dev->irq_stats.csi_bwidth_lack_cnt);
	9854	+ if (err_state & RKCIF_ERR_ID0_MULTI_FS)
	9855	+ v4l2_err(&dev->v4l2_dev,
	9856	+ "ERR: multi fs in oneframe in id0, fs_num:%u\n",
	9857	+ dev->stream[0].fs_cnt_in_single_frame);
	9858	+ if (err_state & RKCIF_ERR_BUS)
	9859	+ v4l2_err(&dev->v4l2_dev, "dvp bus err, intstat 0x%x, last line 0x%x\n",
	9860	+ intstat, lastline);
	9861	+ if (err_state & RKCIF_ERR_PIXEL)
	9862	+ v4l2_err(&dev->v4l2_dev, "dvp pix err, intstat 0x%x, last pixel 0x%x\n",
	9863	+ intstat, lastpixel);
	9864	+ if (err_state & RKCIF_ERR_LINE)
	9865	+ v4l2_err(&dev->v4l2_dev, "dvp line err, intstat 0x%x, last line 0x%x\n",
	9866	+ intstat, lastline);
	9867	+}
	9868	+
	9869	+/* pingpong irq for rk3588 and next */
	9870	+void rkcif_irq_pingpong_v1(struct rkcif_device *cif_dev)
	9871	+{
	9872	+ struct rkcif_stream *stream;
	9873	+ struct rkcif_stream *detect_stream = &cif_dev->stream[0];
	9874	+ struct v4l2_mbus_config *mbus;
	9875	+ unsigned int intstat, i = 0xff;
	9876	+ unsigned long flags;
	9877	+ bool is_update = false;
	9878	+ int ret = 0;
	9879	+
	9880	+ if (!cif_dev->active_sensor)
	9881	+ return;
	9882	+
	9883	+ mbus = &cif_dev->active_sensor->mbus;
	9884	+ if (mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	9885	+ mbus->type == V4L2_MBUS_CSI2_CPHY \|\|
	9886	+ mbus->type == V4L2_MBUS_CCP2) {
	9887	+ int mipi_id;
	9888	+ u32 lastline = 0;
	9889	+
	9890	+ intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
	9891	+ lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1);
	9892	+ cif_dev->err_state_work.lastline = lastline;
	9893	+ cif_dev->err_state_work.intstat = intstat;
	9894	+
	9895	+ /* clear all interrupts that has been triggered */
	9896	+ if (intstat) {
	9897	+ rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
	9898	+ v4l2_dbg(2, rkcif_debug, &cif_dev->v4l2_dev,
	9899	+ "intstat 0x%x\n",
	9900	+ intstat);
	9901	+ } else {
	9902	+ return;
	9903	+ }
	9904	+
	9905	+ if (intstat & CSI_SIZE_ERR) {
	9906	+ cif_dev->irq_stats.csi_size_err_cnt++;
	9907	+ cif_dev->err_state \|= RKCIF_ERR_SIZE;
	9908	+ rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_CTRL, 0x000A0000);
	9909	+ return;
	9910	+ }
	9911	+
	9912	+ if (intstat & CSI_FIFO_OVERFLOW_V1) {
	9913	+ cif_dev->irq_stats.csi_overflow_cnt++;
	9914	+ cif_dev->err_state \|= RKCIF_ERR_OVERFLOW;
	9915	+ return;
	9916	+ }
	9917	+
	9918	+ if (intstat & CSI_BANDWIDTH_LACK_V1) {
	9919	+ cif_dev->irq_stats.csi_bwidth_lack_cnt++;
	9920	+ cif_dev->err_state \|= RKCIF_ERR_BANDWIDTH_LACK;
	9921	+ }
	9922	+
	9923	+ if (intstat & CSI_ALL_ERROR_INTEN_V1) {
	9924	+ cif_dev->irq_stats.all_err_cnt++;
	9925	+ return;
	9926	+ }
	9927	+
	9928	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	9929	+ mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
	9930	+ intstat);
	9931	+ if (mipi_id < 0)
	9932	+ continue;
	9933	+
	9934	+ stream = &cif_dev->stream[mipi_id];
	9935	+ if (!cif_dev->sditf[0] \|\|
	9936	+ cif_dev->sditf[0]->mode.rdbk_mode)
	9937	+ stream->buf_wake_up_cnt++;
	9938	+
	9939	+ if (stream->stopping && (!stream->dma_en)) {
	9940	+ rkcif_stream_stop(stream);
	9941	+ stream->stopping = false;
	9942	+ wake_up(&stream->wq_stopped);
	9943	+ continue;
	9944	+ }
	9945	+
	9946	+ if (stream->state != RKCIF_STATE_STREAMING)
	9947	+ continue;
	9948	+ stream->is_in_vblank = true;
	9949	+ switch (mipi_id) {
	9950	+ case RKCIF_STREAM_MIPI_ID0:
	9951	+ stream->frame_phase = SW_FRM_END_ID0(intstat);
	9952	+ intstat &= ~CSI_FRAME_END_ID0;
	9953	+ break;
	9954	+ case RKCIF_STREAM_MIPI_ID1:
	9955	+ stream->frame_phase = SW_FRM_END_ID1(intstat);
	9956	+ intstat &= ~CSI_FRAME_END_ID1;
	9957	+ break;
	9958	+ case RKCIF_STREAM_MIPI_ID2:
	9959	+ stream->frame_phase = SW_FRM_END_ID2(intstat);
	9960	+ intstat &= ~CSI_FRAME_END_ID2;
	9961	+ break;
	9962	+ case RKCIF_STREAM_MIPI_ID3:
	9963	+ stream->frame_phase = SW_FRM_END_ID3(intstat);
	9964	+ intstat &= ~CSI_FRAME_END_ID3;
	9965	+ break;
	9966	+ }
	9967	+ if (stream->cifdev->rdbk_debug &&
	9968	+ stream->frame_idx < 15 &&
	9969	+ (!cif_dev->sditf[0] \|\| cif_dev->sditf[0]->mode.rdbk_mode))
	9970	+ v4l2_info(&cif_dev->v4l2_dev,
	9971	+ "stream[%d] fe %d, phase %d, %lld\n",
	9972	+ stream->id,
	9973	+ stream->frame_idx - 1,
	9974	+ stream->frame_phase,
	9975	+ ktime_get_ns());
	9976	+
	9977	+ if (stream->crop_dyn_en)
	9978	+ rkcif_dynamic_crop(stream);
	9979	+
	9980	+ if (stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
	9981	+ if (cif_dev->sync_cfg.type == RKCIF_NOSYNC_MODE)
	9982	+ is_update = true;
	9983	+ else
	9984	+ is_update = rkcif_check_buffer_prepare(stream);
	9985	+ if (is_update)
	9986	+ rkcif_update_stream(cif_dev, stream, mipi_id);
	9987	+ } else if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	9988	+ rkcif_update_stream_toisp(cif_dev, stream, mipi_id);
	9989	+ } else if (stream->dma_en & RKCIF_DMAEN_BY_ROCKIT) {
	9990	+ rkcif_update_stream_rockit(cif_dev, stream, mipi_id);
	9991	+ }
	9992	+
	9993	+ if (cif_dev->chip_id >= CHIP_RV1106_CIF)
	9994	+ rkcif_modify_frame_skip_config(stream);
	9995	+ if (stream->is_change_toisp) {
	9996	+ stream->is_change_toisp = false;
	9997	+ if ((cif_dev->hdr.hdr_mode == HDR_X2 && stream->id != 1) \|\|
	9998	+ (cif_dev->hdr.hdr_mode == HDR_X3 && stream->id != 2))
	9999	+ rkcif_release_unnecessary_buf_for_online(stream,
	10000	+ stream->curr_buf_toisp);
	10001	+ else
	10002	+ sditf_change_to_online(cif_dev->sditf[0]);
	10003	+ }
	10004	+
	10005	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	10006	+ if (stream->is_finish_stop_dma) {
	10007	+ wake_up(&stream->wq_stopped);
	10008	+ stream->is_finish_stop_dma = false;
	10009	+ }
	10010	+ if (!(stream->dma_en & RKCIF_DMAEN_BY_ISP) && stream->lack_buf_cnt == 2) {
	10011	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	10012	+ rkcif_stop_dma_capture(stream);
	10013	+ }
	10014	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	10015	+ if (stream->to_en_scale) {
	10016	+ stream->to_en_scale = false;
	10017	+ rkcif_scale_start(stream->scale_vdev);
	10018	+ }
	10019	+ rkcif_detect_wake_up_mode_change(stream);
	10020	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	10021	+ mipi_id == RKCIF_STREAM_MIPI_ID0) {
	10022	+ if ((intstat & (CSI_FRAME1_START_ID0 \| CSI_FRAME0_START_ID0)) == 0 &&
	10023	+ detect_stream->fs_cnt_in_single_frame > 1) {
	10024	+ cif_dev->err_state \|= RKCIF_ERR_ID0_MULTI_FS;
	10025	+ detect_stream->is_fs_fe_not_paired = true;
	10026	+ detect_stream->fs_cnt_in_single_frame = 0;
	10027	+ } else {
	10028	+ detect_stream->fs_cnt_in_single_frame--;
	10029	+ }
	10030	+ }
	10031	+ rkcif_monitor_reset_event(cif_dev);
	10032	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
	10033	+ }
	10034	+
	10035	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	10036	+ if (intstat & CSI_START_INTSTAT(i)) {
	10037	+ stream = &cif_dev->stream[i];
	10038	+ if (i == 0) {
	10039	+ rkcif_deal_sof(cif_dev);
	10040	+ } else {
	10041	+ spin_lock_irqsave(&stream->fps_lock, flags);
	10042	+ stream->readout.fs_timestamp = ktime_get_ns();
	10043	+ stream->frame_idx++;
	10044	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	10045	+ }
	10046	+ stream->is_in_vblank = false;
	10047	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	10048	+ if (stream->stopping && stream->dma_en) {
	10049	+ if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
	10050	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	10051	+ else if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
	10052	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	10053	+ stream->is_stop_capture = true;
	10054	+ }
	10055	+ if (stream->to_stop_dma) {
	10056	+ ret = rkcif_stop_dma_capture(stream);
	10057	+ if (!ret)
	10058	+ stream->is_finish_stop_dma = true;
	10059	+ }
	10060	+ if (stream->to_en_dma)
	10061	+ rkcif_enable_dma_capture(stream, false);
	10062	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	10063	+ }
	10064	+ if (intstat & CSI_LINE_INTSTAT_V1(i)) {
	10065	+ stream = &cif_dev->stream[i];
	10066	+ if (stream->is_line_inten) {
	10067	+ stream->line_int_cnt++;
	10068	+ if (cif_dev->rdbk_debug > 1 &&
	10069	+ stream->frame_idx < 15)
	10070	+ v4l2_info(&cif_dev->v4l2_dev,
	10071	+ "line int %lld\n",
	10072	+ stream->line_int_cnt);
	10073	+ if (cif_dev->sditf[0] && cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO)
	10074	+ rkcif_line_wake_up_rdbk(stream, stream->id);
	10075	+ else
	10076	+ rkcif_line_wake_up(stream, stream->id);
	10077	+ rkcif_modify_line_int(stream, false);
	10078	+ stream->is_line_inten = false;
	10079	+ }
	10080	+ v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
	10081	+ "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
	10082	+ }
	10083	+ }
	10084	+ } else {
	10085	+ struct rkcif_stream *stream;
	10086	+ int ch_id;
	10087	+ int lastline;
	10088	+
	10089	+ intstat = rkcif_read_register(cif_dev, CIF_REG_DVP_INTSTAT);
	10090	+ if (intstat)
	10091	+ rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, intstat);
	10092	+ else
	10093	+ return;
	10094	+ lastline = rkcif_read_register(cif_dev, CIF_REG_DVP_LINE_CNT);
	10095	+ cif_dev->err_state_work.lastline = lastline;
	10096	+ cif_dev->err_state_work.intstat = intstat;
	10097	+ stream = &cif_dev->stream[RKCIF_STREAM_CIF];
	10098	+
	10099	+ if (intstat & DVP_SIZE_ERR) {
	10100	+ cif_dev->irq_stats.dvp_size_err_cnt++;
	10101	+ rkcif_write_register_or(cif_dev, CIF_REG_DVP_CTRL, 0x000A0000);
	10102	+ cif_dev->err_state \|= RKCIF_ERR_SIZE;
	10103	+ }
	10104	+
	10105	+ if (intstat & DVP_FIFO_OVERFLOW) {
	10106	+ cif_dev->irq_stats.dvp_overflow_cnt++;
	10107	+ cif_dev->err_state \|= RKCIF_ERR_OVERFLOW;
	10108	+ }
	10109	+
	10110	+ if (intstat & DVP_BANDWIDTH_LACK) {
	10111	+ cif_dev->irq_stats.dvp_bwidth_lack_cnt++;
	10112	+ cif_dev->err_state \|= RKCIF_ERR_BANDWIDTH_LACK;
	10113	+ }
	10114	+
	10115	+ if (intstat & INTSTAT_ERR_RK3588) {
	10116	+ cif_dev->irq_stats.all_err_cnt++;
	10117	+ }
	10118	+
	10119	+ for (i = 0; i < RKCIF_MAX_STREAM_DVP; i++) {
	10120	+ ch_id = rkcif_dvp_g_ch_id_by_fe(&cif_dev->v4l2_dev, intstat);
	10121	+
	10122	+ if (ch_id < 0)
	10123	+ continue;
	10124	+
	10125	+ stream = &cif_dev->stream[ch_id];
	10126	+ if (!cif_dev->sditf[0] \|\|
	10127	+ cif_dev->sditf[0]->mode.rdbk_mode)
	10128	+ stream->buf_wake_up_cnt++;
	10129	+
	10130	+ if (stream->stopping) {
	10131	+ rkcif_stream_stop(stream);
	10132	+ stream->stopping = false;
	10133	+ wake_up(&stream->wq_stopped);
	10134	+ continue;
	10135	+ }
	10136	+
	10137	+ if (stream->state != RKCIF_STATE_STREAMING)
	10138	+ continue;
	10139	+ stream->is_in_vblank = true;
	10140	+ switch (ch_id) {
	10141	+ case RKCIF_STREAM_MIPI_ID0:
	10142	+ stream->frame_phase = SW_FRM_END_ID0(intstat);
	10143	+ intstat &= ~DVP_ALL_END_ID0;
	10144	+ break;
	10145	+ case RKCIF_STREAM_MIPI_ID1:
	10146	+ stream->frame_phase = SW_FRM_END_ID1(intstat);
	10147	+ intstat &= ~DVP_ALL_END_ID1;
	10148	+ break;
	10149	+ case RKCIF_STREAM_MIPI_ID2:
	10150	+ stream->frame_phase = SW_FRM_END_ID2(intstat);
	10151	+ intstat &= ~DVP_ALL_END_ID2;
	10152	+ break;
	10153	+ case RKCIF_STREAM_MIPI_ID3:
	10154	+ stream->frame_phase = SW_FRM_END_ID3(intstat);
	10155	+ intstat &= ~DVP_ALL_END_ID3;
	10156	+ break;
	10157	+ }
	10158	+ if (stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
	10159	+ if (cif_dev->sync_cfg.type == RKCIF_NOSYNC_MODE)
	10160	+ is_update = true;
	10161	+ else
	10162	+ is_update = rkcif_check_buffer_prepare(stream);
	10163	+ if (is_update)
	10164	+ rkcif_update_stream(cif_dev, stream, ch_id);
	10165	+ } else if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	10166	+ rkcif_update_stream_toisp(cif_dev, stream, ch_id);
	10167	+ } else if (stream->dma_en & RKCIF_DMAEN_BY_ROCKIT) {
	10168	+ rkcif_update_stream_rockit(cif_dev, stream, ch_id);
	10169	+ }
	10170	+
	10171	+ if (stream->to_en_dma)
	10172	+ rkcif_enable_dma_capture(stream, false);
	10173	+ if (stream->to_stop_dma) {
	10174	+ rkcif_stop_dma_capture(stream);
	10175	+ wake_up(&stream->wq_stopped);
	10176	+ }
	10177	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
	10178	+ }
	10179	+
	10180	+ if (intstat & DVP_FRAME0_START_ID0 \|\| intstat & DVP_FRAME1_START_ID0) {
	10181	+ stream->is_in_vblank = false;
	10182	+ rkcif_deal_sof(cif_dev);
	10183	+ }
	10184	+
	10185	+ if (stream->crop_dyn_en)
	10186	+ rkcif_dynamic_crop(stream);
	10187	+ }
	10188	+}
	10189	+
6072	10190	void rkcif_irq_pingpong(struct rkcif_device *cif_dev)
6073	10191	{
6074	10192	struct rkcif_stream *stream;
6075	10193	struct rkcif_stream *detect_stream = &cif_dev->stream[0];
6076	10194	struct v4l2_mbus_config *mbus;
6077		- unsigned int intstat = 0x0, i = 0xff, bak_intstat = 0x0;
	10195	+ unsigned int intstat = 0x0, i = 0xff;
6078	10196	unsigned long flags;
6079	10197	int ret = 0;
6080	10198
..	..	@@ -6082,7 +10200,8 @@
6082	10200	return;
6083	10201
6084	10202	mbus = &cif_dev->active_sensor->mbus;
6085		- if ((mbus->type == V4L2_MBUS_CSI2 \|\|
	10203	+ if ((mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	10204	+ mbus->type == V4L2_MBUS_CSI2_CPHY \|\|
6086	10205	mbus->type == V4L2_MBUS_CCP2) &&
6087	10206	(cif_dev->chip_id == CHIP_RK1808_CIF \|\|
6088	10207	cif_dev->chip_id == CHIP_RV1126_CIF \|\|
..	..	@@ -6092,78 +10211,27 @@
6092	10211
6093	10212	intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
6094	10213	lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1);
	10214	+ cif_dev->err_state_work.lastline = lastline;
	10215	+ cif_dev->err_state_work.intstat = intstat;
6095	10216
6096	10217	/* clear all interrupts that has been triggered */
6097	10218	rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
6098	10219
6099	10220	if (intstat & CSI_FIFO_OVERFLOW) {
6100	10221	cif_dev->irq_stats.csi_overflow_cnt++;
6101		- v4l2_err(&cif_dev->v4l2_dev,
6102		- "ERROR: csi fifo overflow, intstat:0x%x, lastline:%d!!\n",
6103		- intstat, lastline);
6104		- return;
	10222	+ cif_dev->err_state \|= RKCIF_ERR_OVERFLOW;
6105	10223	}
6106	10224
6107	10225	if (intstat & CSI_BANDWIDTH_LACK) {
6108	10226	cif_dev->irq_stats.csi_bwidth_lack_cnt++;
6109		- v4l2_err(&cif_dev->v4l2_dev,
6110		- "ERROR: csi bandwidth lack, intstat:0x%x!!\n",
6111		- intstat);
	10227	+ cif_dev->err_state \|= RKCIF_ERR_BANDWIDTH_LACK;
6112	10228	return;
6113	10229	}
6114	10230
6115	10231	if (intstat & CSI_ALL_ERROR_INTEN) {
6116	10232	cif_dev->irq_stats.all_err_cnt++;
6117		- v4l2_err(&cif_dev->v4l2_dev,
6118		- "ERROR: CSI_ALL_ERROR_INTEN:0x%x!!\n", intstat);
6119	10233	return;
6120	10234	}
6121		-
6122		- if ((intstat & (CSI_FRAME0_START_ID0 \| CSI_FRAME1_START_ID0)) ==
6123		- (CSI_FRAME0_START_ID0 \| CSI_FRAME1_START_ID0)) {
6124		- v4l2_err(&cif_dev->v4l2_dev, "%s:ERR: double fs in one fs int\n",
6125		- __func__);
6126		- }
6127		-
6128		- if (intstat & CSI_FRAME0_START_ID0) {
6129		- if (mbus->type == V4L2_MBUS_CSI2)
6130		- rkcif_csi2_event_inc_sof();
6131		- else if (mbus->type == V4L2_MBUS_CCP2)
6132		- rkcif_lvds_event_inc_sof(cif_dev);
6133		- detect_stream->fs_cnt_in_single_frame++;
6134		- spin_lock_irqsave(&detect_stream->fps_lock, flags);
6135		- detect_stream->readout.fs_timestamp = ktime_get_ns();
6136		- spin_unlock_irqrestore(&detect_stream->fps_lock, flags);
6137		- }
6138		-
6139		- if (intstat & CSI_FRAME1_START_ID0) {
6140		- if (mbus->type == V4L2_MBUS_CSI2)
6141		- rkcif_csi2_event_inc_sof();
6142		- else if (mbus->type == V4L2_MBUS_CCP2)
6143		- rkcif_lvds_event_inc_sof(cif_dev);
6144		- detect_stream->fs_cnt_in_single_frame++;
6145		- spin_lock_irqsave(&detect_stream->fps_lock, flags);
6146		- detect_stream->readout.fs_timestamp = ktime_get_ns();
6147		- spin_unlock_irqrestore(&detect_stream->fps_lock, flags);
6148		- }
6149		- for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
6150		- if (intstat & CSI_LINE_INTSTAT(i)) {
6151		- stream = &cif_dev->stream[i];
6152		- if (stream->is_line_inten) {
6153		- stream->line_int_cnt++;
6154		- rkcif_line_wake_up(stream, stream->id);
6155		- rkcif_modify_line_int(stream, false);
6156		- stream->is_line_inten = false;
6157		- }
6158		- v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
6159		- "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
6160		- }
6161		- }
6162		-
6163		- /* if do not reach frame dma end, return irq */
6164		- mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev, intstat);
6165		- if (mipi_id < 0)
6166		- return;
6167	10235
6168	10236	for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
6169	10237	mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
..	..	@@ -6206,22 +10274,44 @@
6206	10274
6207	10275	rkcif_update_stream(cif_dev, stream, mipi_id);
6208	10276	rkcif_detect_wake_up_mode_change(stream);
	10277	+ rkcif_monitor_reset_event(cif_dev);
6209	10278	if (mipi_id == RKCIF_STREAM_MIPI_ID0) {
6210	10279	if ((intstat & (CSI_FRAME1_START_ID0 \| CSI_FRAME0_START_ID0)) == 0 &&
6211	10280	detect_stream->fs_cnt_in_single_frame > 1) {
6212		- v4l2_dbg(2, rkcif_debug, &cif_dev->v4l2_dev,
6213		- "%s ERR: multi fs in oneframe, bak_int:0x%x, fs_num:%u\n",
6214		- __func__,
6215		- bak_intstat,
6216		- detect_stream->fs_cnt_in_single_frame);
	10281	+ cif_dev->err_state \|= RKCIF_ERR_ID0_MULTI_FS;
6217	10282	detect_stream->is_fs_fe_not_paired = true;
6218	10283	detect_stream->fs_cnt_in_single_frame = 0;
6219	10284	} else {
6220	10285	detect_stream->fs_cnt_in_single_frame--;
6221	10286	}
6222	10287	}
	10288	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
6223	10289	}
6224		- cif_dev->irq_stats.all_frm_end_cnt++;
	10290	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	10291	+ if (intstat & CSI_START_INTSTAT(i)) {
	10292	+ stream = &cif_dev->stream[i];
	10293	+ if (i == 0) {
	10294	+ rkcif_deal_sof(cif_dev);
	10295	+ } else {
	10296	+ spin_lock_irqsave(&stream->fps_lock, flags);
	10297	+ stream->readout.fs_timestamp = ktime_get_ns();
	10298	+ stream->frame_idx++;
	10299	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	10300	+ }
	10301	+ stream->is_in_vblank = false;
	10302	+ }
	10303	+ if (intstat & CSI_LINE_INTSTAT(i)) {
	10304	+ stream = &cif_dev->stream[i];
	10305	+ if (stream->is_line_inten) {
	10306	+ stream->line_int_cnt++;
	10307	+ rkcif_line_wake_up(stream, stream->id);
	10308	+ rkcif_modify_line_int(stream, false);
	10309	+ stream->is_line_inten = false;
	10310	+ }
	10311	+ v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
	10312	+ "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
	10313	+ }
	10314	+ }
6225	10315	} else {
6226	10316	u32 lastline, lastpix, ctl;
6227	10317	u32 cif_frmst, frmid, int_en;
..	..	@@ -6235,49 +10325,36 @@
6235	10325	lastpix = rkcif_read_register(cif_dev, CIF_REG_DVP_LAST_PIX);
6236	10326	lastpix = CIF_FETCH_Y_LAST_LINE(lastpix);
6237	10327	ctl = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
	10328	+ cif_dev->err_state_work.lastline = lastline;
	10329	+ cif_dev->err_state_work.lastpixel = lastpix;
	10330	+ cif_dev->err_state_work.intstat = intstat;
6238	10331
6239	10332	rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, intstat);
6240	10333
6241	10334	stream = &cif_dev->stream[RKCIF_STREAM_CIF];
6242	10335
6243		- if ((intstat & LINE_INT_END) && !(intstat & FRAME_END) &&
6244		- (cif_dev->dvp_sof_in_oneframe == 0)) {
6245		- if ((intstat & (PRE_INF_FRAME_END \| PST_INF_FRAME_END)) == 0x0) {
6246		- if ((intstat & INTSTAT_ERR) == 0x0) {
6247		- rkcif_dvp_event_inc_sof(cif_dev);
6248		- int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
6249		- int_en &= ~LINE_INT_EN;
6250		- rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);
6251		- cif_dev->dvp_sof_in_oneframe = 1;
6252		- }
6253		- }
6254		- }
6255		-
6256	10336	if (intstat & BUS_ERR) {
6257	10337	cif_dev->irq_stats.dvp_bus_err_cnt++;
6258		- v4l2_info(&cif_dev->v4l2_dev, "dvp bus err\n");
	10338	+ cif_dev->err_state \|= RKCIF_ERR_BUS;
6259	10339	}
6260	10340
6261	10341	if (intstat & DVP_ALL_OVERFLOW) {
6262	10342	cif_dev->irq_stats.dvp_overflow_cnt++;
6263		- v4l2_info(&cif_dev->v4l2_dev, "dvp overflow err\n");
	10343	+ cif_dev->err_state \|= RKCIF_ERR_OVERFLOW;
6264	10344	}
6265	10345
6266	10346	if (intstat & LINE_ERR) {
6267	10347	cif_dev->irq_stats.dvp_line_err_cnt++;
6268		- v4l2_info(&cif_dev->v4l2_dev, "dvp line err\n");
	10348	+ cif_dev->err_state \|= RKCIF_ERR_LINE;
6269	10349	}
6270	10350
6271	10351	if (intstat & PIX_ERR) {
6272	10352	cif_dev->irq_stats.dvp_pix_err_cnt++;
6273		- v4l2_info(&cif_dev->v4l2_dev, "dvp pix err\n");
	10353	+ cif_dev->err_state \|= RKCIF_ERR_PIXEL;
6274	10354	}
6275	10355
6276		- if (intstat & INTSTAT_ERR) {
	10356	+ if (intstat & INTSTAT_ERR)
6277	10357	cif_dev->irq_stats.all_err_cnt++;
6278		- v4l2_err(&cif_dev->v4l2_dev,
6279		- "ERROR: DVP_ALL_ERROR_INTEN:0x%x!!\n", intstat);
6280		- }
6281	10358
6282	10359	/* There are two irqs enabled:
6283	10360	* - PST_INF_FRAME_END: cif FIFO is ready,
..	..	@@ -6298,7 +10375,7 @@
6298	10375	stream = &cif_dev->stream[RKCIF_STREAM_CIF];
6299	10376
6300	10377	if ((intstat & FRAME_END)) {
6301		- struct vb2_v4l2_buffer *vb_done = NULL;
	10378	+ struct rkcif_buffer *active_buf = NULL;
6302	10379
6303	10380	int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
6304	10381	int_en \|= LINE_INT_EN;
..	..	@@ -6318,7 +10395,7 @@
6318	10395	v4l2_info(&cif_dev->v4l2_dev, "frmid:%d, frmstat:0x%x\n",
6319	10396	frmid, cif_frmst);
6320	10397	rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
6321		- cif_frmst & 0x3);
	10398	+ FRAME_STAT_CLS);
6322	10399	}
6323	10400
6324	10401	if (lastline != stream->pixm.height \|\|
..	..	@@ -6334,11 +10411,11 @@
6334	10411
6335	10412	if (cif_frmst & CIF_F0_READY) {
6336	10413	if (stream->curr_buf)
6337		- vb_done = &stream->curr_buf->vb;
	10414	+ active_buf = stream->curr_buf;
6338	10415	stream->frame_phase = CIF_CSI_FRAME0_READY;
6339	10416	} else if (cif_frmst & CIF_F1_READY) {
6340	10417	if (stream->next_buf)
6341		- vb_done = &stream->next_buf->vb;
	10418	+ active_buf = stream->next_buf;
6342	10419	stream->frame_phase = CIF_CSI_FRAME1_READY;
6343	10420	}
6344	10421
..	..	@@ -6352,12 +10429,12 @@
6352	10429	ret = rkcif_assign_new_buffer_oneframe(stream,
6353	10430	RKCIF_YUV_ADDR_STATE_UPDATE);
6354	10431
6355		- if (vb_done && (!ret)) {
6356		- vb_done->sequence = stream->frame_idx;
6357		- rkcif_vb_done_oneframe(stream, vb_done);
	10432	+ if (active_buf && (!ret)) {
	10433	+ active_buf->vb.sequence = stream->frame_idx;
	10434	+ rkcif_vb_done_tasklet(stream, active_buf);
6358	10435	}
6359	10436	stream->frame_idx++;
6360		- cif_dev->irq_stats.all_frm_end_cnt++;
	10437	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
6361	10438	}
6362	10439	} else {
6363	10440	for (i = 0; i < RKCIF_MAX_STREAM_DVP; i++) {
..	..	@@ -6406,10 +10483,23 @@
6406	10483	v4l2_info(&cif_dev->v4l2_dev, "frmid:%d, frmstat:0x%x\n",
6407	10484	frmid, cif_frmst);
6408	10485	rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
6409		- cif_frmst & 0xffff);
	10486	+ FRAME_STAT_CLS);
6410	10487	}
6411	10488	rkcif_update_stream(cif_dev, stream, ch_id);
6412		- cif_dev->irq_stats.all_frm_end_cnt++;
	10489	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
	10490	+ }
	10491	+ }
	10492	+
	10493	+ if ((intstat & LINE_INT_END) && !(intstat & FRAME_END) &&
	10494	+ (cif_dev->dvp_sof_in_oneframe == 0)) {
	10495	+ if ((intstat & (PRE_INF_FRAME_END \| PST_INF_FRAME_END)) == 0x0) {
	10496	+ if ((intstat & INTSTAT_ERR) == 0x0) {
	10497	+ rkcif_deal_sof(cif_dev);
	10498	+ int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
	10499	+ int_en &= ~LINE_INT_EN;
	10500	+ rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);
	10501	+ cif_dev->dvp_sof_in_oneframe = 1;
	10502	+ }
6413	10503	}
6414	10504	}
6415	10505
..	..	@@ -6431,6 +10521,8 @@
6431	10521
6432	10522	intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
6433	10523	lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1);
	10524	+ cif_dev->err_state_work.lastline = lastline;
	10525	+ cif_dev->err_state_work.intstat = intstat;
6434	10526
6435	10527	/* clear all interrupts that has been triggered */
6436	10528	rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
..	..	@@ -6454,18 +10546,6 @@
6454	10546	"ERROR: cif lite lvds all err:0x%x!!\n", intstat);
6455	10547	return;
6456	10548	}
6457		-
6458		- if (intstat & CSI_FRAME0_START_ID0)
6459		- rkcif_lvds_event_inc_sof(cif_dev);
6460		-
6461		-
6462		- if (intstat & CSI_FRAME1_START_ID0)
6463		- rkcif_lvds_event_inc_sof(cif_dev);
6464		-
6465		- /* if do not reach frame dma end, return irq */
6466		- mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev, intstat);
6467		- if (mipi_id < 0)
6468		- return;
6469	10549
6470	10550	for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
6471	10551	mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
..	..	@@ -6505,7 +10585,31 @@
6505	10585	}
6506	10586
6507	10587	rkcif_update_stream(cif_dev, stream, mipi_id);
	10588	+ rkcif_monitor_reset_event(cif_dev);
	10589	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
6508	10590	}
6509		- cif_dev->irq_stats.all_frm_end_cnt++;
	10591	+
	10592	+ if (intstat & CSI_FRAME0_START_ID0)
	10593	+ rkcif_lvds_event_inc_sof(cif_dev);
	10594	+
	10595	+ if (intstat & CSI_FRAME1_START_ID0)
	10596	+ rkcif_lvds_event_inc_sof(cif_dev);
6510	10597	}
6511	10598	}
	10599	+
	10600	+int rkcif_sditf_disconnect(struct video_device *vdev)
	10601	+{
	10602	+ struct rkcif_vdev_node *vnode = vdev_to_node(vdev);
	10603	+ struct rkcif_stream *stream = to_rkcif_stream(vnode);
	10604	+ struct rkcif_device *cifdev = stream->cifdev;
	10605	+ struct media_link *link;
	10606	+ int ret;
	10607	+
	10608	+ link = list_first_entry(&cifdev->sditf[0]->sd.entity.links, struct media_link, list);
	10609	+ ret = media_entity_setup_link(link, 0);
	10610	+ if (ret)
	10611	+ dev_err(cifdev->dev, "failed to disable link of sditf with isp");
	10612	+
	10613	+ return ret;
	10614	+}
	10615	+EXPORT_SYMBOL(rkcif_sditf_disconnect);