add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/gpu/drm/radeon/radeon_gem.c
..
..
@@ -25,8 +25,14 @@
25
25
  *          Alex Deucher
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26
  *          Jerome Glisse
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27
  */
28
-#include <drm/drmP.h>
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+
29
+#include <linux/pci.h>
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+
31
+#include <drm/drm_debugfs.h>
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+#include <drm/drm_device.h>
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+#include <drm/drm_file.h>
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34
 #include <drm/radeon_drm.h>
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+
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36
 #include "radeon.h"
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37
 
32
38
 void radeon_gem_object_free(struct drm_gem_object *gobj)
..
..
@@ -78,7 +84,7 @@
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84
 		}
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 		return r;
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86
 	}
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-	*obj = &robj->gem_base;
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+	*obj = &robj->tbo.base;
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 	robj->pid = task_pid_nr(current);
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89
 
84
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 	mutex_lock(&rdev->gem.mutex);
..
..
@@ -109,7 +115,7 @@
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115
 	}
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116
 	if (domain == RADEON_GEM_DOMAIN_CPU) {
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 		/* Asking for cpu access wait for object idle */
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-		r = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ);
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+		r = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, 30 * HZ);
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119
 		if (!r)
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 			r = -EBUSY;
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121
 
..
..
@@ -218,9 +224,9 @@
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 {
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 	struct radeon_device *rdev = dev->dev_private;
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 	struct drm_radeon_gem_info *args = data;
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-	struct ttm_mem_type_manager *man;
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+	struct ttm_resource_manager *man;
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228
 
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-	man = &rdev->mman.bdev.man[TTM_PL_VRAM];
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+	man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
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230
 
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231
 	args->vram_size = (u64)man->size << PAGE_SHIFT;
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232
 	args->vram_visible = rdev->mc.visible_vram_size;
..
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@@ -269,7 +275,7 @@
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 	}
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 	r = drm_gem_handle_create(filp, gobj, &handle);
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 	/* drop reference from allocate - handle holds it now */
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-	drm_gem_object_put_unlocked(gobj);
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+	drm_gem_object_put(gobj);
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 	if (r) {
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 		up_read(&rdev->exclusive_lock);
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 		r = radeon_gem_handle_lockup(rdev, r);
..
..
@@ -325,7 +331,7 @@
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 		goto handle_lockup;
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332
 
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 	bo = gem_to_radeon_bo(gobj);
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-	r = radeon_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
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+	r = radeon_ttm_tt_set_userptr(rdev, bo->tbo.ttm, args->addr, args->flags);
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 	if (r)
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336
 		goto release_object;
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337
 
..
..
@@ -336,24 +342,24 @@
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 	}
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343
 
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 	if (args->flags & RADEON_GEM_USERPTR_VALIDATE) {
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-		down_read(&current->mm->mmap_sem);
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+		mmap_read_lock(current->mm);
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 		r = radeon_bo_reserve(bo, true);
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 		if (r) {
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-			up_read(&current->mm->mmap_sem);
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+			mmap_read_unlock(current->mm);
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 			goto release_object;
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350
 		}
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351
 
346
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 		radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_GTT);
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 		r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
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 		radeon_bo_unreserve(bo);
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-		up_read(&current->mm->mmap_sem);
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+		mmap_read_unlock(current->mm);
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356
 		if (r)
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357
 			goto release_object;
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358
 	}
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359
 
354
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 	r = drm_gem_handle_create(filp, gobj, &handle);
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 	/* drop reference from allocate - handle holds it now */
356
-	drm_gem_object_put_unlocked(gobj);
362
+	drm_gem_object_put(gobj);
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363
 	if (r)
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 		goto handle_lockup;
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365
 
..
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@@ -362,7 +368,7 @@
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 	return 0;
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369
 
364
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 release_object:
365
-	drm_gem_object_put_unlocked(gobj);
371
+	drm_gem_object_put(gobj);
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372
 
367
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 handle_lockup:
368
374
 	up_read(&rdev->exclusive_lock);
..
..
@@ -396,7 +402,7 @@
396
402
 
397
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 	r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain);
398
404
 
399
-	drm_gem_object_put_unlocked(gobj);
405
+	drm_gem_object_put(gobj);
400
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 	up_read(&rdev->exclusive_lock);
401
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 	r = radeon_gem_handle_lockup(robj->rdev, r);
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 	return r;
..
..
@@ -414,12 +420,12 @@
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420
 		return -ENOENT;
415
421
 	}
416
422
 	robj = gem_to_radeon_bo(gobj);
417
-	if (radeon_ttm_tt_has_userptr(robj->tbo.ttm)) {
418
-		drm_gem_object_put_unlocked(gobj);
423
+	if (radeon_ttm_tt_has_userptr(robj->rdev, robj->tbo.ttm)) {
424
+		drm_gem_object_put(gobj);
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425
 		return -EPERM;
420
426
 	}
421
427
 	*offset_p = radeon_bo_mmap_offset(robj);
422
-	drm_gem_object_put_unlocked(gobj);
428
+	drm_gem_object_put(gobj);
423
429
 	return 0;
424
430
 }
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431
 
..
..
@@ -446,7 +452,7 @@
446
452
 	}
447
453
 	robj = gem_to_radeon_bo(gobj);
448
454
 
449
-	r = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
455
+	r = dma_resv_test_signaled_rcu(robj->tbo.base.resv, true);
450
456
 	if (r == 0)
451
457
 		r = -EBUSY;
452
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 	else
..
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@@ -454,7 +460,7 @@
454
460
 
455
461
 	cur_placement = READ_ONCE(robj->tbo.mem.mem_type);
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462
 	args->domain = radeon_mem_type_to_domain(cur_placement);
457
-	drm_gem_object_put_unlocked(gobj);
463
+	drm_gem_object_put(gobj);
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464
 	return r;
459
465
 }
460
466
 
..
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@@ -475,7 +481,7 @@
475
481
 	}
476
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 	robj = gem_to_radeon_bo(gobj);
477
483
 
478
-	ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ);
484
+	ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, 30 * HZ);
479
485
 	if (ret == 0)
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486
 		r = -EBUSY;
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487
 	else if (ret < 0)
..
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@@ -486,7 +492,7 @@
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 	if (rdev->asic->mmio_hdp_flush &&
487
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 	    radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM)
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 		robj->rdev->asic->mmio_hdp_flush(rdev);
489
-	drm_gem_object_put_unlocked(gobj);
495
+	drm_gem_object_put(gobj);
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 	r = radeon_gem_handle_lockup(rdev, r);
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 	return r;
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498
 }
..
..
@@ -505,7 +511,7 @@
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511
 		return -ENOENT;
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512
 	robj = gem_to_radeon_bo(gobj);
507
513
 	r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch);
508
-	drm_gem_object_put_unlocked(gobj);
514
+	drm_gem_object_put(gobj);
509
515
 	return r;
510
516
 }
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517
 
..
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@@ -528,7 +534,7 @@
528
534
 	radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch);
529
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 	radeon_bo_unreserve(rbo);
530
536
 out:
531
-	drm_gem_object_put_unlocked(gobj);
537
+	drm_gem_object_put(gobj);
532
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 	return r;
533
539
 }
534
540
 
..
..
@@ -554,7 +560,7 @@
554
560
 	INIT_LIST_HEAD(&list);
555
561
 
556
562
 	tv.bo = &bo_va->bo->tbo;
557
-	tv.shared = true;
563
+	tv.num_shared = 1;
558
564
 	list_add(&tv.head, &list);
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565
 
560
566
 	vm_bos = radeon_vm_get_bos(rdev, bo_va->vm, &list);
..
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@@ -662,14 +668,14 @@
662
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 	r = radeon_bo_reserve(rbo, false);
663
669
 	if (r) {
664
670
 		args->operation = RADEON_VA_RESULT_ERROR;
665
-		drm_gem_object_put_unlocked(gobj);
671
+		drm_gem_object_put(gobj);
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672
 		return r;
667
673
 	}
668
674
 	bo_va = radeon_vm_bo_find(&fpriv->vm, rbo);
669
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 	if (!bo_va) {
670
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 		args->operation = RADEON_VA_RESULT_ERROR;
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 		radeon_bo_unreserve(rbo);
672
-		drm_gem_object_put_unlocked(gobj);
678
+		drm_gem_object_put(gobj);
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 		return -ENOENT;
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 	}
675
681
 
..
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@@ -696,7 +702,7 @@
696
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 		args->operation = RADEON_VA_RESULT_ERROR;
697
703
 	}
698
704
 out:
699
-	drm_gem_object_put_unlocked(gobj);
705
+	drm_gem_object_put(gobj);
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706
 	return r;
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707
 }
702
708
 
..
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@@ -715,7 +721,7 @@
715
721
 	robj = gem_to_radeon_bo(gobj);
716
722
 
717
723
 	r = -EPERM;
718
-	if (radeon_ttm_tt_has_userptr(robj->tbo.ttm))
724
+	if (radeon_ttm_tt_has_userptr(robj->rdev, robj->tbo.ttm))
719
725
 		goto out;
720
726
 
721
727
 	r = radeon_bo_reserve(robj, false);
..
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@@ -737,7 +743,7 @@
737
743
 
738
744
 	radeon_bo_unreserve(robj);
739
745
 out:
740
-	drm_gem_object_put_unlocked(gobj);
746
+	drm_gem_object_put(gobj);
741
747
 	return r;
742
748
 }
743
749
 
..
..
@@ -763,7 +769,7 @@
763
769
 
764
770
 	r = drm_gem_handle_create(file_priv, gobj, &handle);
765
771
 	/* drop reference from allocate - handle holds it now */
766
-	drm_gem_object_put_unlocked(gobj);
772
+	drm_gem_object_put(gobj);
767
773
 	if (r) {
768
774
 		return r;
769
775
 	}