add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/gpu/drm/msm/dsi/dsi.xml.h
..
..
@@ -8,19 +8,19 @@
8
8
 git clone https://github.com/freedreno/envytools.git
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9
 
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10
 The rules-ng-ng source files this header was generated from are:
11
-- /home/robclark/src/envytools/rnndb/msm.xml                 (    676 bytes, from 2018-07-03 19:37:13)
12
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml (   1572 bytes, from 2018-07-03 19:37:13)
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-- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2018-07-03 19:37:13)
14
-- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml      (   2849 bytes, from 2018-07-03 19:37:13)
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-- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml            (  37411 bytes, from 2018-07-03 19:37:13)
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-- /home/robclark/src/envytools/rnndb/dsi/dsi.xml             (  37239 bytes, from 2018-07-03 19:37:13)
17
-- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml            (    602 bytes, from 2018-07-03 19:37:13)
18
-- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2018-07-03 19:37:13)
19
-- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2018-07-03 19:37:13)
20
-- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml           (  41799 bytes, from 2018-07-03 19:37:13)
21
-- /home/robclark/src/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2018-07-03 19:37:13)
11
+- /home/robclark/src/envytools/rnndb/msm.xml                 (    676 bytes, from 2020-07-23 21:58:14)
12
+- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml (   1572 bytes, from 2020-07-23 21:58:14)
13
+- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2020-07-23 21:58:14)
14
+- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml      (   2849 bytes, from 2020-07-23 21:58:14)
15
+- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml            (  37411 bytes, from 2020-07-23 21:58:14)
16
+- /home/robclark/src/envytools/rnndb/dsi/dsi.xml             (  42301 bytes, from 2020-07-23 21:58:14)
17
+- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml            (    602 bytes, from 2020-07-23 21:58:14)
18
+- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2020-07-23 21:58:14)
19
+- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2020-07-23 21:58:14)
20
+- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml           (  41874 bytes, from 2020-07-23 21:58:14)
21
+- /home/robclark/src/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2020-07-23 21:58:14)
22
22
 
23
-Copyright (C) 2013-2018 by the following authors:
23
+Copyright (C) 2013-2020 by the following authors:
24
24
 - Rob Clark <robdclark@gmail.com> (robclark)
25
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 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
26
 
..
..
@@ -148,7 +148,31 @@
148
148
 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION			0x80000000
149
149
 
150
150
 #define REG_DSI_FIFO_STATUS					0x00000008
151
+#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW			0x00000001
152
+#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW		0x00000008
151
153
 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW			0x00000080
154
+#define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH		0x00000100
155
+#define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH		0x00000200
156
+#define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW			0x00000400
157
+#define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY			0x00001000
158
+#define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL			0x00002000
159
+#define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW			0x00004000
160
+#define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY			0x00010000
161
+#define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL			0x00020000
162
+#define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW			0x00040000
163
+#define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW			0x00080000
164
+#define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY			0x00100000
165
+#define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL			0x00200000
166
+#define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW			0x00400000
167
+#define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW			0x00800000
168
+#define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY			0x01000000
169
+#define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL			0x02000000
170
+#define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW			0x04000000
171
+#define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW			0x08000000
172
+#define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY			0x10000000
173
+#define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL			0x20000000
174
+#define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW			0x40000000
175
+#define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW			0x80000000
152
176
 
153
177
 #define REG_DSI_VID_CFG0					0x0000000c
154
178
 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK				0x00000003
..
..
@@ -318,38 +342,72 @@
318
342
 
319
343
 #define REG_DSI_DMA_LEN						0x00000048
320
344
 
321
-#define REG_DSI_CMD_MDP_STREAM_CTRL				0x00000054
322
-#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK			0x0000003f
323
-#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT		0
324
-static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val)
345
+#define REG_DSI_CMD_MDP_STREAM0_CTRL				0x00000054
346
+#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK		0x0000003f
347
+#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT		0
348
+static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val)
325
349
 {
326
-	return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK;
350
+	return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK;
327
351
 }
328
-#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK		0x00000300
329
-#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT		8
330
-static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val)
352
+#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK		0x00000300
353
+#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT		8
354
+static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val)
331
355
 {
332
-	return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK;
356
+	return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK;
333
357
 }
334
-#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK		0xffff0000
335
-#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT		16
336
-static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val)
358
+#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK		0xffff0000
359
+#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT		16
360
+static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val)
337
361
 {
338
-	return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK;
362
+	return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK;
339
363
 }
340
364
 
341
-#define REG_DSI_CMD_MDP_STREAM_TOTAL				0x00000058
342
-#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK			0x00000fff
343
-#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT			0
344
-static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val)
365
+#define REG_DSI_CMD_MDP_STREAM0_TOTAL				0x00000058
366
+#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK			0x00000fff
367
+#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT		0
368
+static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val)
345
369
 {
346
-	return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK;
370
+	return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK;
347
371
 }
348
-#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK			0x0fff0000
349
-#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT			16
350
-static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val)
372
+#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK			0x0fff0000
373
+#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT		16
374
+static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val)
351
375
 {
352
-	return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK;
376
+	return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK;
377
+}
378
+
379
+#define REG_DSI_CMD_MDP_STREAM1_CTRL				0x0000005c
380
+#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK		0x0000003f
381
+#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT		0
382
+static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val)
383
+{
384
+	return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK;
385
+}
386
+#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK		0x00000300
387
+#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT		8
388
+static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val)
389
+{
390
+	return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK;
391
+}
392
+#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK		0xffff0000
393
+#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT		16
394
+static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val)
395
+{
396
+	return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK;
397
+}
398
+
399
+#define REG_DSI_CMD_MDP_STREAM1_TOTAL				0x00000060
400
+#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK			0x0000ffff
401
+#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT		0
402
+static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val)
403
+{
404
+	return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK;
405
+}
406
+#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK			0xffff0000
407
+#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT		16
408
+static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val)
409
+{
410
+	return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK;
353
411
 }
354
412
 
355
413
 #define REG_DSI_ACK_ERR_STATUS					0x00000064
..
..
@@ -389,6 +447,35 @@
389
447
 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0		0x00001000
390
448
 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1		0x00010000
391
449
 
450
+#define REG_DSI_LP_TIMER_CTRL					0x000000b4
451
+#define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK			0x0000ffff
452
+#define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT			0
453
+static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val)
454
+{
455
+	return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK;
456
+}
457
+#define DSI_LP_TIMER_CTRL_BTA_TO__MASK				0xffff0000
458
+#define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT				16
459
+static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val)
460
+{
461
+	return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK;
462
+}
463
+
464
+#define REG_DSI_HS_TIMER_CTRL					0x000000b8
465
+#define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK			0x0000ffff
466
+#define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT			0
467
+static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val)
468
+{
469
+	return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK;
470
+}
471
+#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK		0x000f0000
472
+#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT		16
473
+static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val)
474
+{
475
+	return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK;
476
+}
477
+#define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN			0x10000000
478
+
392
479
 #define REG_DSI_TIMEOUT_STATUS					0x000000bc
393
480
 
394
481
 #define REG_DSI_CLKOUT_TIMING_CTRL				0x000000c0
..
..
@@ -408,6 +495,19 @@
408
495
 #define REG_DSI_EOT_PACKET_CTRL					0x000000c8
409
496
 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND			0x00000001
410
497
 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE			0x00000010
498
+
499
+#define REG_DSI_LANE_STATUS					0x000000a4
500
+#define DSI_LANE_STATUS_DLN0_STOPSTATE				0x00000001
501
+#define DSI_LANE_STATUS_DLN1_STOPSTATE				0x00000002
502
+#define DSI_LANE_STATUS_DLN2_STOPSTATE				0x00000004
503
+#define DSI_LANE_STATUS_DLN3_STOPSTATE				0x00000008
504
+#define DSI_LANE_STATUS_CLKLN_STOPSTATE				0x00000010
505
+#define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT			0x00000100
506
+#define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT			0x00000200
507
+#define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT			0x00000400
508
+#define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT			0x00000800
509
+#define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT			0x00001000
510
+#define DSI_LANE_STATUS_DLN0_DIRECTION				0x00010000
411
511
 
412
512
 #define REG_DSI_LANE_CTRL					0x000000a8
413
513
 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST			0x10000000
..
..
@@ -436,6 +536,21 @@
436
536
 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK			0x00000200
437
537
 
438
538
 #define REG_DSI_CLK_STATUS					0x0000011c
539
+#define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE			0x00000001
540
+#define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE			0x00000002
541
+#define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE			0x00000004
542
+#define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE			0x00000008
543
+#define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE			0x00000010
544
+#define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE			0x00000020
545
+#define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE			0x00000040
546
+#define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE			0x00000080
547
+#define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE			0x00000100
548
+#define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE			0x00000200
549
+#define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE			0x00000400
550
+#define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE			0x00001000
551
+#define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE			0x00002000
552
+#define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE			0x00004000
553
+#define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT			0x00008000
439
554
 #define DSI_CLK_STATUS_PLL_UNLOCKED				0x00010000
440
555
 
441
556
 #define REG_DSI_PHY_RESET					0x00000128
..
..
@@ -443,6 +558,51 @@
443
558
 
444
559
 #define REG_DSI_T_CLK_PRE_EXTEND				0x0000017c
445
560
 #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK			0x00000001
561
+
562
+#define REG_DSI_CMD_MODE_MDP_CTRL2				0x000001b4
563
+#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK		0x0000000f
564
+#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT		0
565
+static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val)
566
+{
567
+	return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK;
568
+}
569
+#define DSI_CMD_MODE_MDP_CTRL2_R_SEL				0x00000010
570
+#define DSI_CMD_MODE_MDP_CTRL2_G_SEL				0x00000020
571
+#define DSI_CMD_MODE_MDP_CTRL2_B_SEL				0x00000040
572
+#define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP		0x00000080
573
+#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK			0x00000700
574
+#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT			8
575
+static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val)
576
+{
577
+	return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK;
578
+}
579
+#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK		0x00007000
580
+#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT		12
581
+static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val)
582
+{
583
+	return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK;
584
+}
585
+#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE			0x00010000
586
+
587
+#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL			0x000001b8
588
+#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK		0x0000003f
589
+#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT		0
590
+static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val)
591
+{
592
+	return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK;
593
+}
594
+#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK	0x00000300
595
+#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT	8
596
+static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val)
597
+{
598
+	return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK;
599
+}
600
+#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK		0xffff0000
601
+#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT		16
602
+static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val)
603
+{
604
+	return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK;
605
+}
446
606
 
447
607
 #define REG_DSI_RDBK_DATA_CTRL					0x000001d0
448
608
 #define DSI_RDBK_DATA_CTRL_COUNT__MASK				0x00ff0000
..
..
@@ -1726,5 +1886,428 @@
1726
1886
 
1727
1887
 #define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE			0x000001a0
1728
1888
 
1889
+#define REG_DSI_7nm_PHY_CMN_REVISION_ID0			0x00000000
1890
+
1891
+#define REG_DSI_7nm_PHY_CMN_REVISION_ID1			0x00000004
1892
+
1893
+#define REG_DSI_7nm_PHY_CMN_REVISION_ID2			0x00000008
1894
+
1895
+#define REG_DSI_7nm_PHY_CMN_REVISION_ID3			0x0000000c
1896
+
1897
+#define REG_DSI_7nm_PHY_CMN_CLK_CFG0				0x00000010
1898
+
1899
+#define REG_DSI_7nm_PHY_CMN_CLK_CFG1				0x00000014
1900
+
1901
+#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL				0x00000018
1902
+
1903
+#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL				0x0000001c
1904
+
1905
+#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0				0x00000020
1906
+
1907
+#define REG_DSI_7nm_PHY_CMN_CTRL_0				0x00000024
1908
+
1909
+#define REG_DSI_7nm_PHY_CMN_CTRL_1				0x00000028
1910
+
1911
+#define REG_DSI_7nm_PHY_CMN_CTRL_2				0x0000002c
1912
+
1913
+#define REG_DSI_7nm_PHY_CMN_CTRL_3				0x00000030
1914
+
1915
+#define REG_DSI_7nm_PHY_CMN_LANE_CFG0				0x00000034
1916
+
1917
+#define REG_DSI_7nm_PHY_CMN_LANE_CFG1				0x00000038
1918
+
1919
+#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL				0x0000003c
1920
+
1921
+#define REG_DSI_7nm_PHY_CMN_DPHY_SOT				0x00000040
1922
+
1923
+#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0				0x000000a0
1924
+
1925
+#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1				0x000000a4
1926
+
1927
+#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2				0x000000a8
1928
+
1929
+#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3				0x000000ac
1930
+
1931
+#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4				0x000000b0
1932
+
1933
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0			0x000000b4
1934
+
1935
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1			0x000000b8
1936
+
1937
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2			0x000000bc
1938
+
1939
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3			0x000000c0
1940
+
1941
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4			0x000000c4
1942
+
1943
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5			0x000000c8
1944
+
1945
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6			0x000000cc
1946
+
1947
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7			0x000000d0
1948
+
1949
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8			0x000000d4
1950
+
1951
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9			0x000000d8
1952
+
1953
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10			0x000000dc
1954
+
1955
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11			0x000000e0
1956
+
1957
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12			0x000000e4
1958
+
1959
+#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13			0x000000e8
1960
+
1961
+#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0		0x000000ec
1962
+
1963
+#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1		0x000000f0
1964
+
1965
+#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL	0x000000f4
1966
+
1967
+#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL	0x000000f8
1968
+
1969
+#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL	0x000000fc
1970
+
1971
+#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL			0x00000100
1972
+
1973
+#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0			0x00000104
1974
+
1975
+#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1			0x00000108
1976
+
1977
+#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL		0x0000010c
1978
+
1979
+#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1				0x00000110
1980
+
1981
+#define REG_DSI_7nm_PHY_CMN_CTRL_4				0x00000114
1982
+
1983
+#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4			0x00000128
1984
+
1985
+#define REG_DSI_7nm_PHY_CMN_PHY_STATUS				0x00000140
1986
+
1987
+#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0			0x00000148
1988
+
1989
+#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1			0x0000014c
1990
+
1991
+static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1992
+
1993
+static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
1994
+
1995
+static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
1996
+
1997
+static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
1998
+
1999
+static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
2000
+
2001
+static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
2002
+
2003
+static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
2004
+
2005
+static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
2006
+
2007
+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE			0x00000000
2008
+
2009
+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO			0x00000004
2010
+
2011
+#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS			0x00000008
2012
+
2013
+#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO		0x0000000c
2014
+
2015
+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE		0x00000010
2016
+
2017
+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR		0x00000014
2018
+
2019
+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE		0x00000018
2020
+
2021
+#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS			0x0000001c
2022
+
2023
+#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER				0x00000020
2024
+
2025
+#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER			0x00000024
2026
+
2027
+#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES			0x00000028
2028
+
2029
+#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES	0x0000002c
2030
+
2031
+#define REG_DSI_7nm_PHY_PLL_CMODE				0x00000030
2032
+
2033
+#define REG_DSI_7nm_PHY_PLL_PSM_CTRL				0x00000034
2034
+
2035
+#define REG_DSI_7nm_PHY_PLL_RSM_CTRL				0x00000038
2036
+
2037
+#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP			0x0000003c
2038
+
2039
+#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL				0x00000040
2040
+
2041
+#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS		0x00000044
2042
+
2043
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW		0x00000048
2044
+
2045
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH		0x0000004c
2046
+
2047
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS		0x00000050
2048
+
2049
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN			0x00000054
2050
+
2051
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX			0x00000058
2052
+
2053
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT			0x0000005c
2054
+
2055
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT			0x00000060
2056
+
2057
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO		0x00000064
2058
+
2059
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE		0x00000068
2060
+
2061
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR		0x0000006c
2062
+
2063
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH			0x00000070
2064
+
2065
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW			0x00000074
2066
+
2067
+#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE		0x00000078
2068
+
2069
+#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH			0x0000007c
2070
+
2071
+#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH		0x00000080
2072
+
2073
+#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW			0x00000084
2074
+
2075
+#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH		0x00000088
2076
+
2077
+#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW			0x0000008c
2078
+
2079
+#define REG_DSI_7nm_PHY_PLL_PFILT				0x00000090
2080
+
2081
+#define REG_DSI_7nm_PHY_PLL_IFILT				0x00000094
2082
+
2083
+#define REG_DSI_7nm_PHY_PLL_PLL_GAIN				0x00000098
2084
+
2085
+#define REG_DSI_7nm_PHY_PLL_ICODE_LOW				0x0000009c
2086
+
2087
+#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH				0x000000a0
2088
+
2089
+#define REG_DSI_7nm_PHY_PLL_LOCKDET				0x000000a4
2090
+
2091
+#define REG_DSI_7nm_PHY_PLL_OUTDIV				0x000000a8
2092
+
2093
+#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL			0x000000ac
2094
+
2095
+#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE		0x000000b0
2096
+
2097
+#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO		0x000000b4
2098
+
2099
+#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE			0x000000b8
2100
+
2101
+#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE			0x000000bc
2102
+
2103
+#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE				0x000000c0
2104
+
2105
+#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS			0x000000c4
2106
+
2107
+#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO		0x000000c8
2108
+
2109
+#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START			0x000000cc
2110
+
2111
+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW			0x000000d0
2112
+
2113
+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID			0x000000d4
2114
+
2115
+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH			0x000000d8
2116
+
2117
+#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES			0x000000dc
2118
+
2119
+#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1			0x000000e0
2120
+
2121
+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1		0x000000e4
2122
+
2123
+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1		0x000000e8
2124
+
2125
+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1		0x000000ec
2126
+
2127
+#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2			0x000000f0
2128
+
2129
+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2		0x000000f4
2130
+
2131
+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2		0x000000f8
2132
+
2133
+#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2		0x000000fc
2134
+
2135
+#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL			0x00000100
2136
+
2137
+#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW			0x00000104
2138
+
2139
+#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH			0x00000108
2140
+
2141
+#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW			0x0000010c
2142
+
2143
+#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH			0x00000110
2144
+
2145
+#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW			0x00000114
2146
+
2147
+#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH			0x00000118
2148
+
2149
+#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL			0x0000011c
2150
+
2151
+#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1			0x00000120
2152
+
2153
+#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1			0x00000124
2154
+
2155
+#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1			0x00000128
2156
+
2157
+#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1			0x0000012c
2158
+
2159
+#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1			0x00000130
2160
+
2161
+#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1			0x00000134
2162
+
2163
+#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2			0x00000138
2164
+
2165
+#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2			0x0000013c
2166
+
2167
+#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2			0x00000140
2168
+
2169
+#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2			0x00000144
2170
+
2171
+#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2			0x00000148
2172
+
2173
+#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2			0x0000014c
2174
+
2175
+#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL				0x00000150
2176
+
2177
+#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE			0x00000154
2178
+
2179
+#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1			0x00000158
2180
+
2181
+#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2			0x0000015c
2182
+
2183
+#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1		0x00000160
2184
+
2185
+#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2		0x00000164
2186
+
2187
+#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1			0x00000168
2188
+
2189
+#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2			0x0000016c
2190
+
2191
+#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1		0x00000170
2192
+
2193
+#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2		0x00000174
2194
+
2195
+#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1	0x00000178
2196
+
2197
+#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2	0x0000017c
2198
+
2199
+#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND		0x00000180
2200
+
2201
+#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID		0x00000184
2202
+
2203
+#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH		0x00000188
2204
+
2205
+#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX		0x0000018c
2206
+
2207
+#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE			0x00000190
2208
+
2209
+#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY			0x00000194
2210
+
2211
+#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY			0x00000198
2212
+
2213
+#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS			0x0000019c
2214
+
2215
+#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES		0x000001a0
2216
+
2217
+#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1			0x000001a4
2218
+
2219
+#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2			0x000001a8
2220
+
2221
+#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1		0x000001ac
2222
+
2223
+#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE			0x000001b0
2224
+
2225
+#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO			0x000001b4
2226
+
2227
+#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL			0x000001b8
2228
+
2229
+#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW		0x000001bc
2230
+
2231
+#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH		0x000001c0
2232
+
2233
+#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW				0x000001c4
2234
+
2235
+#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH				0x000001c8
2236
+
2237
+#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1		0x000001cc
2238
+
2239
+#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG			0x000001d0
2240
+
2241
+#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG				0x000001d4
2242
+
2243
+#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME			0x000001d8
2244
+
2245
+#define REG_DSI_7nm_PHY_PLL_FLL_CODE0				0x000001dc
2246
+
2247
+#define REG_DSI_7nm_PHY_PLL_FLL_CODE1				0x000001e0
2248
+
2249
+#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0				0x000001e4
2250
+
2251
+#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1				0x000001e8
2252
+
2253
+#define REG_DSI_7nm_PHY_PLL_SW_RESET				0x000001ec
2254
+
2255
+#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP				0x000001f0
2256
+
2257
+#define REG_DSI_7nm_PHY_PLL_LOCKTIME0				0x000001f4
2258
+
2259
+#define REG_DSI_7nm_PHY_PLL_LOCKTIME1				0x000001f8
2260
+
2261
+#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL			0x000001fc
2262
+
2263
+#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0				0x00000200
2264
+
2265
+#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1				0x00000204
2266
+
2267
+#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2				0x00000208
2268
+
2269
+#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3				0x0000020c
2270
+
2271
+#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES	0x00000210
2272
+
2273
+#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG				0x00000214
2274
+
2275
+#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS		0x00000218
2276
+
2277
+#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS		0x0000021c
2278
+
2279
+#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS			0x00000220
2280
+
2281
+#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET				0x00000224
2282
+
2283
+#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS		0x00000228
2284
+
2285
+#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS		0x0000022c
2286
+
2287
+#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS			0x00000230
2288
+
2289
+#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS		0x00000234
2290
+
2291
+#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS			0x00000238
2292
+
2293
+#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2			0x0000023c
2294
+
2295
+#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1			0x00000240
2296
+
2297
+#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2			0x00000244
2298
+
2299
+#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1			0x00000248
2300
+
2301
+#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2			0x0000024c
2302
+
2303
+#define REG_DSI_7nm_PHY_PLL_CMODE_1				0x00000250
2304
+
2305
+#define REG_DSI_7nm_PHY_PLL_CMODE_2				0x00000254
2306
+
2307
+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1		0x00000258
2308
+
2309
+#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2		0x0000025c
2310
+
2311
+#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE			0x00000260
1729
2312
 
1730
2313
 #endif /* DSI_XML */