add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/gpu/drm/amd/include/kgd_pp_interface.h
..
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@@ -92,8 +92,12 @@
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 	PP_SCLK,
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 	PP_MCLK,
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 	PP_PCIE,
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+	PP_SOCCLK,
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+	PP_FCLK,
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+	PP_DCEFCLK,
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 	OD_SCLK,
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 	OD_MCLK,
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+	OD_VDDC_CURVE,
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 	OD_RANGE,
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 };
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..
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@@ -105,13 +109,21 @@
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 	AMDGPU_PP_SENSOR_UVD_DCLK,
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 	AMDGPU_PP_SENSOR_VCE_ECCLK,
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 	AMDGPU_PP_SENSOR_GPU_LOAD,
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+	AMDGPU_PP_SENSOR_MEM_LOAD,
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 	AMDGPU_PP_SENSOR_GFX_MCLK,
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 	AMDGPU_PP_SENSOR_GPU_TEMP,
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+	AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
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+	AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
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+	AMDGPU_PP_SENSOR_MEM_TEMP,
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 	AMDGPU_PP_SENSOR_VCE_POWER,
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 	AMDGPU_PP_SENSOR_UVD_POWER,
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 	AMDGPU_PP_SENSOR_GPU_POWER,
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 	AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
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 	AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
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+	AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
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+	AMDGPU_PP_SENSOR_MIN_FAN_RPM,
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+	AMDGPU_PP_SENSOR_MAX_FAN_RPM,
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+	AMDGPU_PP_SENSOR_VCN_POWER_STATE,
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 };
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 enum amd_pp_task {
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@@ -123,12 +135,14 @@
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 };
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 enum PP_SMC_POWER_PROFILE {
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-	PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x0,
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-	PP_SMC_POWER_PROFILE_POWERSAVING  = 0x1,
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-	PP_SMC_POWER_PROFILE_VIDEO        = 0x2,
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-	PP_SMC_POWER_PROFILE_VR           = 0x3,
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-	PP_SMC_POWER_PROFILE_COMPUTE      = 0x4,
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-	PP_SMC_POWER_PROFILE_CUSTOM       = 0x5,
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+	PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
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+	PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
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+	PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
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+	PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
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+	PP_SMC_POWER_PROFILE_VR           = 0x4,
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+	PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
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+	PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
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+	PP_SMC_POWER_PROFILE_COUNT,
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 };
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 enum {
..
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@@ -141,6 +155,7 @@
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 enum PP_OD_DPM_TABLE_COMMAND {
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 	PP_OD_EDIT_SCLK_VDDC_TABLE,
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 	PP_OD_EDIT_MCLK_VDDC_TABLE,
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+	PP_OD_EDIT_VDDC_CURVE,
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 	PP_OD_RESTORE_DEFAULT_TABLE,
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 	PP_OD_COMMIT_DPM_TABLE
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 };
..
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@@ -148,6 +163,25 @@
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 struct pp_states_info {
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 	uint32_t nums;
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 	uint32_t states[16];
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+};
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+
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+enum PP_HWMON_TEMP {
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+	PP_TEMP_EDGE = 0,
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+	PP_TEMP_JUNCTION,
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+	PP_TEMP_MEM,
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+	PP_TEMP_MAX
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+};
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+
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+enum pp_mp1_state {
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+	PP_MP1_STATE_NONE,
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+	PP_MP1_STATE_SHUTDOWN,
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+	PP_MP1_STATE_UNLOAD,
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+	PP_MP1_STATE_RESET,
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+};
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+
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+enum pp_df_cstate {
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+	DF_CSTATE_DISALLOW = 0,
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+	DF_CSTATE_ALLOW,
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 };
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 #define PP_GROUP_MASK        0xF0000000
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@@ -185,6 +219,9 @@
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 #define PP_CG_MSG_ID(group, block, support, state) \
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 		((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
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 		(support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
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+
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+#define XGMI_MODE_PSTATE_D3 0
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+#define XGMI_MODE_PSTATE_D0 1
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 struct seq_file;
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 enum amd_pp_clock_type;
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@@ -225,6 +262,7 @@
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 	enum amd_dpm_forced_level (*get_performance_level)(void *handle);
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 	enum amd_pm_state_type (*get_current_power_state)(void *handle);
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 	int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
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+	int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
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 	int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
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 	int (*get_pp_table)(void *handle, char **table);
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 	int (*set_pp_table)(void *handle, const char *buf, size_t size);
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@@ -243,7 +281,10 @@
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 	int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
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 	int (*get_power_profile_mode)(void *handle, char *buf);
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 	int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
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+	int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
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 	int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
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+	int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
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+	int (*smu_i2c_bus_access)(void *handle, bool acquire);
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 /* export to DC */
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 	u32 (*get_sclk)(void *handle, bool low);
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 	u32 (*get_mclk)(void *handle, bool low);
..
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@@ -269,6 +310,128 @@
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 	int (*get_display_mode_validation_clocks)(void *handle,
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 		struct amd_pp_simple_clock_info *clocks);
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 	int (*notify_smu_enable_pwe)(void *handle);
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+	int (*enable_mgpu_fan_boost)(void *handle);
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+	int (*set_active_display_count)(void *handle, uint32_t count);
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+	int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
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+	int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
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+	int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
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+	int (*get_asic_baco_capability)(void *handle, bool *cap);
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+	int (*get_asic_baco_state)(void *handle, int *state);
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+	int (*set_asic_baco_state)(void *handle, int state);
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+	int (*get_ppfeature_status)(void *handle, char *buf);
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+	int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
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+	int (*asic_reset_mode_2)(void *handle);
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+	int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
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+	int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
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+	ssize_t (*get_gpu_metrics)(void *handle, void **table);
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+};
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+
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+struct metrics_table_header {
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+	uint16_t			structure_size;
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+	uint8_t				format_revision;
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+	uint8_t				content_revision;
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+};
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+
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+struct gpu_metrics_v1_0 {
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+	struct metrics_table_header	common_header;
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+
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+	/* Driver attached timestamp (in ns) */
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+	uint64_t			system_clock_counter;
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+
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+	/* Temperature */
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+	uint16_t			temperature_edge;
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+	uint16_t			temperature_hotspot;
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+	uint16_t			temperature_mem;
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+	uint16_t			temperature_vrgfx;
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+	uint16_t			temperature_vrsoc;
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+	uint16_t			temperature_vrmem;
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+
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+	/* Utilization */
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+	uint16_t			average_gfx_activity;
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+	uint16_t			average_umc_activity; // memory controller
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+	uint16_t			average_mm_activity; // UVD or VCN
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+
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+	/* Power/Energy */
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+	uint16_t			average_socket_power;
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+	uint32_t			energy_accumulator;
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+
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+	/* Average clocks */
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+	uint16_t			average_gfxclk_frequency;
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+	uint16_t			average_socclk_frequency;
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+	uint16_t			average_uclk_frequency;
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+	uint16_t			average_vclk0_frequency;
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+	uint16_t			average_dclk0_frequency;
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+	uint16_t			average_vclk1_frequency;
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+	uint16_t			average_dclk1_frequency;
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+
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+	/* Current clocks */
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+	uint16_t			current_gfxclk;
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+	uint16_t			current_socclk;
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+	uint16_t			current_uclk;
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+	uint16_t			current_vclk0;
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+	uint16_t			current_dclk0;
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+	uint16_t			current_vclk1;
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+	uint16_t			current_dclk1;
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+
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+	/* Throttle status */
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+	uint32_t			throttle_status;
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+
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+	/* Fans */
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+	uint16_t			current_fan_speed;
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+
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+	/* Link width/speed */
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+	uint8_t				pcie_link_width;
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+	uint8_t				pcie_link_speed; // in 0.1 GT/s
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+};
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+
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+struct gpu_metrics_v2_0 {
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+	struct metrics_table_header	common_header;
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+
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+	/* Driver attached timestamp (in ns) */
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+	uint64_t			system_clock_counter;
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+
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+	/* Temperature */
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+	uint16_t			temperature_gfx; // gfx temperature on APUs
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+	uint16_t			temperature_soc; // soc temperature on APUs
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+	uint16_t			temperature_core[8]; // CPU core temperature on APUs
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+	uint16_t			temperature_l3[2];
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+
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+	/* Utilization */
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+	uint16_t			average_gfx_activity;
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+	uint16_t			average_mm_activity; // UVD or VCN
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+
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+	/* Power/Energy */
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+	uint16_t			average_socket_power; // dGPU + APU power on A + A platform
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+	uint16_t			average_cpu_power;
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+	uint16_t			average_soc_power;
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+	uint16_t			average_gfx_power;
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+	uint16_t			average_core_power[8]; // CPU core power on APUs
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+
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+	/* Average clocks */
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+	uint16_t			average_gfxclk_frequency;
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+	uint16_t			average_socclk_frequency;
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+	uint16_t			average_uclk_frequency;
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+	uint16_t			average_fclk_frequency;
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+	uint16_t			average_vclk_frequency;
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+	uint16_t			average_dclk_frequency;
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+
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+	/* Current clocks */
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+	uint16_t			current_gfxclk;
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+	uint16_t			current_socclk;
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+	uint16_t			current_uclk;
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+	uint16_t			current_fclk;
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+	uint16_t			current_vclk;
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+	uint16_t			current_dclk;
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+	uint16_t			current_coreclk[8]; // CPU core clocks
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+	uint16_t			current_l3clk[2];
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+
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+	/* Throttle status */
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+	uint32_t			throttle_status;
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+
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+	/* Fans */
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+	uint16_t			fan_pwm;
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+
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+	uint16_t			padding;
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 };
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 #endif