kernel/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h
.. .. @@ -194,6 +194,8 @@ 194 194 #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 195 195 #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff 196 196 #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 197 +#define CG_SPLL_STATUS__SPLL_CHG_STATUS_MASK 0x2198 +#define CG_SPLL_STATUS__SPLL_CHG_STATUS__SHIFT 0x1197 199 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 198 200 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 199 201 #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2