add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h
..
..
@@ -147,6 +147,46 @@
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 	IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh), \
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 	IPP_SF(DCP0_DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, mask_sh)
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+#define IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
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+	IPP_SF(CUR_UPDATE, CURSOR_UPDATE_LOCK, mask_sh), \
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+	IPP_SF(CUR_CONTROL, CURSOR_EN, mask_sh), \
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+	IPP_SF(CUR_CONTROL, CURSOR_MODE, mask_sh), \
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+	IPP_SF(CUR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
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+	IPP_SF(CUR_CONTROL, CUR_INV_TRANS_CLAMP, mask_sh), \
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+	IPP_SF(CUR_POSITION, CURSOR_X_POSITION, mask_sh), \
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+	IPP_SF(CUR_POSITION, CURSOR_Y_POSITION, mask_sh), \
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+	IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
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+	IPP_SF(CUR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
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+	IPP_SF(CUR_COLOR1, CUR_COLOR1_BLUE, mask_sh), \
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+	IPP_SF(CUR_COLOR1, CUR_COLOR1_GREEN, mask_sh), \
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+	IPP_SF(CUR_COLOR1, CUR_COLOR1_RED, mask_sh), \
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+	IPP_SF(CUR_COLOR2, CUR_COLOR2_BLUE, mask_sh), \
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+	IPP_SF(CUR_COLOR2, CUR_COLOR2_GREEN, mask_sh), \
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+	IPP_SF(CUR_COLOR2, CUR_COLOR2_RED, mask_sh), \
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+	IPP_SF(CUR_SIZE, CURSOR_WIDTH, mask_sh), \
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+	IPP_SF(CUR_SIZE, CURSOR_HEIGHT, mask_sh), \
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+	IPP_SF(CUR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
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+	IPP_SF(CUR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
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+	IPP_SF(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, mask_sh), \
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+	IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_SCALE_R, mask_sh), \
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+	IPP_SF(PRESCALE_VALUES_GRPH_R, GRPH_PRESCALE_BIAS_R, mask_sh), \
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+	IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_SCALE_G, mask_sh), \
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+	IPP_SF(PRESCALE_VALUES_GRPH_G, GRPH_PRESCALE_BIAS_G, mask_sh), \
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+	IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_SCALE_B, mask_sh), \
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+	IPP_SF(PRESCALE_VALUES_GRPH_B, GRPH_PRESCALE_BIAS_B, mask_sh), \
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+	IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
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+	IPP_SF(DC_LUT_WRITE_EN_MASK, DC_LUT_WRITE_EN_MASK, mask_sh), \
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+	IPP_SF(DC_LUT_RW_MODE, DC_LUT_RW_MODE, mask_sh), \
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+	IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_R_FORMAT, mask_sh), \
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+	IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_G_FORMAT, mask_sh), \
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+	IPP_SF(DC_LUT_CONTROL, DC_LUT_DATA_B_FORMAT, mask_sh), \
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+	IPP_SF(DC_LUT_RW_INDEX, DC_LUT_RW_INDEX, mask_sh), \
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+	IPP_SF(DC_LUT_SEQ_COLOR, DC_LUT_SEQ_COLOR, mask_sh), \
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+	IPP_SF(DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, mask_sh), \
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+	IPP_SF(DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, mask_sh)
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+#endif
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+
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 #define IPP_REG_FIELD_LIST(type) \
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 	type CURSOR_UPDATE_LOCK; \
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 	type CURSOR_EN; \
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@@ -233,6 +273,15 @@
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 	const struct dce_ipp_shift *ipp_shift,
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 	const struct dce_ipp_mask *ipp_mask);
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+void dce60_ipp_construct(struct dce_ipp *ipp_dce,
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+	struct dc_context *ctx,
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+	int inst,
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+	const struct dce_ipp_registers *regs,
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+	const struct dce_ipp_shift *ipp_shift,
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+	const struct dce_ipp_mask *ipp_mask);
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+#endif
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+
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 void dce_ipp_destroy(struct input_pixel_processor **ipp);
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 #endif /* _DCE_IPP_H_ */