add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/clk/renesas/r8a77990-cpg-mssr.c
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@@ -2,7 +2,7 @@
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 /*
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  * r8a77990 Clock Pulse Generator / Module Standby and Software Reset
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  *
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- * Copyright (C) 2018 Renesas Electronics Corp.
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+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
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  *
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  * Based on r8a7795-cpg-mssr.c
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  *
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@@ -44,6 +44,8 @@
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 	CLK_S2,
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 	CLK_S3,
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 	CLK_SDSRC,
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+	CLK_RINT,
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+	CLK_OCO,
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 	/* Module Clocks */
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 	MOD_CLK_BASE
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@@ -72,9 +74,14 @@
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 	DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
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 	DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
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+	DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),
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+
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+	DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
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+
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 	/* Core Clock Outputs */
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 	DEF_FIXED("za2",       R8A77990_CLK_ZA2,   CLK_PLL0D24,    1, 1),
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 	DEF_FIXED("za8",       R8A77990_CLK_ZA8,   CLK_PLL0D8,     1, 1),
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+	DEF_GEN3_Z("z2",       R8A77990_CLK_Z2,    CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),
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 	DEF_FIXED("ztr",       R8A77990_CLK_ZTR,   CLK_PLL1,       6, 1),
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 	DEF_FIXED("zt",        R8A77990_CLK_ZT,    CLK_PLL1,       4, 1),
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 	DEF_FIXED("zx",        R8A77990_CLK_ZX,    CLK_PLL1,       3, 1),
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@@ -98,10 +105,11 @@
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 	DEF_GEN3_SD("sd3",     R8A77990_CLK_SD3,   CLK_SDSRC,	  0x026c),
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 	DEF_FIXED("cl",        R8A77990_CLK_CL,    CLK_PLL1,      48, 1),
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+	DEF_FIXED("cr",        R8A77990_CLK_CR,    CLK_PLL1D2,     2, 1),
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 	DEF_FIXED("cp",        R8A77990_CLK_CP,    CLK_EXTAL,      2, 1),
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 	DEF_FIXED("cpex",      R8A77990_CLK_CPEX,  CLK_EXTAL,      4, 1),
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-	DEF_FIXED("osc",       R8A77990_CLK_OSC,   CLK_EXTAL,    384, 1),
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-	DEF_FIXED("r",         R8A77990_CLK_R,     CLK_EXTAL,   1536, 1),
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+
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+	DEF_DIV6_RO("osc",     R8A77990_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
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 	DEF_GEN3_PE("s0d6c",   R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
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 	DEF_GEN3_PE("s3d1c",   R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
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@@ -111,6 +119,8 @@
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 	DEF_DIV6P1("canfd",    R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
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 	DEF_DIV6P1("csi0",     R8A77990_CLK_CSI0,  CLK_PLL1D2, 0x00c),
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 	DEF_DIV6P1("mso",      R8A77990_CLK_MSO,   CLK_PLL1D2, 0x014),
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+
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+	DEF_GEN3_RCKSEL("r",   R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
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 };
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 static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
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@@ -126,6 +136,7 @@
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 	DEF_MOD("sys-dmac2",		 217,	R8A77990_CLK_S3D1),
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 	DEF_MOD("sys-dmac1",		 218,	R8A77990_CLK_S3D1),
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 	DEF_MOD("sys-dmac0",		 219,	R8A77990_CLK_S3D1),
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+	DEF_MOD("sceg-pub",		 229,	R8A77990_CLK_CR),
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 	DEF_MOD("cmt3",			 300,	R8A77990_CLK_R),
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 	DEF_MOD("cmt2",			 301,	R8A77990_CLK_R),
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@@ -144,15 +155,15 @@
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 	DEF_MOD("intc-ex",		 407,	R8A77990_CLK_CP),
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 	DEF_MOD("intc-ap",		 408,	R8A77990_CLK_S0D3),
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-	DEF_MOD("audmac0",		 502,	R8A77990_CLK_S3D4),
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-	DEF_MOD("drif7",		 508,	R8A77990_CLK_S3D2),
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-	DEF_MOD("drif6",		 509,	R8A77990_CLK_S3D2),
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-	DEF_MOD("drif5",		 510,	R8A77990_CLK_S3D2),
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-	DEF_MOD("drif4",		 511,	R8A77990_CLK_S3D2),
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-	DEF_MOD("drif3",		 512,	R8A77990_CLK_S3D2),
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-	DEF_MOD("drif2",		 513,	R8A77990_CLK_S3D2),
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-	DEF_MOD("drif1",		 514,	R8A77990_CLK_S3D2),
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-	DEF_MOD("drif0",		 515,	R8A77990_CLK_S3D2),
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+	DEF_MOD("audmac0",		 502,	R8A77990_CLK_S1D2),
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+	DEF_MOD("drif31",		 508,	R8A77990_CLK_S3D2),
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+	DEF_MOD("drif30",		 509,	R8A77990_CLK_S3D2),
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+	DEF_MOD("drif21",		 510,	R8A77990_CLK_S3D2),
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+	DEF_MOD("drif20",		 511,	R8A77990_CLK_S3D2),
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+	DEF_MOD("drif11",		 512,	R8A77990_CLK_S3D2),
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+	DEF_MOD("drif10",		 513,	R8A77990_CLK_S3D2),
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+	DEF_MOD("drif01",		 514,	R8A77990_CLK_S3D2),
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+	DEF_MOD("drif00",		 515,	R8A77990_CLK_S3D2),
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 	DEF_MOD("hscif4",		 516,	R8A77990_CLK_S3D1C),
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 	DEF_MOD("hscif3",		 517,	R8A77990_CLK_S3D1C),
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 	DEF_MOD("hscif2",		 518,	R8A77990_CLK_S3D1C),
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@@ -172,8 +183,10 @@
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 	DEF_MOD("vspb",			 626,	R8A77990_CLK_S0D1),
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 	DEF_MOD("vspi0",		 631,	R8A77990_CLK_S0D1),
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-	DEF_MOD("ehci0",		 703,	R8A77990_CLK_S3D4),
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-	DEF_MOD("hsusb",		 704,	R8A77990_CLK_S3D4),
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+	DEF_MOD("ehci0",		 703,	R8A77990_CLK_S3D2),
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+	DEF_MOD("hsusb",		 704,	R8A77990_CLK_S3D2),
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+	DEF_MOD("cmm1",			 710,	R8A77990_CLK_S1D1),
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+	DEF_MOD("cmm0",			 711,	R8A77990_CLK_S1D1),
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 	DEF_MOD("csi40",		 716,	R8A77990_CLK_CSI0),
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 	DEF_MOD("du1",			 723,	R8A77990_CLK_S1D1),
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 	DEF_MOD("du0",			 724,	R8A77990_CLK_S1D1),
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@@ -202,6 +215,7 @@
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 	DEF_MOD("i2c1",			 930,	R8A77990_CLK_S3D2),
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 	DEF_MOD("i2c0",			 931,	R8A77990_CLK_S3D2),
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+	DEF_MOD("i2c7",			1003,	R8A77990_CLK_S3D2),
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 	DEF_MOD("ssi-all",		1005,	R8A77990_CLK_S3D4),
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 	DEF_MOD("ssi9",			1006,	MOD_CLK_ID(1005)),
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 	DEF_MOD("ssi8",			1007,	MOD_CLK_ID(1005)),
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@@ -231,6 +245,7 @@
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 };
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 static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
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+	MOD_CLK_ID(402),	/* RWDT */
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 	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
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 };
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@@ -241,8 +256,8 @@
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 /*
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  * MD19		EXTAL (MHz)	PLL0		PLL1		PLL3
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  *--------------------------------------------------------------------
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- * 0		48 x 1		x100/4		x100/3		x100/3
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- * 1		48 x 1		x100/4		x100/3		 x58/3
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+ * 0		48 x 1		x100/1		x100/3		x100/3
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+ * 1		48 x 1		x100/1		x100/3		 x58/3
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  */
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 #define CPG_PLL_CONFIG_INDEX(md)	(((md) & BIT(19)) >> 19)
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