add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/clk/renesas/r8a77980-cpg-mssr.c
..
..
@@ -41,6 +41,8 @@
41
41
 	CLK_S2,
42
42
 	CLK_S3,
43
43
 	CLK_SDSRC,
44
+	CLK_RPCSRC,
45
+	CLK_OCO,
44
46
 
45
47
 	/* Module Clocks */
46
48
 	MOD_CLK_BASE
..
..
@@ -64,6 +66,13 @@
64
66
 	DEF_FIXED(".s2",	CLK_S2,		   CLK_PLL1_DIV2,  4, 1),
65
67
 	DEF_FIXED(".s3",	CLK_S3,		   CLK_PLL1_DIV2,  6, 1),
66
68
 	DEF_FIXED(".sdsrc",	CLK_SDSRC,	   CLK_PLL1_DIV2,  2, 1),
69
+	DEF_BASE(".rpcsrc",	CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
70
+	DEF_RATE(".oco",	CLK_OCO,           32768),
71
+
72
+	DEF_BASE("rpc",		R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
73
+		 CLK_RPCSRC),
74
+	DEF_BASE("rpcd2",	R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
75
+		 R8A77980_CLK_RPC),
67
76
 
68
77
 	/* Core Clock Outputs */
69
78
 	DEF_FIXED("ztr",	R8A77980_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
..
..
@@ -96,6 +105,9 @@
96
105
 	DEF_DIV6P1("canfd",	R8A77980_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
97
106
 	DEF_DIV6P1("csi0",	R8A77980_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
98
107
 	DEF_DIV6P1("mso",	R8A77980_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
108
+
109
+	DEF_GEN3_OSC("osc",	R8A77980_CLK_OSC,   CLK_EXTAL,     8),
110
+	DEF_GEN3_MDSEL("r",	R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
99
111
 };
100
112
 
101
113
 static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
..
..
@@ -114,9 +126,14 @@
114
126
 	DEF_MOD("msiof0",		 211,	R8A77980_CLK_MSO),
115
127
 	DEF_MOD("sys-dmac2",		 217,	R8A77980_CLK_S0D3),
116
128
 	DEF_MOD("sys-dmac1",		 218,	R8A77980_CLK_S0D3),
129
+	DEF_MOD("cmt3",			 300,	R8A77980_CLK_R),
130
+	DEF_MOD("cmt2",			 301,	R8A77980_CLK_R),
131
+	DEF_MOD("cmt1",			 302,	R8A77980_CLK_R),
132
+	DEF_MOD("cmt0",			 303,	R8A77980_CLK_R),
117
133
 	DEF_MOD("tpu0",			 304,	R8A77980_CLK_S3D4),
118
134
 	DEF_MOD("sdif",			 314,	R8A77980_CLK_SD0),
119
135
 	DEF_MOD("pciec0",		 319,	R8A77980_CLK_S2D2),
136
+	DEF_MOD("rwdt",			 402,	R8A77980_CLK_R),
120
137
 	DEF_MOD("intc-ex",		 407,	R8A77980_CLK_CP),
121
138
 	DEF_MOD("intc-ap",		 408,	R8A77980_CLK_S0D3),
122
139
 	DEF_MOD("hscif3",		 517,	R8A77980_CLK_S3D1),
..
..
@@ -154,6 +171,7 @@
154
171
 	DEF_MOD("gpio1",		 911,	R8A77980_CLK_CP),
155
172
 	DEF_MOD("gpio0",		 912,	R8A77980_CLK_CP),
156
173
 	DEF_MOD("can-fd",		 914,	R8A77980_CLK_S3D2),
174
+	DEF_MOD("rpc-if",		 917,	R8A77980_CLK_RPCD2),
157
175
 	DEF_MOD("i2c4",			 927,	R8A77980_CLK_S0D6),
158
176
 	DEF_MOD("i2c3",			 928,	R8A77980_CLK_S0D6),
159
177
 	DEF_MOD("i2c2",			 929,	R8A77980_CLK_S3D2),
..
..
@@ -162,32 +180,32 @@
162
180
 };
163
181
 
164
182
 static const unsigned int r8a77980_crit_mod_clks[] __initconst = {
183
+	MOD_CLK_ID(402),	/* RWDT */
165
184
 	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
166
185
 };
167
-
168
186
 
169
187
 /*
170
188
  * CPG Clock Data
171
189
  */
172
190
 
173
191
 /*
174
- *   MD		EXTAL		PLL2	PLL1	PLL3
192
+ *   MD		EXTAL		PLL2	PLL1	PLL3	OSC
175
193
  * 14 13	(MHz)
176
- * --------------------------------------------------
177
- * 0  0		16.66 x 1	x240	x192	x192
178
- * 0  1		20    x 1	x200	x160	x160
179
- * 1  0		27    x 1	x148	x118	x118
180
- * 1  1		33.33 / 2	x240	x192	x192
194
+ * --------------------------------------------------------
195
+ * 0  0		16.66 x 1	x240	x192	x192	/16
196
+ * 0  1		20    x 1	x200	x160	x160	/19
197
+ * 1  0		27    x 1	x148	x118	x118	/26
198
+ * 1  1		33.33 / 2	x240	x192	x192	/32
181
199
  */
182
200
 #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
183
201
 					 (((md) & BIT(13)) >> 13))
184
202
 
185
203
 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
186
-	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
187
-	{ 1,		192,	1,	192,	1,	},
188
-	{ 1,		160,	1,	160,	1,	},
189
-	{ 1,		118,	1,	118,	1,	},
190
-	{ 2,		192,	1,	192,	1,	},
204
+	/* EXTAL div	PLL1 mult/div	PLL3 mult/div	OSC prediv */
205
+	{ 1,		192,	1,	192,	1,	16,	},
206
+	{ 1,		160,	1,	160,	1,	19,	},
207
+	{ 1,		118,	1,	118,	1,	26,	},
208
+	{ 2,		192,	1,	192,	1,	32,	},
191
209
 };
192
210
 
193
211
 static int __init r8a77980_cpg_mssr_init(struct device *dev)