add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/arch/x86/power/cpu.c
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@@ -1,7 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Suspend support specific for i386/x86-64.
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- *
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- * Distribute under GPLv2
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  *
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  * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
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  * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
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@@ -14,8 +13,8 @@
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 #include <linux/perf_event.h>
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 #include <linux/tboot.h>
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 #include <linux/dmi.h>
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+#include <linux/pgtable.h>
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-#include <asm/pgtable.h>
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 #include <asm/proto.h>
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 #include <asm/mtrr.h>
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 #include <asm/page.h>
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@@ -26,6 +25,7 @@
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 #include <asm/cpu.h>
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 #include <asm/mmu_context.h>
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 #include <asm/cpu_device_id.h>
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+#include <asm/microcode.h>
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29
 
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 #ifdef CONFIG_X86_32
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 __visible unsigned long saved_context_ebx;
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@@ -41,7 +41,8 @@
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 	struct saved_msr *end = msr + ctxt->saved_msrs.num;
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 	while (msr < end) {
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-		msr->valid = !rdmsrl_safe(msr->info.msr_no, &msr->info.reg.q);
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+		if (msr->valid)
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+			rdmsrl(msr->info.msr_no, msr->info.reg.q);
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 		msr++;
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 	}
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 }
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@@ -124,9 +125,6 @@
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 	ctxt->cr2 = read_cr2();
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 	ctxt->cr3 = __read_cr3();
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 	ctxt->cr4 = __read_cr4();
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-#ifdef CONFIG_X86_64
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-	ctxt->cr8 = read_cr8();
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-#endif
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 	ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
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 					       &ctxt->misc_enable);
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 	msr_save_context(ctxt);
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@@ -197,6 +195,8 @@
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  */
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 static void notrace __restore_processor_state(struct saved_context *ctxt)
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 {
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+	struct cpuinfo_x86 *c;
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+
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 	if (ctxt->misc_enable_saved)
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 		wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
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 	/*
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@@ -209,7 +209,6 @@
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 #else
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 /* CONFIG X86_64 */
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 	wrmsrl(MSR_EFER, ctxt->efer);
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-	write_cr8(ctxt->cr8);
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 	__write_cr4(ctxt->cr4);
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 #endif
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 	write_cr3(ctxt->cr3);
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@@ -267,12 +266,36 @@
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 	x86_platform.restore_sched_clock_state();
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 	mtrr_bp_restore();
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 	perf_restore_debug_store();
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+
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+	c = &cpu_data(smp_processor_id());
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+	if (cpu_has(c, X86_FEATURE_MSR_IA32_FEAT_CTL))
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+		init_ia32_feat_ctl(c);
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+
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+	microcode_bsp_resume();
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+
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+	/*
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+	 * This needs to happen after the microcode has been updated upon resume
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+	 * because some of the MSRs are "emulated" in microcode.
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+	 */
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 	msr_restore_context(ctxt);
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 }
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 /* Needed by apm.c */
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 void notrace restore_processor_state(void)
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 {
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+#ifdef __clang__
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+	// The following code snippet is copied from __restore_processor_state.
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+	// Its purpose is to prepare GS segment before the function is called.
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+	// Since the function is compiled with SCS on, it will use GS at its
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+	// entry.
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+	// TODO: Hack to be removed later when compiler bug is fixed.
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+#ifdef CONFIG_X86_64
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+	wrmsrl(MSR_GS_BASE, saved_context.kernelmode_gs_base);
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+#else
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+	loadsegment(fs, __KERNEL_PERCPU);
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+	loadsegment(gs, __KERNEL_STACK_CANARY);
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+#endif
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+#endif
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 	__restore_processor_state(&saved_context);
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 }
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 #ifdef CONFIG_X86_32
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@@ -312,7 +335,7 @@
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 	if (ret)
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 		return ret;
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 	smp_ops.play_dead = resume_play_dead;
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-	ret = disable_nonboot_cpus();
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+	ret = freeze_secondary_cpus(0);
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 	smp_ops.play_dead = play_dead;
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 	return ret;
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 }
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@@ -426,8 +449,10 @@
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 	}
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 	for (i = saved_msrs->num, j = 0; i < total_num; i++, j++) {
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+		u64 dummy;
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+
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 		msr_array[i].info.msr_no	= msr_id[j];
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-		msr_array[i].valid		= false;
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+		msr_array[i].valid		= !rdmsrl_safe(msr_id[j], &dummy);
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 		msr_array[i].info.reg.q		= 0;
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 	}
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 	saved_msrs->num   = total_num;
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@@ -480,20 +505,8 @@
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 }
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 static const struct x86_cpu_id msr_save_cpu_table[] = {
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-	{
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-		.vendor = X86_VENDOR_AMD,
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-		.family = 0x15,
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-		.model = X86_MODEL_ANY,
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-		.feature = X86_FEATURE_ANY,
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-		.driver_data = (kernel_ulong_t)msr_save_cpuid_features,
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-	},
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-	{
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-		.vendor = X86_VENDOR_AMD,
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-		.family = 0x16,
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-		.model = X86_MODEL_ANY,
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-		.feature = X86_FEATURE_ANY,
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-		.driver_data = (kernel_ulong_t)msr_save_cpuid_features,
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-	},
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+	X86_MATCH_VENDOR_FAM(AMD, 0x15, &msr_save_cpuid_features),
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+	X86_MATCH_VENDOR_FAM(AMD, 0x16, &msr_save_cpuid_features),
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 	{}
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 };
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@@ -514,10 +527,32 @@
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 	return ret;
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 }
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+static void pm_save_spec_msr(void)
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+{
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+	struct msr_enumeration {
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+		u32 msr_no;
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+		u32 feature;
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+	} msr_enum[] = {
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+		{ MSR_IA32_SPEC_CTRL,	 X86_FEATURE_MSR_SPEC_CTRL },
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+		{ MSR_IA32_TSX_CTRL,	 X86_FEATURE_MSR_TSX_CTRL },
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+		{ MSR_TSX_FORCE_ABORT,	 X86_FEATURE_TSX_FORCE_ABORT },
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+		{ MSR_IA32_MCU_OPT_CTRL, X86_FEATURE_SRBDS_CTRL },
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+		{ MSR_AMD64_LS_CFG,	 X86_FEATURE_LS_CFG_SSBD },
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+		{ MSR_AMD64_DE_CFG,	 X86_FEATURE_LFENCE_RDTSC },
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+	};
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+	int i;
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+
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+	for (i = 0; i < ARRAY_SIZE(msr_enum); i++) {
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+		if (boot_cpu_has(msr_enum[i].feature))
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+			msr_build_context(&msr_enum[i].msr_no, 1);
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+	}
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+}
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+
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 static int pm_check_save_msr(void)
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 {
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 	dmi_check_system(msr_save_dmi_table);
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 	pm_cpu_check(msr_save_cpu_table);
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+	pm_save_spec_msr();
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 	return 0;
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 }