add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/arch/x86/include/asm/stackprotector.h
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@@ -13,7 +13,7 @@
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  * On x86_64, %gs is shared by percpu area and stack canary.  All
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  * percpu symbols are zero based and %gs points to the base of percpu
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  * area.  The first occupant of the percpu area is always
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- * irq_stack_union which contains stack_canary at offset 40.  Userland
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+ * fixed_percpu_data which contains stack_canary at offset 40.  Userland
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  * %gs is always saved and restored on kernel entry and exit using
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  * swapgs, so stack protector doesn't add any complexity there.
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  *
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@@ -65,11 +65,11 @@
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  */
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 static __always_inline void boot_init_stack_canary(void)
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 {
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-	u64 uninitialized_var(canary);
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+	u64 canary = 0;
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 	u64 tsc;
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 #ifdef CONFIG_X86_64
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-	BUILD_BUG_ON(offsetof(union irq_stack_union, stack_canary) != 40);
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+	BUILD_BUG_ON(offsetof(struct fixed_percpu_data, stack_canary) != 40);
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 #endif
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 	/*
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 	 * We both use the random pool and the current TSC as a source
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@@ -81,7 +81,7 @@
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 	 * due to locking constraints. We just leave canary
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 	 * uninitialized and use the TSC based randomness on top of it.
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 	 */
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-#ifndef CONFIG_PREEMPT_RT_FULL
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+#ifndef CONFIG_PREEMPT_RT
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 	get_random_bytes(&canary, sizeof(canary));
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 #endif
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 	tsc = rdtsc();
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@@ -90,9 +90,18 @@
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 	current->stack_canary = canary;
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 #ifdef CONFIG_X86_64
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-	this_cpu_write(irq_stack_union.stack_canary, canary);
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+	this_cpu_write(fixed_percpu_data.stack_canary, canary);
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 #else
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 	this_cpu_write(stack_canary.canary, canary);
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+#endif
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+}
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+
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+static inline void cpu_init_stack_canary(int cpu, struct task_struct *idle)
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+{
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+#ifdef CONFIG_X86_64
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+	per_cpu(fixed_percpu_data.stack_canary, cpu) = idle->stack_canary;
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+#else
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+	per_cpu(stack_canary.canary, cpu) = idle->stack_canary;
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 #endif
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 }
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@@ -125,6 +134,9 @@
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 static inline void setup_stack_canary_segment(int cpu)
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 { }
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+static inline void cpu_init_stack_canary(int cpu, struct task_struct *idle)
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+{ }
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+
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 static inline void load_stack_canary_segment(void)
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 {
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 #ifdef CONFIG_X86_32