.. | .. |
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1 | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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2 | 2 | /* |
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3 | | - * Device Tree Include file for Freescale Layerscape-1043A family SoC. |
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| 3 | + * Device Tree Include file for NXP Layerscape-1043A family SoC. |
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4 | 4 | * |
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5 | 5 | * Copyright 2014-2015 Freescale Semiconductor, Inc. |
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| 6 | + * Copyright 2018, 2020 NXP |
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6 | 7 | * |
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7 | 8 | * Mingkai Hu <Mingkai.hu@freescale.com> |
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8 | 9 | */ |
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.. | .. |
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17 | 18 | #size-cells = <2>; |
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18 | 19 | |
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19 | 20 | aliases { |
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| 21 | + crypto = &crypto; |
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20 | 22 | fman0 = &fman0; |
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21 | 23 | ethernet0 = &enet0; |
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22 | 24 | ethernet1 = &enet1; |
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.. | .. |
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25 | 27 | ethernet4 = &enet4; |
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26 | 28 | ethernet5 = &enet5; |
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27 | 29 | ethernet6 = &enet6; |
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| 30 | + rtc1 = &ftm_alarm0; |
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28 | 31 | }; |
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29 | 32 | |
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30 | 33 | cpus { |
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.. | .. |
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147 | 150 | }; |
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148 | 151 | |
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149 | 152 | thermal-zones { |
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150 | | - cpu_thermal: cpu-thermal { |
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| 153 | + ddr-controller { |
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151 | 154 | polling-delay-passive = <1000>; |
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152 | 155 | polling-delay = <5000>; |
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153 | | - |
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154 | | - thermal-sensors = <&tmu 3>; |
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| 156 | + thermal-sensors = <&tmu 0>; |
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155 | 157 | |
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156 | 158 | trips { |
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157 | | - cpu_alert: cpu-alert { |
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| 159 | + ddr-ctrler-alert { |
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158 | 160 | temperature = <85000>; |
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159 | 161 | hysteresis = <2000>; |
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160 | 162 | type = "passive"; |
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161 | 163 | }; |
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162 | | - cpu_crit: cpu-crit { |
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| 164 | + |
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| 165 | + ddr-ctrler-crit { |
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| 166 | + temperature = <95000>; |
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| 167 | + hysteresis = <2000>; |
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| 168 | + type = "critical"; |
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| 169 | + }; |
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| 170 | + }; |
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| 171 | + }; |
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| 172 | + |
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| 173 | + serdes { |
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| 174 | + polling-delay-passive = <1000>; |
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| 175 | + polling-delay = <5000>; |
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| 176 | + thermal-sensors = <&tmu 1>; |
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| 177 | + |
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| 178 | + trips { |
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| 179 | + serdes-alert { |
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| 180 | + temperature = <85000>; |
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| 181 | + hysteresis = <2000>; |
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| 182 | + type = "passive"; |
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| 183 | + }; |
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| 184 | + |
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| 185 | + serdes-crit { |
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| 186 | + temperature = <95000>; |
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| 187 | + hysteresis = <2000>; |
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| 188 | + type = "critical"; |
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| 189 | + }; |
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| 190 | + }; |
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| 191 | + }; |
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| 192 | + |
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| 193 | + fman { |
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| 194 | + polling-delay-passive = <1000>; |
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| 195 | + polling-delay = <5000>; |
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| 196 | + thermal-sensors = <&tmu 2>; |
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| 197 | + |
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| 198 | + trips { |
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| 199 | + fman-alert { |
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| 200 | + temperature = <85000>; |
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| 201 | + hysteresis = <2000>; |
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| 202 | + type = "passive"; |
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| 203 | + }; |
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| 204 | + |
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| 205 | + fman-crit { |
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| 206 | + temperature = <95000>; |
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| 207 | + hysteresis = <2000>; |
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| 208 | + type = "critical"; |
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| 209 | + }; |
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| 210 | + }; |
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| 211 | + }; |
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| 212 | + |
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| 213 | + core-cluster { |
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| 214 | + polling-delay-passive = <1000>; |
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| 215 | + polling-delay = <5000>; |
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| 216 | + thermal-sensors = <&tmu 3>; |
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| 217 | + |
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| 218 | + trips { |
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| 219 | + core_cluster_alert: core-cluster-alert { |
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| 220 | + temperature = <85000>; |
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| 221 | + hysteresis = <2000>; |
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| 222 | + type = "passive"; |
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| 223 | + }; |
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| 224 | + |
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| 225 | + core_cluster_crit: core-cluster-crit { |
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163 | 226 | temperature = <95000>; |
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164 | 227 | hysteresis = <2000>; |
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165 | 228 | type = "critical"; |
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.. | .. |
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168 | 231 | |
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169 | 232 | cooling-maps { |
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170 | 233 | map0 { |
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171 | | - trip = <&cpu_alert>; |
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| 234 | + trip = <&core_cluster_alert>; |
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172 | 235 | cooling-device = |
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173 | | - <&cpu0 THERMAL_NO_LIMIT |
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174 | | - THERMAL_NO_LIMIT>; |
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| 236 | + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
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| 237 | + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
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| 238 | + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
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| 239 | + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
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| 240 | + }; |
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| 241 | + }; |
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| 242 | + }; |
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| 243 | + |
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| 244 | + sec { |
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| 245 | + polling-delay-passive = <1000>; |
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| 246 | + polling-delay = <5000>; |
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| 247 | + thermal-sensors = <&tmu 4>; |
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| 248 | + |
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| 249 | + trips { |
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| 250 | + sec-alert { |
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| 251 | + temperature = <85000>; |
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| 252 | + hysteresis = <2000>; |
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| 253 | + type = "passive"; |
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| 254 | + }; |
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| 255 | + |
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| 256 | + sec-crit { |
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| 257 | + temperature = <95000>; |
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| 258 | + hysteresis = <2000>; |
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| 259 | + type = "critical"; |
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175 | 260 | }; |
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176 | 261 | }; |
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177 | 262 | }; |
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.. | .. |
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281 | 366 | ifc: ifc@1530000 { |
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282 | 367 | compatible = "fsl,ifc", "simple-bus"; |
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283 | 368 | reg = <0x0 0x1530000 0x0 0x10000>; |
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284 | | - big-endian; |
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285 | 369 | interrupts = <0 43 0x4>; |
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286 | 370 | }; |
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287 | 371 | |
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.. | .. |
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295 | 379 | interrupts = <0 99 0x4>; |
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296 | 380 | clock-names = "qspi_en", "qspi"; |
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297 | 381 | clocks = <&clockgen 4 0>, <&clockgen 4 0>; |
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298 | | - big-endian; |
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299 | 382 | status = "disabled"; |
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300 | 383 | }; |
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301 | 384 | |
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.. | .. |
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524 | 607 | #interrupt-cells = <2>; |
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525 | 608 | }; |
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526 | 609 | |
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| 610 | + uqe: uqe@2400000 { |
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| 611 | + #address-cells = <1>; |
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| 612 | + #size-cells = <1>; |
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| 613 | + compatible = "fsl,qe", "simple-bus"; |
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| 614 | + ranges = <0x0 0x0 0x2400000 0x40000>; |
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| 615 | + reg = <0x0 0x2400000 0x0 0x480>; |
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| 616 | + brg-frequency = <100000000>; |
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| 617 | + bus-frequency = <200000000>; |
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| 618 | + fsl,qe-num-riscs = <1>; |
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| 619 | + fsl,qe-num-snums = <28>; |
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| 620 | + |
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| 621 | + qeic: qeic@80 { |
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| 622 | + compatible = "fsl,qe-ic"; |
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| 623 | + reg = <0x80 0x80>; |
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| 624 | + #address-cells = <0>; |
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| 625 | + interrupt-controller; |
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| 626 | + #interrupt-cells = <1>; |
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| 627 | + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, |
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| 628 | + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
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| 629 | + }; |
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| 630 | + |
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| 631 | + si1: si@700 { |
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| 632 | + #address-cells = <1>; |
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| 633 | + #size-cells = <0>; |
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| 634 | + compatible = "fsl,ls1043-qe-si", |
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| 635 | + "fsl,t1040-qe-si"; |
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| 636 | + reg = <0x700 0x80>; |
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| 637 | + }; |
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| 638 | + |
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| 639 | + siram1: siram@1000 { |
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| 640 | + #address-cells = <1>; |
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| 641 | + #size-cells = <1>; |
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| 642 | + compatible = "fsl,ls1043-qe-siram", |
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| 643 | + "fsl,t1040-qe-siram"; |
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| 644 | + reg = <0x1000 0x800>; |
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| 645 | + }; |
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| 646 | + |
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| 647 | + ucc@2000 { |
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| 648 | + cell-index = <1>; |
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| 649 | + reg = <0x2000 0x200>; |
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| 650 | + interrupts = <32>; |
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| 651 | + interrupt-parent = <&qeic>; |
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| 652 | + }; |
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| 653 | + |
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| 654 | + ucc@2200 { |
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| 655 | + cell-index = <3>; |
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| 656 | + reg = <0x2200 0x200>; |
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| 657 | + interrupts = <34>; |
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| 658 | + interrupt-parent = <&qeic>; |
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| 659 | + }; |
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| 660 | + |
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| 661 | + muram@10000 { |
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| 662 | + #address-cells = <1>; |
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| 663 | + #size-cells = <1>; |
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| 664 | + compatible = "fsl,qe-muram", "fsl,cpm-muram"; |
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| 665 | + ranges = <0x0 0x10000 0x6000>; |
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| 666 | + |
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| 667 | + data-only@0 { |
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| 668 | + compatible = "fsl,qe-muram-data", |
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| 669 | + "fsl,cpm-muram-data"; |
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| 670 | + reg = <0x0 0x6000>; |
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| 671 | + }; |
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| 672 | + }; |
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| 673 | + }; |
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| 674 | + |
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527 | 675 | lpuart0: serial@2950000 { |
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528 | 676 | compatible = "fsl,ls1021a-lpuart"; |
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529 | 677 | reg = <0x0 0x2950000 0x0 0x1000>; |
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.. | .. |
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610 | 758 | dr_mode = "host"; |
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611 | 759 | snps,quirk-frame-length-adjustment = <0x20>; |
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612 | 760 | snps,dis_rxdet_inp3_quirk; |
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| 761 | + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; |
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| 762 | + status = "disabled"; |
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613 | 763 | }; |
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614 | 764 | |
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615 | 765 | usb1: usb3@3000000 { |
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.. | .. |
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619 | 769 | dr_mode = "host"; |
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620 | 770 | snps,quirk-frame-length-adjustment = <0x20>; |
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621 | 771 | snps,dis_rxdet_inp3_quirk; |
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| 772 | + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; |
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| 773 | + status = "disabled"; |
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622 | 774 | }; |
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623 | 775 | |
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624 | 776 | usb2: usb3@3100000 { |
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.. | .. |
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628 | 780 | dr_mode = "host"; |
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629 | 781 | snps,quirk-frame-length-adjustment = <0x20>; |
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630 | 782 | snps,dis_rxdet_inp3_quirk; |
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| 783 | + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; |
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| 784 | + status = "disabled"; |
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631 | 785 | }; |
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632 | 786 | |
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633 | 787 | sata: sata@3200000 { |
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.. | .. |
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661 | 815 | interrupts = <0 160 0x4>; |
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662 | 816 | }; |
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663 | 817 | |
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664 | | - pcie@3400000 { |
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665 | | - compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; |
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| 818 | + pcie1: pcie@3400000 { |
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| 819 | + compatible = "fsl,ls1043a-pcie"; |
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666 | 820 | reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ |
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667 | 821 | 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ |
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668 | 822 | reg-names = "regs", "config"; |
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.. | .. |
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673 | 827 | #size-cells = <2>; |
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674 | 828 | device_type = "pci"; |
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675 | 829 | dma-coherent; |
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676 | | - num-lanes = <4>; |
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| 830 | + num-viewport = <6>; |
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677 | 831 | bus-range = <0x0 0xff>; |
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678 | 832 | ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ |
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679 | 833 | 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
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.. | .. |
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684 | 838 | <0000 0 0 2 &gic 0 111 0x4>, |
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685 | 839 | <0000 0 0 3 &gic 0 112 0x4>, |
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686 | 840 | <0000 0 0 4 &gic 0 113 0x4>; |
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| 841 | + status = "disabled"; |
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687 | 842 | }; |
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688 | 843 | |
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689 | | - pcie@3500000 { |
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690 | | - compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; |
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| 844 | + pcie2: pcie@3500000 { |
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| 845 | + compatible = "fsl,ls1043a-pcie"; |
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691 | 846 | reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ |
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692 | 847 | 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ |
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693 | 848 | reg-names = "regs", "config"; |
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.. | .. |
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698 | 853 | #size-cells = <2>; |
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699 | 854 | device_type = "pci"; |
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700 | 855 | dma-coherent; |
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701 | | - num-lanes = <2>; |
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| 856 | + num-viewport = <6>; |
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702 | 857 | bus-range = <0x0 0xff>; |
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703 | 858 | ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ |
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704 | 859 | 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
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.. | .. |
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709 | 864 | <0000 0 0 2 &gic 0 121 0x4>, |
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710 | 865 | <0000 0 0 3 &gic 0 122 0x4>, |
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711 | 866 | <0000 0 0 4 &gic 0 123 0x4>; |
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| 867 | + status = "disabled"; |
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712 | 868 | }; |
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713 | 869 | |
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714 | | - pcie@3600000 { |
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715 | | - compatible = "fsl,ls1043a-pcie", "snps,dw-pcie"; |
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| 870 | + pcie3: pcie@3600000 { |
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| 871 | + compatible = "fsl,ls1043a-pcie"; |
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716 | 872 | reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ |
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717 | 873 | 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ |
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718 | 874 | reg-names = "regs", "config"; |
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.. | .. |
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723 | 879 | #size-cells = <2>; |
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724 | 880 | device_type = "pci"; |
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725 | 881 | dma-coherent; |
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726 | | - num-lanes = <2>; |
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| 882 | + num-viewport = <6>; |
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727 | 883 | bus-range = <0x0 0xff>; |
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728 | 884 | ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ |
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729 | 885 | 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
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.. | .. |
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734 | 890 | <0000 0 0 2 &gic 0 155 0x4>, |
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735 | 891 | <0000 0 0 3 &gic 0 156 0x4>, |
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736 | 892 | <0000 0 0 4 &gic 0 157 0x4>; |
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| 893 | + status = "disabled"; |
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| 894 | + }; |
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| 895 | + |
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| 896 | + qdma: dma-controller@8380000 { |
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| 897 | + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma"; |
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| 898 | + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ |
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| 899 | + <0x0 0x8390000 0x0 0x10000>, /* Status regs */ |
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| 900 | + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ |
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| 901 | + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
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| 902 | + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
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| 903 | + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
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| 904 | + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
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| 905 | + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
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| 906 | + interrupt-names = "qdma-error", "qdma-queue0", |
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| 907 | + "qdma-queue1", "qdma-queue2", "qdma-queue3"; |
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| 908 | + dma-channels = <8>; |
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| 909 | + block-number = <1>; |
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| 910 | + block-offset = <0x10000>; |
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| 911 | + fsl,dma-queues = <2>; |
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| 912 | + status-sizes = <64>; |
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| 913 | + queue-sizes = <64 64>; |
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| 914 | + big-endian; |
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| 915 | + }; |
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| 916 | + |
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| 917 | + rcpm: power-controller@1ee2140 { |
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| 918 | + compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+"; |
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| 919 | + reg = <0x0 0x1ee2140 0x0 0x4>; |
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| 920 | + #fsl,rcpm-wakeup-cells = <1>; |
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| 921 | + }; |
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| 922 | + |
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| 923 | + ftm_alarm0: timer@29d0000 { |
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| 924 | + compatible = "fsl,ls1043a-ftm-alarm"; |
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| 925 | + reg = <0x0 0x29d0000 0x0 0x10000>; |
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| 926 | + fsl,rcpm-wakeup = <&rcpm 0x20000>; |
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| 927 | + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
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| 928 | + big-endian; |
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737 | 929 | }; |
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738 | 930 | }; |
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739 | 931 | |
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