.. | .. |
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1 | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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2 | 2 | /* |
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3 | | - * Device Tree Include file for Freescale Layerscape-1012A family SoC. |
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| 3 | + * Device Tree Include file for NXP Layerscape-1012A family SoC. |
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4 | 4 | * |
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5 | 5 | * Copyright 2016 Freescale Semiconductor, Inc. |
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| 6 | + * Copyright 2019-2020 NXP |
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6 | 7 | * |
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7 | 8 | */ |
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8 | 9 | |
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.. | .. |
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17 | 18 | |
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18 | 19 | aliases { |
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19 | 20 | crypto = &crypto; |
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| 21 | + rtc1 = &ftm_alarm0; |
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20 | 22 | rtic-a = &rtic_a; |
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21 | 23 | rtic-b = &rtic_b; |
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22 | 24 | rtic-c = &rtic_c; |
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.. | .. |
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136 | 138 | #address-cells = <2>; |
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137 | 139 | #size-cells = <2>; |
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138 | 140 | ranges; |
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| 141 | + |
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| 142 | + qspi: spi@1550000 { |
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| 143 | + compatible = "fsl,ls1021a-qspi"; |
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| 144 | + #address-cells = <1>; |
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| 145 | + #size-cells = <0>; |
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| 146 | + reg = <0x0 0x1550000 0x0 0x10000>, |
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| 147 | + <0x0 0x40000000 0x0 0x10000000>; |
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| 148 | + reg-names = "QuadSPI", "QuadSPI-memory"; |
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| 149 | + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
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| 150 | + clock-names = "qspi_en", "qspi"; |
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| 151 | + clocks = <&clockgen 4 0>, <&clockgen 4 0>; |
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| 152 | + status = "disabled"; |
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| 153 | + }; |
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139 | 154 | |
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140 | 155 | esdhc0: esdhc@1560000 { |
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141 | 156 | compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; |
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.. | .. |
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324 | 339 | #size-cells = <0>; |
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325 | 340 | reg = <0x0 0x2180000 0x0 0x10000>; |
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326 | 341 | interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
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327 | | - clocks = <&clockgen 4 0>; |
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| 342 | + clocks = <&clockgen 4 3>; |
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328 | 343 | status = "disabled"; |
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329 | 344 | }; |
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330 | 345 | |
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.. | .. |
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334 | 349 | #size-cells = <0>; |
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335 | 350 | reg = <0x0 0x2190000 0x0 0x10000>; |
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336 | 351 | interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
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337 | | - clocks = <&clockgen 4 0>; |
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| 352 | + clocks = <&clockgen 4 3>; |
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338 | 353 | status = "disabled"; |
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339 | 354 | }; |
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340 | 355 | |
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.. | .. |
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447 | 462 | dr_mode = "host"; |
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448 | 463 | snps,quirk-frame-length-adjustment = <0x20>; |
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449 | 464 | snps,dis_rxdet_inp3_quirk; |
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| 465 | + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; |
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450 | 466 | }; |
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451 | 467 | |
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452 | 468 | sata: sata@3200000 { |
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.. | .. |
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475 | 491 | interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; |
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476 | 492 | }; |
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477 | 493 | |
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478 | | - pcie@3400000 { |
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479 | | - compatible = "fsl,ls1012a-pcie", "snps,dw-pcie"; |
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| 494 | + pcie1: pcie@3400000 { |
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| 495 | + compatible = "fsl,ls1012a-pcie"; |
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480 | 496 | reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ |
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481 | 497 | 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ |
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482 | 498 | reg-names = "regs", "config"; |
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.. | .. |
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486 | 502 | #address-cells = <3>; |
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487 | 503 | #size-cells = <2>; |
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488 | 504 | device_type = "pci"; |
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489 | | - num-lanes = <4>; |
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| 505 | + num-viewport = <2>; |
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490 | 506 | bus-range = <0x0 0xff>; |
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491 | 507 | ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ |
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492 | 508 | 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
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.. | .. |
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497 | 513 | <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, |
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498 | 514 | <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, |
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499 | 515 | <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; |
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| 516 | + status = "disabled"; |
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| 517 | + }; |
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| 518 | + |
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| 519 | + rcpm: power-controller@1ee2140 { |
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| 520 | + compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+"; |
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| 521 | + reg = <0x0 0x1ee2140 0x0 0x4>; |
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| 522 | + #fsl,rcpm-wakeup-cells = <1>; |
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| 523 | + }; |
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| 524 | + |
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| 525 | + ftm_alarm0: timer@29d0000 { |
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| 526 | + compatible = "fsl,ls1012a-ftm-alarm"; |
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| 527 | + reg = <0x0 0x29d0000 0x0 0x10000>; |
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| 528 | + fsl,rcpm-wakeup = <&rcpm 0x20000>; |
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| 529 | + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
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| 530 | + big-endian; |
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500 | 531 | }; |
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501 | 532 | }; |
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502 | 533 | |
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