add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
..
..
@@ -232,37 +232,152 @@
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 		};
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 	};
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-Stratix10 SoCFPGA ECC Manager
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+Stratix10 SoCFPGA ECC Manager (ARM64)
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 The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
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-in a shared register similar to the Arria10. However, ECC requires
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-access to registers that can only be read from Secure Monitor with
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-SMC calls. Therefore the device tree is slightly different.
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+in a shared register similar to the Arria10. However, Stratix10 ECC
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+requires access to registers that can only be read from Secure Monitor
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+with SMC calls. Therefore the device tree is slightly different. Note
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+that only 1 interrupt is sent in Stratix10 because the double bit errors
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+are treated as SErrors in ARM64 instead of IRQs in ARM32.
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 Required Properties:
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 - compatible : Should be "altr,socfpga-s10-ecc-manager"
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-- interrupts : Should be single bit error interrupt, then double bit error
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-	interrupt.
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+- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
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+	              containing the ECC manager registers.
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+- interrupts : Should be single bit error interrupt.
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 - interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
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 - #interrupt-cells : must be set to 2.
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+- #address-cells: must be 1
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+- #size-cells: must be 1
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+- ranges : standard definition, should translate from local addresses
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253
 
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 Subcomponents:
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 SDRAM ECC
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 Required Properties:
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 - compatible : Should be "altr,sdram-edac-s10"
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-- interrupts : Should be single bit error interrupt, then double bit error
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-	interrupt, in this order.
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+- interrupts : Should be single bit error interrupt.
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+
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+On-Chip RAM ECC
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+Required Properties:
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+- compatible      : Should be "altr,socfpga-s10-ocram-ecc"
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+- reg             : Address and size for ECC block registers.
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+- altr,ecc-parent : phandle to parent OCRAM node.
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+- interrupts      : Should be single bit error interrupt.
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+
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+Ethernet FIFO ECC
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+Required Properties:
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+- compatible      : Should be "altr,socfpga-s10-eth-mac-ecc"
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+- reg             : Address and size for ECC block registers.
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+- altr,ecc-parent : phandle to parent Ethernet node.
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+- interrupts      : Should be single bit error interrupt.
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+
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+NAND FIFO ECC
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+Required Properties:
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+- compatible      : Should be "altr,socfpga-s10-nand-ecc"
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+- reg             : Address and size for ECC block registers.
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+- altr,ecc-parent : phandle to parent NAND node.
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+- interrupts      : Should be single bit error interrupt.
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+
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+DMA FIFO ECC
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+Required Properties:
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+- compatible      : Should be "altr,socfpga-s10-dma-ecc"
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+- reg             : Address and size for ECC block registers.
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+- altr,ecc-parent : phandle to parent DMA node.
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+- interrupts      : Should be single bit error interrupt.
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+
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+USB FIFO ECC
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+Required Properties:
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+- compatible      : Should be "altr,socfpga-s10-usb-ecc"
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+- reg             : Address and size for ECC block registers.
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+- altr,ecc-parent : phandle to parent USB node.
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+- interrupts      : Should be single bit error interrupt.
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+
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+SDMMC FIFO ECC
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+Required Properties:
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+- compatible      : Should be "altr,socfpga-s10-sdmmc-ecc"
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+- reg             : Address and size for ECC block registers.
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+- altr,ecc-parent : phandle to parent SD/MMC node.
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+- interrupts      : Should be single bit error interrupt for port A
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+		    and then single bit error interrupt for port B.
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 Example:
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 	eccmgr {
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 		compatible = "altr,socfpga-s10-ecc-manager";
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-		interrupts = <0 15 4>, <0 95 4>;
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+		altr,sysmgr-syscon = <&sysmgr>;
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+		#address-cells = <1>;
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+		#size-cells = <1>;
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+		interrupts = <0 15 4>;
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 		interrupt-controller;
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 		#interrupt-cells = <2>;
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+		ranges;
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 		sdramedac {
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 			compatible = "altr,sdram-edac-s10";
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-			interrupts = <16 4>, <48 4>;
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+			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
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+		};
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+
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+		ocram-ecc@ff8cc000 {
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+			compatible = "altr,socfpga-s10-ocram-ecc";
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+			reg = <ff8cc000 0x100>;
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+			altr,ecc-parent = <&ocram>;
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+			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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+		};
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+
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+		emac0-rx-ecc@ff8c0000 {
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+			compatible = "altr,socfpga-s10-eth-mac-ecc";
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+			reg = <0xff8c0000 0x100>;
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+			altr,ecc-parent = <&gmac0>;
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+			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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+		};
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+
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+		emac0-tx-ecc@ff8c0400 {
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+			compatible = "altr,socfpga-s10-eth-mac-ecc";
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+			reg = <0xff8c0400 0x100>;
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+			altr,ecc-parent = <&gmac0>;
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+			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
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+		};
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+
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+		nand-buf-ecc@ff8c8000 {
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+			compatible = "altr,socfpga-s10-nand-ecc";
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+			reg = <0xff8c8000 0x100>;
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+			altr,ecc-parent = <&nand>;
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+			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
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+		};
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+
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+		nand-rd-ecc@ff8c8400 {
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+			compatible = "altr,socfpga-s10-nand-ecc";
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+			reg = <0xff8c8400 0x100>;
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+			altr,ecc-parent = <&nand>;
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+			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
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+		};
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+
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+		nand-wr-ecc@ff8c8800 {
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+			compatible = "altr,socfpga-s10-nand-ecc";
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+			reg = <0xff8c8800 0x100>;
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+			altr,ecc-parent = <&nand>;
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+			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
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+		};
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+
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+		dma-ecc@ff8c9000 {
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+			compatible = "altr,socfpga-s10-dma-ecc";
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+			reg = <0xff8c9000 0x100>;
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+			altr,ecc-parent = <&pdma>;
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+			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
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+
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+		usb0-ecc@ff8c4000 {
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+			compatible = "altr,socfpga-s10-usb-ecc";
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+			reg = <0xff8c4000 0x100>;
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+			altr,ecc-parent = <&usb0>;
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+			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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+		};
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+
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+		sdmmc-ecc@ff8c8c00 {
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+			compatible = "altr,socfpga-s10-sdmmc-ecc";
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+			reg = <0xff8c8c00 0x100>;
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+			altr,ecc-parent = <&mmc>;
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+			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
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+				     <15 IRQ_TYPE_LEVEL_HIGH>;
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 		};
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 	};