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hc
2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/sound/soc/rockchip/rockchip_sai.c
....@@ -27,6 +27,8 @@
2727 #define MAXBURST_PER_FIFO	8
2828 
2929 #define DEFAULT_FS		48000
30
+#define TIMEOUT_US		1000
31
+#define WAIT_TIME_MS_MAX	10000
3032 #define QUIRK_ALWAYS_ON		BIT(0)
3133 
3234 enum fpw_mode {
....@@ -45,6 +47,7 @@
4547 	struct snd_dmaengine_dai_dma_data capture_dma_data;
4648 	struct snd_dmaengine_dai_dma_data playback_dma_data;
4749 	struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1];
50
+	unsigned int wait_time[SNDRV_PCM_STREAM_LAST + 1];
4851 	unsigned int tx_lanes;
4952 	unsigned int rx_lanes;
5053 	unsigned int quirks;
....@@ -54,6 +57,7 @@
5457 	bool has_playback;
5558 	bool is_master_mode;
5659 	bool is_tdm;
60
+	bool is_clk_auto;
5761 };
5862 
5963 static const struct sai_of_quirks {
....@@ -80,11 +84,26 @@
8084 				   SAI_XFER_FSS_DIS);
8185 
8286 	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_XFER, val,
83
-					      (val & SAI_XFER_FS_IDLE), 10, 100);
87
+					      (val & SAI_XFER_FS_IDLE), 10, TIMEOUT_US);
8488 	if (ret < 0)
8589 		dev_warn(sai->dev, "Failed to idle FS\n");
8690 
8791 	regcache_cache_only(sai->regmap, true);
92
+	/*
93
+	 * After FS idle, should wait at least 2 BCLK cycle to make sure
94
+	 * the CLK gate operation done, and then disable mclk.
95
+	 *
96
+	 * Otherwise, the BCLK is still ungated. once the mclk is enabled,
97
+	 * there maybe a risk that a few BCLK cycle leak. especially for
98
+	 * low speed situation, such as 8k samplerate.
99
+	 *
100
+	 * The best way is to use delay per samplerate, but, the max time
101
+	 * is quite a tiny value, so, let's make it simple to use the max
102
+	 * time.
103
+	 *
104
+	 * The max BCLK cycle time is: 31us @ 8K-8Bit (64K BCLK)
105
+	 */
106
+	udelay(40);
88107 	clk_disable_unprepare(sai->mclk);
89108 	clk_disable_unprepare(sai->hclk);
90109 
....@@ -110,7 +129,7 @@
110129 	if (ret)
111130 		goto err_regmap;
112131 
113
-	if (sai->is_master_mode)
132
+	if (sai->quirks & QUIRK_ALWAYS_ON && sai->is_master_mode)
114133 		regmap_update_bits(sai->regmap, SAI_XFER,
115134 				   SAI_XFER_CLK_MASK |
116135 				   SAI_XFER_FSS_MASK,
....@@ -203,7 +222,7 @@
203222 
204223 	regmap_update_bits(sai->regmap, SAI_CLR, clr, clr);
205224 	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_CLR, val,
206
-					      !(val & clr), 10, 100);
225
+					      !(val & clr), 10, TIMEOUT_US);
207226 	if (ret < 0) {
208227 		dev_warn(sai->dev, "Failed to clear %u\n", clr);
209228 		goto reset;
....@@ -249,7 +268,7 @@
249268 
250269 	regmap_update_bits(sai->regmap, SAI_XFER, msk, val);
251270 	ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_XFER, val,
252
-					      (val & idle), 10, 100);
271
+					      (val & idle), 10, TIMEOUT_US);
253272 	if (ret < 0)
254273 		dev_warn(sai->dev, "Failed to idle stream %d\n", stream);
255274 
....@@ -433,6 +452,7 @@
433452 		val = SAI_XCR_VDW(24);
434453 		break;
435454 	case SNDRV_PCM_FORMAT_S32_LE:
455
+	case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
436456 		val = SAI_XCR_VDW(32);
437457 		break;
438458 	default:
....@@ -473,6 +493,8 @@
473493 
474494 	if (sai->is_master_mode) {
475495 		bclk_rate = sai->fw_ratio * slot_width * ch_per_lane * params_rate(params);
496
+		if (sai->is_clk_auto)
497
+			clk_set_rate(sai->mclk, bclk_rate);
476498 		mclk_rate = clk_get_rate(sai->mclk);
477499 		if (mclk_rate < bclk_rate) {
478500 			dev_err(sai->dev, "Mismatch mclk: %u, expected %u at least\n",
....@@ -484,6 +506,22 @@
484506 
485507 		regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
486508 				   SAI_CKR_MDIV(div_bclk));
509
+		/*
510
+		 * Should wait for one BCLK ready after DIV and then ungate
511
+		 * output clk to achieve the clean clk.
512
+		 *
513
+		 * The best way is to use delay per samplerate, but, the max time
514
+		 * is quite a tiny value, so, let's make it simple to use the max
515
+		 * time.
516
+		 *
517
+		 * The max BCLK cycle time is: 15.6us @ 8K-8Bit (64K BCLK)
518
+		 */
519
+		udelay(20);
520
+		regmap_update_bits(sai->regmap, SAI_XFER,
521
+				   SAI_XFER_CLK_MASK |
522
+				   SAI_XFER_FSS_MASK,
523
+				   SAI_XFER_CLK_EN |
524
+				   SAI_XFER_FSS_EN);
487525 	}
488526 
489527 	return 0;
....@@ -520,7 +558,7 @@
520558 	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
521559 	int ret;
522560 
523
-	if (!freq)
561
+	if (!freq || sai->is_clk_auto)
524562 		return 0;
525563 
526564 	ret = clk_set_rate(sai->mclk, freq);
....@@ -545,11 +583,15 @@
545583 				    struct snd_soc_dai *dai)
546584 {
547585 	struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
586
+	int stream = substream->stream;
548587 
549
-	if (sai->substreams[substream->stream])
588
+	if (sai->substreams[stream])
550589 		return -EBUSY;
551590 
552
-	sai->substreams[substream->stream] = substream;
591
+	if (sai->wait_time[stream])
592
+		substream->wait_time = msecs_to_jiffies(sai->wait_time[stream]);
593
+
594
+	sai->substreams[stream] = substream;
553595 
554596 	return 0;
555597 }
....@@ -746,7 +788,8 @@
746788 		dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
747789 					SNDRV_PCM_FMTBIT_S16_LE |
748790 					SNDRV_PCM_FMTBIT_S24_LE |
749
-					SNDRV_PCM_FMTBIT_S32_LE;
791
+					SNDRV_PCM_FMTBIT_S32_LE |
792
+					SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
750793 
751794 		sai->playback_dma_data.addr = res->start + SAI_TXDR;
752795 		sai->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
....@@ -761,7 +804,8 @@
761804 		dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
762805 				       SNDRV_PCM_FMTBIT_S16_LE |
763806 				       SNDRV_PCM_FMTBIT_S24_LE |
764
-				       SNDRV_PCM_FMTBIT_S32_LE;
807
+				       SNDRV_PCM_FMTBIT_S32_LE |
808
+				       SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE;
765809 
766810 		sai->capture_dma_data.addr = res->start + SAI_RXDR;
767811 		sai->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
....@@ -794,8 +838,8 @@
794838 static const char * const vdj_text[] = { "Right J", "Left J" };
795839 
796840 static const char * const sbw_text[] = {
797
-	" 0", " 0", " 0", " 0", " 0", " 0", " 0", " 8",
798
-	" 9", "10", "11", "12", "13", "14", "15", "16",
841
+	 "0",  "0",  "0",  "0",  "0",  "0",  "0",  "8",
842
+	 "9", "10", "11", "12", "13", "14", "15", "16",
799843 	"17", "18", "19", "20", "21", "22", "23", "24",
800844 	"25", "26", "27", "28", "29", "30", "31", "32", };
801845 
....@@ -803,7 +847,7 @@
803847 
804848 static DECLARE_TLV_DB_SCALE(rmss_tlv, 0, 128, 0);
805849 
806
-static const char * const mss_text[] = { "Master", "Slave" };
850
+static const char * const mss_text[] = { "Slave", "Master" };
807851 
808852 static const char * const ckp_text[] = { "Normal", "Inverted" };
809853 
....@@ -850,7 +894,8 @@
850894 static SOC_ENUM_SINGLE_DECL(tmono_switch, SAI_MONO_CR, 0, mono_text);
851895 
852896 /* CKR */
853
-static SOC_ENUM_SINGLE_DECL(mss_switch, SAI_CKR, 2, mss_text);
897
+static const struct soc_enum mss_switch =
898
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mss_text), mss_text);
854899 static SOC_ENUM_SINGLE_DECL(sp_switch,  SAI_CKR, 1, ckp_text);
855900 static SOC_ENUM_SINGLE_DECL(fp_switch,  SAI_CKR, 0, ckp_text);
856901 
....@@ -981,6 +1026,154 @@
9811026 	return 1;
9821027 }
9831028 
1029
+static int rockchip_sai_mss_get(struct snd_kcontrol *kcontrol,
1030
+				struct snd_ctl_elem_value *ucontrol)
1031
+{
1032
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1033
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1034
+
1035
+	ucontrol->value.enumerated.item[0] = sai->is_master_mode;
1036
+
1037
+	return 0;
1038
+}
1039
+
1040
+static int rockchip_sai_mss_put(struct snd_kcontrol *kcontrol,
1041
+				struct snd_ctl_elem_value *ucontrol)
1042
+{
1043
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1044
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1045
+	bool mss;
1046
+
1047
+	/* MUST: do not update mode while stream is running */
1048
+	if (snd_soc_component_active(component))
1049
+		return -EPERM;
1050
+
1051
+	mss = !!ucontrol->value.enumerated.item[0];
1052
+	if (mss == sai->is_master_mode)
1053
+		return 0;
1054
+
1055
+	sai->is_master_mode = mss;
1056
+
1057
+	pm_runtime_get_sync(sai->dev);
1058
+	if (sai->is_master_mode) {
1059
+		/* Switch from Slave to Master */
1060
+		regmap_update_bits(sai->regmap, SAI_CKR,
1061
+				   SAI_CKR_MSS_MASK,
1062
+				   SAI_CKR_MSS_MASTER);
1063
+		regmap_update_bits(sai->regmap, SAI_XFER,
1064
+				   SAI_XFER_CLK_MASK |
1065
+				   SAI_XFER_FSS_MASK,
1066
+				   SAI_XFER_CLK_EN |
1067
+				   SAI_XFER_FSS_EN);
1068
+	} else {
1069
+		/* Switch from Master to Slave */
1070
+		regmap_update_bits(sai->regmap, SAI_CKR,
1071
+				   SAI_CKR_MSS_MASK,
1072
+				   SAI_CKR_MSS_SLAVE);
1073
+		regmap_update_bits(sai->regmap, SAI_XFER,
1074
+				   SAI_XFER_CLK_MASK |
1075
+				   SAI_XFER_FSS_MASK,
1076
+				   SAI_XFER_CLK_DIS |
1077
+				   SAI_XFER_FSS_DIS);
1078
+	}
1079
+	pm_runtime_put(sai->dev);
1080
+
1081
+	return 1;
1082
+}
1083
+
1084
+static int rockchip_sai_clk_auto_get(struct snd_kcontrol *kcontrol,
1085
+				     struct snd_ctl_elem_value *ucontrol)
1086
+{
1087
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1088
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1089
+
1090
+	ucontrol->value.integer.value[0] = sai->is_clk_auto;
1091
+
1092
+	return 0;
1093
+}
1094
+
1095
+static int rockchip_sai_clk_auto_put(struct snd_kcontrol *kcontrol,
1096
+				     struct snd_ctl_elem_value *ucontrol)
1097
+{
1098
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1099
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1100
+	bool clk_auto = ucontrol->value.integer.value[0];
1101
+
1102
+	if (clk_auto == sai->is_clk_auto)
1103
+		return 0;
1104
+
1105
+	sai->is_clk_auto = clk_auto;
1106
+
1107
+	return 1;
1108
+}
1109
+
1110
+static int rockchip_sai_wait_time_info(struct snd_kcontrol *kcontrol,
1111
+				       struct snd_ctl_elem_info *uinfo)
1112
+{
1113
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1114
+	uinfo->count = 1;
1115
+	uinfo->value.integer.min = 0;
1116
+	uinfo->value.integer.max = WAIT_TIME_MS_MAX;
1117
+	uinfo->value.integer.step = 1;
1118
+
1119
+	return 0;
1120
+}
1121
+
1122
+static int rockchip_sai_rd_wait_time_get(struct snd_kcontrol *kcontrol,
1123
+					 struct snd_ctl_elem_value *ucontrol)
1124
+{
1125
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1126
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1127
+
1128
+	ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_CAPTURE];
1129
+
1130
+	return 0;
1131
+}
1132
+
1133
+static int rockchip_sai_rd_wait_time_put(struct snd_kcontrol *kcontrol,
1134
+					 struct snd_ctl_elem_value *ucontrol)
1135
+{
1136
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1137
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1138
+
1139
+	if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
1140
+		return -EINVAL;
1141
+
1142
+	sai->wait_time[SNDRV_PCM_STREAM_CAPTURE] = ucontrol->value.integer.value[0];
1143
+
1144
+	return 1;
1145
+}
1146
+
1147
+static int rockchip_sai_wr_wait_time_get(struct snd_kcontrol *kcontrol,
1148
+					 struct snd_ctl_elem_value *ucontrol)
1149
+{
1150
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1151
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1152
+
1153
+	ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK];
1154
+
1155
+	return 0;
1156
+}
1157
+
1158
+static int rockchip_sai_wr_wait_time_put(struct snd_kcontrol *kcontrol,
1159
+					 struct snd_ctl_elem_value *ucontrol)
1160
+{
1161
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1162
+	struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component);
1163
+
1164
+	if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX)
1165
+		return -EINVAL;
1166
+
1167
+	sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK] = ucontrol->value.integer.value[0];
1168
+
1169
+	return 1;
1170
+}
1171
+
1172
+#define SAI_PCM_WAIT_TIME(xname, xhandler_get, xhandler_put)	\
1173
+{	.iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname,	\
1174
+	.info = rockchip_sai_wait_time_info,			\
1175
+	.get = xhandler_get, .put = xhandler_put }
1176
+
9841177 static DECLARE_TLV_DB_SCALE(fs_shift_tlv, 0, 8192, 0);
9851178 
9861179 static const struct snd_kcontrol_new rockchip_sai_controls[] = {
....@@ -1012,7 +1205,8 @@
10121205 	SOC_ENUM("Receive Mono Switch", rmono_switch),
10131206 	SOC_ENUM("Transmit Mono Switch", tmono_switch),
10141207 
1015
-	SOC_ENUM("Master / Slave Mode Select", mss_switch),
1208
+	SOC_ENUM_EXT("Master / Slave Mode Select", mss_switch,
1209
+		     rockchip_sai_mss_get, rockchip_sai_mss_put),
10161210 	SOC_ENUM("Sclk Polarity", sp_switch),
10171211 	SOC_ENUM("Frame Sync Polarity", fp_switch),
10181212 
....@@ -1039,6 +1233,17 @@
10391233 		       0, 8192, 0, fs_shift_tlv),
10401234 	SOC_SINGLE_TLV("Receive Frame Shift Select", SAI_RX_SHIFT,
10411235 		       0, 8192, 0, fs_shift_tlv),
1236
+
1237
+	SOC_SINGLE_BOOL_EXT("Clk Auto Switch", 0,
1238
+			    rockchip_sai_clk_auto_get,
1239
+			    rockchip_sai_clk_auto_put),
1240
+
1241
+	SAI_PCM_WAIT_TIME("PCM Read Wait Time MS",
1242
+			  rockchip_sai_rd_wait_time_get,
1243
+			  rockchip_sai_rd_wait_time_put),
1244
+	SAI_PCM_WAIT_TIME("PCM Write Wait Time MS",
1245
+			  rockchip_sai_wr_wait_time_get,
1246
+			  rockchip_sai_wr_wait_time_put),
10421247 };
10431248 
10441249 static const struct snd_soc_component_driver rockchip_sai_component = {
....@@ -1110,7 +1315,7 @@
11101315 	int ret = 0, i = 0;
11111316 
11121317 	for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
1113
-		if (of_property_read_bool(sai->dev->of_node, of_quirks[i].quirk))
1318
+		if (device_property_read_bool(sai->dev, of_quirks[i].quirk))
11141319 			sai->quirks |= of_quirks[i].id;
11151320 
11161321 	if (sai->quirks & QUIRK_ALWAYS_ON)
....@@ -1134,6 +1339,8 @@
11341339 
11351340 	sai->dev = &pdev->dev;
11361341 	sai->fw_ratio = 1;
1342
+	/* match to register default */
1343
+	sai->is_master_mode = true;
11371344 	dev_set_drvdata(&pdev->dev, sai);
11381345 
11391346 	sai->rst_h = devm_reset_control_get_optional_exclusive(&pdev->dev, "h");
....@@ -1153,7 +1360,7 @@
11531360 	if (IS_ERR(sai->regmap))
11541361 		return PTR_ERR(sai->regmap);
11551362 
1156
-	irq = platform_get_irq(pdev, 0);
1363
+	irq = platform_get_irq_optional(pdev, 0);
11571364 	if (irq > 0) {
11581365 		ret = devm_request_irq(&pdev->dev, irq, rockchip_sai_isr,
11591366 				       IRQF_SHARED, node->name, sai);
....@@ -1196,6 +1403,11 @@
11961403 	if (ret)
11971404 		goto err_runtime_suspend;
11981405 
1406
+	if (device_property_read_bool(&pdev->dev, "rockchip,no-dmaengine")) {
1407
+		dev_info(&pdev->dev, "Used for Multi-DAI\n");
1408
+		return 0;
1409
+	}
1410
+
11991411 	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
12001412 	if (ret)
12011413 		goto err_runtime_suspend;
....@@ -1233,13 +1445,10 @@
12331445 static int rockchip_sai_resume(struct device *dev)
12341446 {
12351447 	struct rk_sai_dev *sai = dev_get_drvdata(dev);
1236
-	int ret = pm_runtime_get_sync(dev);
1448
+	int ret = pm_runtime_resume_and_get(dev);
12371449 
1238
-	if (ret < 0) {
1239
-		pm_runtime_put_noidle(dev);
1450
+	if (ret < 0)
12401451 		return ret;
1241
-	}
1242
-
12431452 	ret = regcache_sync(sai->regmap);
12441453 	pm_runtime_put(dev);
12451454