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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d 
 kernel/include/uapi/gpu/arm/bifrost/gpu/backend/mali_kbase_gpu_regmap_csf.h
....@@ -1,7 +1,7 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
22 /*
33  *
4
- * (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
4
+ * (C) COPYRIGHT 2022 ARM Limited. All rights reserved.
55  *
66  * This program is free software and is provided to you under the terms of the
77  * GNU General Public License version 2 as published by the Free Software
....@@ -22,314 +22,20 @@
2222 #ifndef _UAPI_KBASE_GPU_REGMAP_CSF_H_
2323 #define _UAPI_KBASE_GPU_REGMAP_CSF_H_
2424 
25
-#include <linux/types.h>
26
-
27
-#if !MALI_USE_CSF && defined(__KERNEL__)
28
-#error "Cannot be compiled with JM"
29
-#endif
30
-
3125 /* IPA control registers */
26
+#define IPA_CONTROL_BASE 0x40000
27
+#define IPA_CONTROL_REG(r) (IPA_CONTROL_BASE + (r))
28
+#define STATUS 0x004 /* (RO) Status register */
3229 
33
-#define IPA_CONTROL_BASE       0x40000
34
-#define IPA_CONTROL_REG(r)     (IPA_CONTROL_BASE+(r))
35
-#define COMMAND                0x000 /* (WO) Command register */
36
-#define STATUS                 0x004 /* (RO) Status register */
37
-#define TIMER                  0x008 /* (RW) Timer control register */
30
+/* USER base address */
31
+#define USER_BASE 0x0010000
32
+#define USER_REG(r) (USER_BASE + (r))
3833 
39
-#define SELECT_CSHW_LO         0x010 /* (RW) Counter select for CS hardware, low word */
40
-#define SELECT_CSHW_HI         0x014 /* (RW) Counter select for CS hardware, high word */
41
-#define SELECT_MEMSYS_LO       0x018 /* (RW) Counter select for Memory system, low word */
42
-#define SELECT_MEMSYS_HI       0x01C /* (RW) Counter select for Memory system, high word */
43
-#define SELECT_TILER_LO        0x020 /* (RW) Counter select for Tiler cores, low word */
44
-#define SELECT_TILER_HI        0x024 /* (RW) Counter select for Tiler cores, high word */
45
-#define SELECT_SHADER_LO       0x028 /* (RW) Counter select for Shader cores, low word */
46
-#define SELECT_SHADER_HI       0x02C /* (RW) Counter select for Shader cores, high word */
34
+/* USER register offsets */
35
+#define LATEST_FLUSH 0x0000 /* () Flush ID of latest clean-and-invalidate operation */
4736 
48
-/* Accumulated counter values for CS hardware */
49
-#define VALUE_CSHW_BASE        0x100
50
-#define VALUE_CSHW_REG_LO(n)   (VALUE_CSHW_BASE + ((n) << 3))       /* (RO) Counter value #n, low word */
51
-#define VALUE_CSHW_REG_HI(n)   (VALUE_CSHW_BASE + ((n) << 3) + 4)   /* (RO) Counter value #n, high word */
52
-
53
-/* Accumulated counter values for memory system */
54
-#define VALUE_MEMSYS_BASE      0x140
55
-#define VALUE_MEMSYS_REG_LO(n) (VALUE_MEMSYS_BASE + ((n) << 3))     /* (RO) Counter value #n, low word */
56
-#define VALUE_MEMSYS_REG_HI(n) (VALUE_MEMSYS_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */
57
-
58
-#define VALUE_TILER_BASE       0x180
59
-#define VALUE_TILER_REG_LO(n)  (VALUE_TILER_BASE + ((n) << 3))      /* (RO) Counter value #n, low word */
60
-#define VALUE_TILER_REG_HI(n)  (VALUE_TILER_BASE + ((n) << 3) + 4)  /* (RO) Counter value #n, high word */
61
-
62
-#define VALUE_SHADER_BASE      0x1C0
63
-#define VALUE_SHADER_REG_LO(n) (VALUE_SHADER_BASE + ((n) << 3))     /* (RO) Counter value #n, low word */
64
-#define VALUE_SHADER_REG_HI(n) (VALUE_SHADER_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */
65
-
66
-#include "../../csf/mali_gpu_csf_control_registers.h"
67
-
68
-/* Set to implementation defined, outer caching */
69
-#define AS_MEMATTR_AARCH64_OUTER_IMPL_DEF 0x88ull
70
-/* Set to write back memory, outer caching */
71
-#define AS_MEMATTR_AARCH64_OUTER_WA       0x8Dull
72
-/* Set to inner non-cacheable, outer-non-cacheable
73
- * Setting defined by the alloc bits is ignored, but set to a valid encoding:
74
- * - no-alloc on read
75
- * - no alloc on write
76
- */
77
-#define AS_MEMATTR_AARCH64_NON_CACHEABLE  0x4Cull
78
-/* Set to shared memory, that is inner cacheable on ACE and inner or outer
79
- * shared, otherwise inner non-cacheable.
80
- * Outer cacheable if inner or outer shared, otherwise outer non-cacheable.
81
- */
82
-#define AS_MEMATTR_AARCH64_SHARED         0x8ull
83
-
84
-/* Symbols for default MEMATTR to use
85
- * Default is - HW implementation defined caching
86
- */
87
-#define AS_MEMATTR_INDEX_DEFAULT               0
88
-#define AS_MEMATTR_INDEX_DEFAULT_ACE           3
89
-
90
-/* HW implementation defined caching */
91
-#define AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY 0
92
-/* Force cache on */
93
-#define AS_MEMATTR_INDEX_FORCE_TO_CACHE_ALL    1
94
-/* Write-alloc */
95
-#define AS_MEMATTR_INDEX_WRITE_ALLOC           2
96
-/* Outer coherent, inner implementation defined policy */
97
-#define AS_MEMATTR_INDEX_OUTER_IMPL_DEF        3
98
-/* Outer coherent, write alloc inner */
99
-#define AS_MEMATTR_INDEX_OUTER_WA              4
100
-/* Normal memory, inner non-cacheable, outer non-cacheable (ARMv8 mode only) */
101
-#define AS_MEMATTR_INDEX_NON_CACHEABLE         5
102
-/* Normal memory, shared between MCU and Host */
103
-#define AS_MEMATTR_INDEX_SHARED                6
104
-
105
-/* Configuration bits for the CSF. */
106
-#define CSF_CONFIG 0xF00
107
-
108
-/* CSF_CONFIG register */
109
-#define CSF_CONFIG_FORCE_COHERENCY_FEATURES_SHIFT 2
110
-
111
-/* GPU control registers */
112
-#define CORE_FEATURES           0x008   /* () Shader Core Features */
113
-#define MCU_CONTROL             0x700
114
-#define MCU_STATUS              0x704
115
-
116
-#define MCU_CNTRL_ENABLE        (1 << 0)
117
-#define MCU_CNTRL_AUTO          (1 << 1)
118
-#define MCU_CNTRL_DISABLE       (0)
119
-
120
-#define MCU_STATUS_HALTED        (1 << 1)
121
-
122
-#define PRFCNT_BASE_LO   0x060  /* (RW) Performance counter memory
123
-				 * region base address, low word
124
-				 */
125
-#define PRFCNT_BASE_HI   0x064  /* (RW) Performance counter memory
126
-				 * region base address, high word
127
-				 */
128
-#define PRFCNT_CONFIG    0x068  /* (RW) Performance counter
129
-				 * configuration
130
-				 */
131
-
132
-#define PRFCNT_CSHW_EN   0x06C  /* (RW) Performance counter
133
-				 * enable for CS Hardware
134
-				 */
135
-
136
-#define PRFCNT_SHADER_EN 0x070  /* (RW) Performance counter enable
137
-				 * flags for shader cores
138
-				 */
139
-#define PRFCNT_TILER_EN  0x074  /* (RW) Performance counter enable
140
-				 * flags for tiler
141
-				 */
142
-#define PRFCNT_MMU_L2_EN 0x07C  /* (RW) Performance counter enable
143
-				 * flags for MMU/L2 cache
144
-				 */
145
-
146
-/* JOB IRQ flags */
147
-#define JOB_IRQ_GLOBAL_IF       (1 << 31)   /* Global interface interrupt received */
148
-
149
-/* GPU_COMMAND codes */
150
-#define GPU_COMMAND_CODE_NOP                0x00 /* No operation, nothing happens */
151
-#define GPU_COMMAND_CODE_RESET              0x01 /* Reset the GPU */
152
-#define GPU_COMMAND_CODE_PRFCNT             0x02 /* Clear or sample performance counters */
153
-#define GPU_COMMAND_CODE_TIME               0x03 /* Configure time sources */
154
-#define GPU_COMMAND_CODE_FLUSH_CACHES       0x04 /* Flush caches */
155
-#define GPU_COMMAND_CODE_SET_PROTECTED_MODE 0x05 /* Places the GPU in protected mode */
156
-#define GPU_COMMAND_CODE_FINISH_HALT        0x06 /* Halt CSF */
157
-#define GPU_COMMAND_CODE_CLEAR_FAULT        0x07 /* Clear GPU_FAULTSTATUS and GPU_FAULTADDRESS, TODX */
158
-
159
-/* GPU_COMMAND_RESET payloads */
160
-
161
-/* This will leave the state of active jobs UNDEFINED, but will leave the external bus in a defined and idle state.
162
- * Power domains will remain powered on.
163
- */
164
-#define GPU_COMMAND_RESET_PAYLOAD_FAST_RESET 0x00
165
-
166
-/* This will leave the state of active CSs UNDEFINED, but will leave the external bus in a defined and
167
- * idle state.
168
- */
169
-#define GPU_COMMAND_RESET_PAYLOAD_SOFT_RESET 0x01
170
-
171
-/* This reset will leave the state of currently active streams UNDEFINED, will likely lose data, and may leave
172
- * the system bus in an inconsistent state. Use only as a last resort when nothing else works.
173
- */
174
-#define GPU_COMMAND_RESET_PAYLOAD_HARD_RESET 0x02
175
-
176
-/* GPU_COMMAND_PRFCNT payloads */
177
-#define GPU_COMMAND_PRFCNT_PAYLOAD_SAMPLE 0x01 /* Sample performance counters */
178
-#define GPU_COMMAND_PRFCNT_PAYLOAD_CLEAR  0x02 /* Clear performance counters */
179
-
180
-/* GPU_COMMAND_TIME payloads */
181
-#define GPU_COMMAND_TIME_DISABLE 0x00 /* Disable cycle counter */
182
-#define GPU_COMMAND_TIME_ENABLE  0x01 /* Enable cycle counter */
183
-
184
-/* GPU_COMMAND_FLUSH_CACHES payloads */
185
-#define GPU_COMMAND_FLUSH_PAYLOAD_NONE             0x00 /* No flush */
186
-#define GPU_COMMAND_FLUSH_PAYLOAD_CLEAN            0x01 /* Clean the caches */
187
-#define GPU_COMMAND_FLUSH_PAYLOAD_INVALIDATE       0x02 /* Invalidate the caches */
188
-#define GPU_COMMAND_FLUSH_PAYLOAD_CLEAN_INVALIDATE 0x03 /* Clean and invalidate the caches */
189
-
190
-/* GPU_COMMAND command + payload */
191
-#define GPU_COMMAND_CODE_PAYLOAD(opcode, payload) \
192
-	((__u32)opcode | ((__u32)payload << 8))
193
-
194
-/* Final GPU_COMMAND form */
195
-/* No operation, nothing happens */
196
-#define GPU_COMMAND_NOP \
197
-	GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_NOP, 0)
198
-
199
-/* Stop all external bus interfaces, and then reset the entire GPU. */
200
-#define GPU_COMMAND_SOFT_RESET \
201
-	GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_RESET, GPU_COMMAND_RESET_PAYLOAD_SOFT_RESET)
202
-
203
-/* Immediately reset the entire GPU. */
204
-#define GPU_COMMAND_HARD_RESET \
205
-	GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_RESET, GPU_COMMAND_RESET_PAYLOAD_HARD_RESET)
206
-
207
-/* Clear all performance counters, setting them all to zero. */
208
-#define GPU_COMMAND_PRFCNT_CLEAR \
209
-	GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_PRFCNT, GPU_COMMAND_PRFCNT_PAYLOAD_CLEAR)
210
-
211
-/* Sample all performance counters, writing them out to memory */
212
-#define GPU_COMMAND_PRFCNT_SAMPLE \
213
-	GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_PRFCNT, GPU_COMMAND_PRFCNT_PAYLOAD_SAMPLE)
214
-
215
-/* Starts the cycle counter, and system timestamp propagation */
216
-#define GPU_COMMAND_CYCLE_COUNT_START \
217
-	GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_TIME, GPU_COMMAND_TIME_ENABLE)
218
-
219
-/* Stops the cycle counter, and system timestamp propagation */
220
-#define GPU_COMMAND_CYCLE_COUNT_STOP \
221
-	GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_TIME, GPU_COMMAND_TIME_DISABLE)
222
-
223
-/* Clean all caches */
224
-#define GPU_COMMAND_CLEAN_CACHES \
225
-	GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_FLUSH_CACHES, GPU_COMMAND_FLUSH_PAYLOAD_CLEAN)
226
-
227
-/* Clean and invalidate all caches */
228
-#define GPU_COMMAND_CLEAN_INV_CACHES \
229
-	GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_FLUSH_CACHES, GPU_COMMAND_FLUSH_PAYLOAD_CLEAN_INVALIDATE)
230
-
231
-/* Places the GPU in protected mode */
232
-#define GPU_COMMAND_SET_PROTECTED_MODE \
233
-	GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_SET_PROTECTED_MODE, 0)
234
-
235
-/* Halt CSF */
236
-#define GPU_COMMAND_FINISH_HALT \
237
-	GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_FINISH_HALT, 0)
238
-
239
-/* Clear GPU faults */
240
-#define GPU_COMMAND_CLEAR_FAULT \
241
-	GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_CLEAR_FAULT, 0)
242
-
243
-/* End Command Values */
244
-
245
-/* GPU_FAULTSTATUS register */
246
-#define GPU_FAULTSTATUS_EXCEPTION_TYPE_SHIFT 0
247
-#define GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK (0xFFul)
248
-#define GPU_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \
249
-	(((reg_val)&GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK) \
250
-	 >> GPU_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
251
-#define GPU_FAULTSTATUS_ACCESS_TYPE_SHIFT 8
252
-#define GPU_FAULTSTATUS_ACCESS_TYPE_MASK \
253
-	(0x3ul << GPU_FAULTSTATUS_ACCESS_TYPE_SHIFT)
254
-
255
-#define GPU_FAULTSTATUS_ADDR_VALID_SHIFT 10
256
-#define GPU_FAULTSTATUS_ADDR_VALID_FLAG \
257
-	(1ul << GPU_FAULTSTATUS_ADDR_VALID_SHIFT)
258
-
259
-#define GPU_FAULTSTATUS_JASID_VALID_SHIFT 11
260
-#define GPU_FAULTSTATUS_JASID_VALID_FLAG \
261
-	(1ul << GPU_FAULTSTATUS_JASID_VALID_SHIFT)
262
-
263
-#define GPU_FAULTSTATUS_JASID_SHIFT 12
264
-#define GPU_FAULTSTATUS_JASID_MASK (0xF << GPU_FAULTSTATUS_JASID_SHIFT)
265
-#define GPU_FAULTSTATUS_JASID_GET(reg_val) \
266
-	(((reg_val)&GPU_FAULTSTATUS_JASID_MASK) >> GPU_FAULTSTATUS_JASID_SHIFT)
267
-#define GPU_FAULTSTATUS_JASID_SET(reg_val, value) \
268
-	(((reg_val) & ~GPU_FAULTSTATUS_JASID_MASK) |  \
269
-	(((value) << GPU_FAULTSTATUS_JASID_SHIFT) & GPU_FAULTSTATUS_JASID_MASK))
270
-
271
-#define GPU_FAULTSTATUS_SOURCE_ID_SHIFT 16
272
-#define GPU_FAULTSTATUS_SOURCE_ID_MASK \
273
-	(0xFFFFul << GPU_FAULTSTATUS_SOURCE_ID_SHIFT)
274
-/* End GPU_FAULTSTATUS register */
275
-
276
-/* GPU_FAULTSTATUS_ACCESS_TYPE values */
277
-#define GPU_FAULTSTATUS_ACCESS_TYPE_ATOMIC 0x0
278
-#define GPU_FAULTSTATUS_ACCESS_TYPE_EXECUTE 0x1
279
-#define GPU_FAULTSTATUS_ACCESS_TYPE_READ 0x2
280
-#define GPU_FAULTSTATUS_ACCESS_TYPE_WRITE 0x3
281
-/* End of GPU_FAULTSTATUS_ACCESS_TYPE values */
282
-
283
-/* Implementation-dependent exception codes used to indicate CSG
284
- * and CS errors that are not specified in the specs.
285
- */
286
-#define GPU_EXCEPTION_TYPE_SW_FAULT_0 ((__u8)0x70)
287
-#define GPU_EXCEPTION_TYPE_SW_FAULT_1 ((__u8)0x71)
288
-#define GPU_EXCEPTION_TYPE_SW_FAULT_2 ((__u8)0x72)
289
-
290
-/* GPU_FAULTSTATUS_EXCEPTION_TYPE values */
291
-#define GPU_FAULTSTATUS_EXCEPTION_TYPE_OK 0x00
292
-#define GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_BUS_FAULT 0x80
293
-#define GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_SHAREABILITY_FAULT 0x88
294
-#define GPU_FAULTSTATUS_EXCEPTION_TYPE_SYSTEM_SHAREABILITY_FAULT 0x89
295
-#define GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_CACHEABILITY_FAULT 0x8A
296
-/* End of GPU_FAULTSTATUS_EXCEPTION_TYPE values */
297
-
298
-#define GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT GPU_U(10)
299
-#define GPU_FAULTSTATUS_ADDRESS_VALID_MASK (GPU_U(0x1) << GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT)
300
-#define GPU_FAULTSTATUS_ADDRESS_VALID_GET(reg_val) \
301
-	(((reg_val)&GPU_FAULTSTATUS_ADDRESS_VALID_MASK) >> GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT)
302
-#define GPU_FAULTSTATUS_ADDRESS_VALID_SET(reg_val, value) \
303
-	(((reg_val) & ~GPU_FAULTSTATUS_ADDRESS_VALID_MASK) |  \
304
-	(((value) << GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT) & GPU_FAULTSTATUS_ADDRESS_VALID_MASK))
305
-
306
-/* IRQ flags */
307
-#define GPU_FAULT               (1 << 0)    /* A GPU Fault has occurred */
308
-#define GPU_PROTECTED_FAULT     (1 << 1)    /* A GPU fault has occurred in protected mode */
309
-#define RESET_COMPLETED         (1 << 8)    /* Set when a reset has completed.  */
310
-#define POWER_CHANGED_SINGLE    (1 << 9)    /* Set when a single core has finished powering up or down. */
311
-#define POWER_CHANGED_ALL       (1 << 10)   /* Set when all cores have finished powering up or down. */
312
-#define CLEAN_CACHES_COMPLETED  (1 << 17)   /* Set when a cache clean operation has completed. */
313
-#define DOORBELL_MIRROR         (1 << 18)   /* Mirrors the doorbell interrupt line to the CPU */
314
-#define MCU_STATUS_GPU_IRQ      (1 << 19)   /* MCU requires attention */
315
-
316
-/*
317
- * In Debug build,
318
- * GPU_IRQ_REG_COMMON | POWER_CHANGED_SINGLE is used to clear and unmask interupts sources of GPU_IRQ
319
- * by writing it onto GPU_IRQ_CLEAR/MASK registers.
320
- *
321
- * In Release build,
322
- * GPU_IRQ_REG_COMMON is used.
323
- *
324
- * Note:
325
- * CLEAN_CACHES_COMPLETED - Used separately for cache operation.
326
- * DOORBELL_MIRROR - Do not have it included for GPU_IRQ_REG_COMMON
327
- *                   as it can't be cleared by GPU_IRQ_CLEAR, thus interrupt storm might happen
328
- */
329
-#define GPU_IRQ_REG_COMMON (GPU_FAULT | GPU_PROTECTED_FAULT | RESET_COMPLETED \
330
-			| POWER_CHANGED_ALL | MCU_STATUS_GPU_IRQ)
331
-
332
-/* GPU_CONTROL_MCU.GPU_IRQ_RAWSTAT */
333
-#define PRFCNT_SAMPLE_COMPLETED (1 << 16)   /* Set when performance count sample has completed */
37
+/* DOORBELLS base address */
38
+#define DOORBELLS_BASE 0x0080000
39
+#define DOORBELLS_REG(r) (DOORBELLS_BASE + (r))
33440 
33541 #endif /* _UAPI_KBASE_GPU_REGMAP_CSF_H_ */