.. | .. |
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13 | 13 | #include <linux/regmap.h> |
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14 | 14 | #include <linux/mfd/core.h> |
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15 | 15 | |
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16 | | -#ifndef HIWORD_UPDATE |
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17 | 16 | #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) |
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18 | 17 | #define HIWORD_MASK(h, l) ((GENMASK((h), (l)) << 16) | GENMASK((h), (l))) |
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19 | 18 | #define HIWORD_UPDATE(v, h, l) ((((v) << (l)) & GENMASK((h), (l))) | (GENMASK((h), (l)) << 16)) |
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20 | | -#endif |
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21 | 19 | |
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22 | | -#define RTC_REG(x) ((x) + 0x60000) |
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23 | | -#define RTC_SET_SECONDS RTC_REG(0x0) |
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24 | | -#define RTC_SET_MINUTES RTC_REG(0x4) |
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25 | | -#define RTC_SET_HOURS RTC_REG(0x8) |
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26 | | -#define RTC_SET_DAYS RTC_REG(0xc) |
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27 | | -#define RTC_SET_MONTHS RTC_REG(0x10) |
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28 | | -#define RTC_SET_YEARL RTC_REG(0x14) |
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29 | | -#define RTC_SET_YEARH RTC_REG(0x18) |
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30 | | -#define RTC_SET_WEEKS RTC_REG(0x1c) |
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31 | | -#define RTC_ALARM_SECONDS RTC_REG(0x20) |
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32 | | -#define RTC_ALARM_MINUTES RTC_REG(0x24) |
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33 | | -#define RTC_ALARM_HOURS RTC_REG(0x28) |
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34 | | -#define RTC_ALARM_DAYS RTC_REG(0x2c) |
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35 | | -#define RTC_ALARM_MONTHS RTC_REG(0x30) |
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36 | | -#define RTC_ALARM_YEARL RTC_REG(0x34) |
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37 | | -#define RTC_ALARM_YEARH RTC_REG(0x38) |
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38 | | -#define RTC_CTRL RTC_REG(0x3C) |
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39 | | -#define RTC_STATUS0 RTC_REG(0x40) |
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40 | | -#define RTC_STATUS1 RTC_REG(0x44) |
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41 | | -#define RTC_INT0_EN RTC_REG(0x48) |
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42 | | -#define RTC_INT1_EN RTC_REG(0x4c) |
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43 | | -#define RTC_MSEC_CTRL RTC_REG(0x50) |
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44 | | -#define RTC_MSEC_CNT RTC_REG(0x54) |
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45 | | -#define RTC_COMP_H RTC_REG(0x58) |
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46 | | -#define RTC_COMP_D RTC_REG(0x5c) |
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47 | | -#define RTC_COMP_M RTC_REG(0x60) |
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48 | | -#define RTC_ANALOG_CTRL RTC_REG(0x64) |
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49 | | -#define RTC_ANALOG_TEST RTC_REG(0x68) |
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50 | | -#define RTC_LDO_CTRL RTC_REG(0x6c) |
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51 | | -#define RTC_XO_TRIM0 RTC_REG(0x70) |
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52 | | -#define RTC_XO_TRIM1 RTC_REG(0x74) |
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53 | | -#define RTC_VPTAT_TRIM RTC_REG(0x78) |
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54 | | -#define RTC_ANALOG_EN RTC_REG(0x7c) |
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55 | | -#define RTC_CLK32K_TEST RTC_REG(0x80) |
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56 | | -#define RTC_TEST_ST RTC_REG(0x84) |
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57 | | -#define RTC_TEST_LEN RTC_REG(0x88) |
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58 | | -#define RTC_CNT_0 RTC_REG(0x8c) |
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59 | | -#define RTC_CNT_1 RTC_REG(0x90) |
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60 | | -#define RTC_CNT_2 RTC_REG(0x94) |
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61 | | -#define RTC_CNT_3 RTC_REG(0x98) |
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62 | | -#define RTC_MAX_REGISTER RTC_CNT_3 |
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| 20 | +#define GRF_REG(x) ((x) + 0x20000) |
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| 21 | +#define PLUMAGE_GRF_GPIO0A_IOMUX GRF_REG(0x0000) |
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| 22 | +#define GPIO0A0_SEL_MASK HIWORD_MASK(1, 0) |
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| 23 | +#define GPIO0A0_SEL(x) HIWORD_UPDATE(x, 1, 0) |
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| 24 | +#define GPIO0A1_SEL_MASK HIWORD_MASK(3, 2) |
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| 25 | +#define GPIO0A1_SEL(x) HIWORD_UPDATE(x, 3, 2) |
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| 26 | +#define GPIO0A2_SEL_MASK HIWORD_MASK(5, 4) |
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| 27 | +#define GPIO0A2_SEL(x) HIWORD_UPDATE(x, 5, 4) |
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| 28 | +#define GPIO0A3_SEL_MASK HIWORD_MASK(7, 6) |
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| 29 | +#define GPIO0A3_SEL(x) HIWORD_UPDATE(x, 7, 6) |
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| 30 | +#define GPIO0A4_SEL_MASK HIWORD_MASK(9, 8) |
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| 31 | +#define GPIO0A4_SEL(x) HIWORD_UPDATE(x, 9, 8) |
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| 32 | +#define GPIO0A5_SEL_MASK HIWORD_MASK(11, 10) |
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| 33 | +#define GPIO0A5_SEL(x) HIWORD_UPDATE(x, 11, 10) |
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| 34 | +#define GPIO0A6_SEL_MASK HIWORD_MASK(13, 12) |
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| 35 | +#define GPIO0A6_SEL(x) HIWORD_UPDATE(x, 13, 12) |
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| 36 | +#define GPIO0A7_SEL_MASK HIWORD_MASK(15, 14) |
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| 37 | +#define GPIO0A7_SEL(x) HIWORD_UPDATE(x, 15, 14) |
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| 38 | +#define PLUMAGE_GRF_GPIO0B_IOMUX GRF_REG(0x0008) |
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| 39 | +#define GPIO0B0_SEL_MASK HIWORD_MASK(1, 0) |
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| 40 | +#define GPIO0B0_SEL(x) HIWORD_UPDATE(x, 1, 0) |
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| 41 | +#define PLUMAGE_GRF_GPIO0C_IOMUX GRF_REG(0x0010) |
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| 42 | +#define PLUMAGE_GRF_GPIO0D_IOMUX GRF_REG(0x0018) |
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| 43 | +#define PLUMAGE_GRF_GPIO1A_IOMUX GRF_REG(0x0020) |
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| 44 | +#define PLUMAGE_GRF_GPIO1B_IOMUX GRF_REG(0x0028) |
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| 45 | +#define PLUMAGE_GRF_GPIO0A_P GRF_REG(0x0080) |
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| 46 | +#define PLUMAGE_GRF_GPIO0B_P GRF_REG(0x0084) |
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| 47 | +#define PLUMAGE_GRF_GPIO0C_P GRF_REG(0x0088) |
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| 48 | +#define PLUMAGE_GRF_GPIO0D_P GRF_REG(0x008C) |
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| 49 | +#define PLUMAGE_GRF_GPIO1A_P GRF_REG(0x0090) |
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| 50 | +#define PLUMAGE_GRF_GPIO1B_P GRF_REG(0x0094) |
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| 51 | +#define PLUMAGE_GRF_GPIO1B_SR GRF_REG(0x00D4) |
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| 52 | +#define PLUMAGE_GRF_GPIO1B_E GRF_REG(0x0154) |
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| 53 | +#define PLUMAGE_GRF_SOC_CON0 GRF_REG(0x0400) |
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| 54 | +#define SW_TVE_DCLK_POL_MASK HIWORD_MASK(4, 4) |
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| 55 | +#define SW_TVE_DCLK_POL(x) HIWORD_UPDATE(x, 4, 4) |
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| 56 | +#define SW_TVE_DCLK_EN_MASK HIWORD_MASK(3, 3) |
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| 57 | +#define SW_TVE_DCLK_EN(x) HIWORD_UPDATE(x, 3, 3) |
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| 58 | +#define SW_DCLK_UPSAMPLE_EN_MASK HIWORD_MASK(2, 2) |
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| 59 | +#define SW_DCLK_UPSAMPLE_EN(x) HIWORD_UPDATE(x, 2, 2) |
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| 60 | +#define SW_TVE_MODE_MASK HIWORD_MASK(1, 1) |
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| 61 | +#define SW_TVE_MODE(x) HIWORD_UPDATE(x, 1, 1) |
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| 62 | +#define SW_TVE_EN_MASK HIWORD_MASK(0, 0) |
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| 63 | +#define SW_TVE_EN(x) HIWORD_UPDATE(x, 0, 0) |
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| 64 | +#define PLUMAGE_GRF_SOC_CON1 GRF_REG(0x0404) |
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| 65 | +#define PLUMAGE_GRF_SOC_CON2 GRF_REG(0x0408) |
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| 66 | +#define PLUMAGE_GRF_SOC_CON3 GRF_REG(0x040C) |
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| 67 | +#define VDAC_ENVBG_MASK HIWORD_MASK(12, 12) |
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| 68 | +#define VDAC_ENVBG(x) HIWORD_UPDATE(x, 12, 12) |
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| 69 | +#define VDAC_ENSC0_MASK HIWORD_MASK(11, 11) |
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| 70 | +#define VDAC_ENSC0(x) HIWORD_UPDATE(x, 11, 11) |
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| 71 | +#define VDAC_ENEXTREF_MASK HIWORD_MASK(10, 10) |
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| 72 | +#define VDAC_ENEXTREF(x) HIWORD_UPDATE(x, 10, 10) |
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| 73 | +#define VDAC_ENDAC0_MASK HIWORD_MASK(9, 9) |
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| 74 | +#define VDAC_ENDAC0(x) HIWORD_UPDATE(x, 9, 9) |
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| 75 | +#define VDAC_ENCTR2_MASK HIWORD_MASK(8, 8) |
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| 76 | +#define VDAC_ENCTR2(x) HIWORD_UPDATE(x, 8, 8) |
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| 77 | +#define VDAC_ENCTR1_MASK HIWORD_MASK(7, 7) |
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| 78 | +#define VDAC_ENCTR1(x) HIWORD_UPDATE(x, 7, 7) |
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| 79 | +#define VDAC_ENCTR0_MASK HIWORD_MASK(6, 6) |
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| 80 | +#define VDAC_ENCTR0(x) HIWORD_UPDATE(x, 6, 6) |
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| 81 | +#define VDAC_GAIN_MASK GENMASK(x, 5, 0) |
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| 82 | +#define VDAC_GAIN(x) HIWORD_UPDATE(x, 5, 0) |
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| 83 | +#define PLUMAGE_GRF_SOC_CON4 GRF_REG(0x0410) |
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| 84 | +#define PLUMAGE_GRF_SOC_STATUS GRF_REG(0x0480) |
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| 85 | +#define PLUMAGE_GRF_GPIO0_REN0 GRF_REG(0x0500) |
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| 86 | +#define PLUMAGE_GRF_GPIO0_REN1 GRF_REG(0x0504) |
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| 87 | +#define PLUMAGE_GRF_GPIO1_REN0 GRF_REG(0x0508) |
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| 88 | +#define GRF_MAX_REGISTER PLUMAGE_GRF_GPIO1_REN0 |
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63 | 89 | |
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64 | | -#define GRF_REG(x) ((x) + 0x20000) |
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65 | | -#define PLUMAGE_GRF_GPIO0A_IOMUX GRF_REG(0x0000) |
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66 | | -#define PLUMAGE_GRF_GPIO0B_IOMUX GRF_REG(0x0008) |
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67 | | -#define PLUMAGE_GRF_GPIO0C_IOMUX GRF_REG(0x0010) |
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68 | | -#define PLUMAGE_GRF_GPIO0D_IOMUX GRF_REG(0x0018) |
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69 | | -#define PLUMAGE_GRF_GPIO1A_IOMUX GRF_REG(0x0020) |
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70 | | -#define PLUMAGE_GRF_GPIO1B_IOMUX GRF_REG(0x0028) |
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71 | | -#define PIN0_SEL_MASK HIWORD_MASK(1, 0) |
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72 | | -#define PIN0_SEL(x) HIWORD_UPDATE(x, 1, 0) |
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73 | | -#define PIN1_SEL_MASK HIWORD_MASK(3, 2) |
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74 | | -#define PIN1_SEL(x) HIWORD_UPDATE(x, 3, 2) |
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75 | | -#define PIN2_SEL_MASK HIWORD_MASK(5, 4) |
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76 | | -#define PIN2_SEL(x) HIWORD_UPDATE(x, 5, 4) |
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77 | | -#define PIN3_SEL_MASK HIWORD_MASK(7, 6) |
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78 | | -#define PIN3_SEL(x) HIWORD_UPDATE(x, 7, 6) |
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79 | | -#define PIN4_SEL_MASK HIWORD_MASK(9, 8) |
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80 | | -#define PIN4_SEL(x) HIWORD_UPDATE(x, 9, 8) |
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81 | | -#define PIN5_SEL_MASK HIWORD_MASK(11, 10) |
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82 | | -#define PIN5_SEL(x) HIWORD_UPDATE(x, 11, 10) |
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83 | | -#define PIN6_SEL_MASK HIWORD_MASK(13, 12) |
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84 | | -#define PIN6_SEL(x) HIWORD_UPDATE(x, 13, 12) |
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85 | | -#define PIN7_SEL_MASK HIWORD_MASK(15, 14) |
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86 | | -#define PIN7_SEL(x) HIWORD_UPDATE(x, 15, 14) |
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87 | | -#define PLUMAGE_GRF_GPIO0A_P GRF_REG(0x0080) |
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88 | | -#define PLUMAGE_GRF_GPIO0B_P GRF_REG(0x0084) |
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89 | | -#define PLUMAGE_GRF_GPIO0C_P GRF_REG(0x0088) |
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90 | | -#define PLUMAGE_GRF_GPIO0D_P GRF_REG(0x008C) |
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91 | | -#define PLUMAGE_GRF_GPIO1A_P GRF_REG(0x0090) |
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92 | | -#define PLUMAGE_GRF_GPIO1B_P GRF_REG(0x0094) |
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93 | | -#define PLUMAGE_GRF_GPIO1B_SR GRF_REG(0x00D4) |
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94 | | -#define PLUMAGE_GRF_GPIO1B_E GRF_REG(0x0154) |
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95 | | -#define PLUMAGE_GRF_SOC_CON0 GRF_REG(0x0400) |
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96 | | -#define RTC_CLAMP_EN_MASK HIWORD_MASK(13, 13) |
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97 | | -#define RTC_CLAMP_EN(x) HIWORD_UPDATE(x, 13, 13) |
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98 | | -#define SW_TVE_DCLK_POL_MASK HIWORD_MASK(4, 4) |
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99 | | -#define SW_TVE_DCLK_POL(x) HIWORD_UPDATE(x, 4, 4) |
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100 | | -#define SW_TVE_DCLK_POL_MASK HIWORD_MASK(4, 4) |
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101 | | -#define SW_TVE_DCLK_POL(x) HIWORD_UPDATE(x, 4, 4) |
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102 | | -#define SW_TVE_DCLK_EN_MASK HIWORD_MASK(3, 3) |
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103 | | -#define SW_TVE_DCLK_EN(x) HIWORD_UPDATE(x, 3, 3) |
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104 | | -#define SW_DCLK_UPSAMPLE_EN_MASK HIWORD_MASK(2, 2) |
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105 | | -#define SW_DCLK_UPSAMPLE_EN(x) HIWORD_UPDATE(x, 2, 2) |
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106 | | -#define SW_TVE_MODE_MASK HIWORD_MASK(1, 1) |
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107 | | -#define SW_TVE_MODE(x) HIWORD_UPDATE(x, 1, 1) |
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108 | | -#define SW_TVE_EN_MASK HIWORD_MASK(0, 0) |
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109 | | -#define SW_TVE_EN(x) HIWORD_UPDATE(x, 0, 0) |
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110 | | -#define PLUMAGE_GRF_SOC_CON1 GRF_REG(0x0404) |
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111 | | -#define PLUMAGE_GRF_SOC_CON2 GRF_REG(0x0408) |
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112 | | -#define PLUMAGE_GRF_SOC_CON3 GRF_REG(0x040C) |
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113 | | -#define DCLK_UPSAMPLE_2X4X_MASK HIWORD_MASK(15, 15) |
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114 | | -#define DCLK_UPSAMPLE_2X4X(x) HIWORD_UPDATE(x, 15, 15) |
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115 | | -#define VDAC_ENVBG_MASK HIWORD_MASK(12, 12) |
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116 | | -#define VDAC_ENVBG(x) HIWORD_UPDATE(x, 12, 12) |
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117 | | -#define VDAC_ENSC0_MASK HIWORD_MASK(11, 11) |
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118 | | -#define VDAC_ENSC0(x) HIWORD_UPDATE(x, 11, 11) |
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119 | | -#define VDAC_ENEXTREF_MASK HIWORD_MASK(10, 10) |
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120 | | -#define VDAC_ENEXTREF(x) HIWORD_UPDATE(x, 10, 10) |
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121 | | -#define VDAC_ENDAC0_MASK HIWORD_MASK(9, 9) |
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122 | | -#define VDAC_ENDAC0(x) HIWORD_UPDATE(x, 9, 9) |
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123 | | -#define VDAC_ENCTR2_MASK HIWORD_MASK(8, 8) |
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124 | | -#define VDAC_ENCTR2(x) HIWORD_UPDATE(x, 8, 8) |
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125 | | -#define VDAC_ENCTR1_MASK HIWORD_MASK(7, 7) |
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126 | | -#define VDAC_ENCTR1(x) HIWORD_UPDATE(x, 7, 7) |
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127 | | -#define VDAC_ENCTR0_MASK HIWORD_MASK(6, 6) |
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128 | | -#define VDAC_ENCTR0(x) HIWORD_UPDATE(x, 6, 6) |
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129 | | -#define VDAC_GAIN_MASK GENMASK(x, 5, 0) |
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130 | | -#define VDAC_GAIN(x) HIWORD_UPDATE(x, 5, 0) |
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131 | | -#define PLUMAGE_GRF_SOC_CON4 GRF_REG(0x0410) |
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132 | | -#define PLUMAGE_GRF_SOC_STATUS GRF_REG(0x0480) |
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133 | | -#define PLUMAGE_GRF_GPIO0_REN0 GRF_REG(0x0500) |
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134 | | -#define PLUMAGE_GRF_GPIO0_REN1 GRF_REG(0x0504) |
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135 | | -#define PLUMAGE_GRF_GPIO1_REN0 GRF_REG(0x0508) |
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136 | | -#define PLUMAGE_GRF_RTC_STATUS GRF_REG(0x0610) |
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| 90 | +#define CRU_REG(x) ((x) + 0x140000) |
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| 91 | +#define CRU_SPLL_CON0 CRU_REG(0x0000) |
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| 92 | +#define POSTDIV1_MASK HIWORD_MASK(14, 12) |
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| 93 | +#define POSTDIV1(x) HIWORD_UPDATE(x, 14, 12) |
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| 94 | +#define FBDIV_MASK HIWORD_MASK(14, 12) |
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| 95 | +#define FBDIV(x) HIWORD_UPDATE(x, 14, 12) |
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| 96 | +#define CRU_SPLL_CON1 CRU_REG(0x0004) |
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| 97 | +#define PLLPD0_MASK HIWORD_MASK(13, 13) |
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| 98 | +#define PLLPD0(x) HIWORD_UPDATE(x, 13, 13) |
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| 99 | +#define PLL_LOCK BIT(10) |
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| 100 | +#define POSTDIV2_MASK HIWORD_MASK(8, 6) |
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| 101 | +#define POSTDIV2(x) HIWORD_UPDATE(x, 8, 6) |
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| 102 | +#define REFDIV_MASK HIWORD_MASK(5, 0) |
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| 103 | +#define REFDIV(x) HIWORD_UPDATE(x, 5, 0) |
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| 104 | +#define CRU_SPLL_CON2 CRU_REG(0x0008) |
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| 105 | +#define CRU_MODE_CON CRU_REG(0x0020) |
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| 106 | +#define CLK_SPLL_MODE_MASK HIWORD_MASK(2, 0) |
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| 107 | +#define CLK_SPLL_MODE(x) HIWORD_UPDATE(x, 2, 0) |
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| 108 | +#define CRU_CLKSEL_CON0 CRU_REG(0x0030) |
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| 109 | +#define CRU_CLKSEL_CON1 CRU_REG(0x0034) |
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| 110 | +#define DCLK_CVBS_4X_DIV_CON_MASK HIWORD_MASK(12, 8) |
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| 111 | +#define DCLK_CVBS_4X_DIV_CON(x) HIWORD_UPDATE(x, 12, 8) |
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| 112 | +#define CRU_CLKSEL_CON2 CRU_REG(0x0038) |
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| 113 | +#define CRU_CLKSEL_CON3 CRU_REG(0x003c) |
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| 114 | +#define CRU_GATE_CON0 CRU_REG(0x0040) |
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| 115 | +#define CRU_SOFTRST_CON0 CRU_REG(0x0050) |
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| 116 | +#define DRESETN_CVBS_1X_MASK HIWORD_MASK(10, 10) |
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| 117 | +#define DRESETN_CVBS_1X(x) HIWORD_UPDATE(x, 10, 10) |
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| 118 | +#define DRESETN_CVBS_4X_MASK HIWORD_MASK(9, 9) |
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| 119 | +#define DRESETN_CVBS_4X(x) HIWORD_UPDATE(x, 9, 9) |
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| 120 | +#define PRESETN_CVBS_MASK HIWORD_MASK(8, 8) |
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| 121 | +#define PRESETN_CVBS(x) HIWORD_UPDATE(x, 8, 8) |
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| 122 | +#define PRESETN_GRF_MASK HIWORD_MASK(3, 3) |
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| 123 | +#define PRESETN_GRF(x) HIWORD_UPDATE(x, 3, 3) |
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| 124 | +#define CRU_MAX_REGISTER CRU_SOFTRST_CON0 |
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137 | 125 | |
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138 | | -#ifndef GRF_MAX_REGISTER |
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139 | | -#define GRF_MAX_REGISTER PLUMAGE_GRF_RTC_STATUS |
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140 | | -#endif |
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141 | | - |
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142 | | -#define CRU_REG(x) ((x) + 0x140000) |
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143 | | -#define CRU_SPLL_CON0 CRU_REG(0x0000) |
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144 | | -#define POSTDIV1_MASK HIWORD_MASK(14, 12) |
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145 | | -#define POSTDIV1(x) HIWORD_UPDATE(x, 14, 12) |
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146 | | -#define FBDIV_MASK HIWORD_MASK(14, 12) |
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147 | | -#define FBDIV(x) HIWORD_UPDATE(x, 14, 12) |
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148 | | -#define CRU_SPLL_CON1 CRU_REG(0x0004) |
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149 | | -#define PLLPD0_MASK HIWORD_MASK(13, 13) |
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150 | | -#define PLLPD0(x) HIWORD_UPDATE(x, 13, 13) |
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151 | | -#define PLL_LOCK BIT(10) |
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152 | | -#define POSTDIV2_MASK HIWORD_MASK(8, 6) |
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153 | | -#define POSTDIV2(x) HIWORD_UPDATE(x, 8, 6) |
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154 | | -#define REFDIV_MASK HIWORD_MASK(5, 0) |
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155 | | -#define REFDIV(x) HIWORD_UPDATE(x, 5, 0) |
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156 | | -#define CRU_SPLL_CON2 CRU_REG(0x0008) |
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157 | | -#define CRU_MODE_CON CRU_REG(0x0020) |
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158 | | -#define CLK_SPLL_MODE_MASK HIWORD_MASK(2, 0) |
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159 | | -#define CLK_SPLL_MODE(x) HIWORD_UPDATE(x, 2, 0) |
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160 | | -#define CRU_CLKSEL_CON0 CRU_REG(0x0030) |
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161 | | -#define CRU_CLKSEL_CON1 CRU_REG(0x0034) |
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162 | | -#define DCLK_CVBS_4X_DIV_CON_MASK HIWORD_MASK(12, 8) |
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163 | | -#define DCLK_CVBS_4X_DIV_CON(x) HIWORD_UPDATE(x, 12, 8) |
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164 | | -#define CRU_CLKSEL_CON2 CRU_REG(0x0038) |
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165 | | -#define CRU_CLKSEL_CON3 CRU_REG(0x003c) |
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166 | | -#define CRU_GATE_CON0 CRU_REG(0x0040) |
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167 | | -#define PCLK_EFUSE_EN_MASK BIT(14 + 16) |
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168 | | -#define PCLK_EFUSE_DISABLE BIT(14) |
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169 | | -#define DCLK_CVBS_1X_PLL_CLK_GATE_MASK HIWORD_MASK(12, 12) |
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170 | | -#define DCLK_CVBS_1X_PLL_CLK_GATE(x) HIWORD_UPDATE(x, 12, 12) |
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171 | | -#define DCLK_CVBS_4X_PLL_CLK_GATE_MASK HIWORD_MASK(11, 11) |
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172 | | -#define DCLK_CVBS_4X_PLL_CLK_GATE(x) HIWORD_UPDATE(x, 11, 11) |
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173 | | -#define CRU_SOFTRST_CON0 CRU_REG(0x0050) |
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174 | | -#define DRESETN_CVBS_1X_MASK HIWORD_MASK(10, 10) |
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175 | | -#define DRESETN_CVBS_1X(x) HIWORD_UPDATE(x, 10, 10) |
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176 | | -#define DRESETN_CVBS_4X_MASK HIWORD_MASK(9, 9) |
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177 | | -#define DRESETN_CVBS_4X(x) HIWORD_UPDATE(x, 9, 9) |
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178 | | -#define PRESETN_CVBS_MASK HIWORD_MASK(8, 8) |
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179 | | -#define PRESETN_CVBS(x) HIWORD_UPDATE(x, 8, 8) |
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180 | | -#define PRESETN_GRF_MASK HIWORD_MASK(3, 3) |
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181 | | -#define PRESETN_GRF(x) HIWORD_UPDATE(x, 3, 3) |
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182 | | -#define CRU_MAX_REGISTER CRU_SOFTRST_CON0 |
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183 | | - |
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184 | | -#define GPIO0_BASE 0x30000 |
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185 | | -#define GPIO1_BASE 0x40000 |
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186 | | -#define GPIO_SWPORT_DR_L 0x00 |
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187 | | -#define GPIO_SWPORT_DR_H 0x04 |
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188 | | -#define GPIO_SWPORT_DDR_L 0x08 |
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189 | | -#define GPIO_SWPORT_DDR_H 0x0c |
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190 | | -#define GPIO_INT_EN_L 0x10 |
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191 | | -#define GPIO_INT_EN_H 0x14 |
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192 | | -#define GPIO_INT_MASK_L 0x18 |
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193 | | -#define GPIO_INT_MASK_H 0x1c |
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194 | | -#define GPIO_INT_TYPE_L 0x20 |
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195 | | -#define GPIO_INT_TYPE_H 0x24 |
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196 | | -#define GPIO_INT_POLARITY_L 0x28 |
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197 | | -#define GPIO_INT_POLARITY_H 0x2c |
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198 | | -#define GPIO_INT_BOTHEDGE_L 0x30 |
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199 | | -#define GPIO_INT_BOTHEDGE_H 0x34 |
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200 | | -#define GPIO_DEBOUNCE_L 0x38 |
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201 | | -#define GPIO_DEBOUNCE_H 0x3c |
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202 | | -#define GPIO_DBCLK_DIV_EN_L 0x40 |
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203 | | -#define GPIO_DBCLK_DIV_EN_H 0x44 |
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204 | | -#define GPIO_DBCLK_DIV_CON 0x48 |
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205 | | -#define GPIO_INT_STATUS 0x50 |
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206 | | -#define GPIO_INT_RAWSTATUS 0x58 |
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207 | | -#define GPIO_PORT_EOI_L 0x60 |
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208 | | -#define GPIO_PORT_EOI_H 0x64 |
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209 | | -#define GPIO_EXT_PORT 0x70 |
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210 | | -#define GPIO_VER_ID 0x78 |
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211 | | -#define GPIO_MAX_REGISTER (GPIO1_BASE + GPIO_VER_ID) |
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212 | | - |
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213 | | -#define TVE_REG(x) ((x) + 0x10000) |
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214 | | -#define BT656_DECODER_CTRL TVE_REG(0x3D00) |
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215 | | -#define BT656_DECODER_CROP TVE_REG(0x3D04) |
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216 | | -#define BT656_DECODER_SIZE TVE_REG(0x3D08) |
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217 | | -#define BT656_DECODER_HTOTAL_HS_END TVE_REG(0x3D0C) |
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218 | | -#define BT656_DECODER_VACT_ST_HACT_ST TVE_REG(0x3D10) |
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219 | | -#define BT656_DECODER_VTOTAL_VS_END TVE_REG(0x3D14) |
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220 | | -#define BT656_DECODER_VS_ST_END_F1 TVE_REG(0x3D18) |
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221 | | -#define BT656_DECODER_DBG_REG TVE_REG(0x3D1C) |
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222 | | -#define TVE_MODE_CTRL TVE_REG(0x3E00) |
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223 | | -#define TVE_HOR_TIMING1 TVE_REG(0x3E04) |
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224 | | -#define TVE_HOR_TIMING2 TVE_REG(0x3E08) |
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225 | | -#define TVE_HOR_TIMING3 TVE_REG(0x3E0C) |
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226 | | -#define TVE_SUB_CAR_FRQ TVE_REG(0x3E10) |
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227 | | -#define TVE_LUMA_FILTER1 TVE_REG(0x3E14) |
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228 | | -#define TVE_LUMA_FILTER2 TVE_REG(0x3E18) |
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229 | | -#define TVE_LUMA_FILTER3 TVE_REG(0x3E1C) |
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230 | | -#define TVE_LUMA_FILTER4 TVE_REG(0x3E20) |
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231 | | -#define TVE_LUMA_FILTER5 TVE_REG(0x3E24) |
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232 | | -#define TVE_LUMA_FILTER6 TVE_REG(0x3E28) |
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233 | | -#define TVE_LUMA_FILTER7 TVE_REG(0x3E2C) |
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234 | | -#define TVE_LUMA_FILTER8 TVE_REG(0x3E30) |
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235 | | -#define TVE_IMAGE_POSITION TVE_REG(0x3E34) |
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236 | | -#define TVE_ROUTING TVE_REG(0x3E38) |
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237 | | -#define TVE_SYNC_ADJUST TVE_REG(0x3E50) |
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238 | | -#define TVE_STATUS TVE_REG(0x3E54) |
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239 | | -#define TVE_CTRL TVE_REG(0x3E68) |
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240 | | -#define TVE_INTR_STATUS TVE_REG(0x3E6C) |
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241 | | -#define TVE_INTR_EN TVE_REG(0x3E70) |
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242 | | -#define TVE_INTR_CLR TVE_REG(0x3E74) |
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243 | | -#define TVE_COLOR_BUSRT_SAT TVE_REG(0x3E78) |
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244 | | -#define TVE_CHROMA_BANDWIDTH TVE_REG(0x3E8C) |
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245 | | -#define TVE_BRIGHTNESS_CONTRAST TVE_REG(0x3E90) |
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246 | | -#define TVE_ID TVE_REG(0x3E98) |
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247 | | -#define TVE_REVISION TVE_REG(0x3E9C) |
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248 | | -#define TVE_CLAMP TVE_REG(0x3EA0) |
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249 | | -#define TVE_MAX_REGISTER TVE_CLAMP |
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250 | | - |
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251 | | -/* RK630 IRQ Definitions */ |
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252 | | -#define RK630_IRQ_RTC_ALARM 0 |
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253 | | -#define RK630_IRQ_SYS_INT 1 |
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254 | | - |
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255 | | -#define RK630_IRQ_RTC_ALARM_MSK BIT(7) |
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256 | | -#define RK630_IRQ_SYS_MSK BIT(4) |
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| 126 | +#define TVE_REG(x) ((x) + 0x10000) |
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| 127 | +#define BT656_DECODER_CTRL TVE_REG(0x3D00) |
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| 128 | +#define BT656_DECODER_CROP TVE_REG(0x3D04) |
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| 129 | +#define BT656_DECODER_SIZE TVE_REG(0x3D08) |
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| 130 | +#define BT656_DECODER_HTOTAL_HS_END TVE_REG(0x3D0C) |
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| 131 | +#define BT656_DECODER_VACT_ST_HACT_ST TVE_REG(0x3D10) |
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| 132 | +#define BT656_DECODER_VTOTAL_VS_END TVE_REG(0x3D14) |
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| 133 | +#define BT656_DECODER_VS_ST_END_F1 TVE_REG(0x3D18) |
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| 134 | +#define BT656_DECODER_DBG_REG TVE_REG(0x3D1C) |
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| 135 | +#define TVE_MODE_CTRL TVE_REG(0x3E00) |
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| 136 | +#define TVE_HOR_TIMING1 TVE_REG(0x3E04) |
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| 137 | +#define TVE_HOR_TIMING2 TVE_REG(0x3E08) |
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| 138 | +#define TVE_HOR_TIMING3 TVE_REG(0x3E0C) |
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| 139 | +#define TVE_SUB_CAR_FRQ TVE_REG(0x3E10) |
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| 140 | +#define TVE_LUMA_FILTER1 TVE_REG(0x3E14) |
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| 141 | +#define TVE_LUMA_FILTER2 TVE_REG(0x3E18) |
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| 142 | +#define TVE_LUMA_FILTER3 TVE_REG(0x3E1C) |
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| 143 | +#define TVE_LUMA_FILTER4 TVE_REG(0x3E20) |
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| 144 | +#define TVE_LUMA_FILTER5 TVE_REG(0x3E24) |
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| 145 | +#define TVE_LUMA_FILTER6 TVE_REG(0x3E28) |
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| 146 | +#define TVE_LUMA_FILTER7 TVE_REG(0x3E2C) |
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| 147 | +#define TVE_LUMA_FILTER8 TVE_REG(0x3E30) |
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| 148 | +#define TVE_IMAGE_POSITION TVE_REG(0x3E34) |
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| 149 | +#define TVE_ROUTING TVE_REG(0x3E38) |
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| 150 | +#define TVE_SYNC_ADJUST TVE_REG(0x3E50) |
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| 151 | +#define TVE_STATUS TVE_REG(0x3E54) |
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| 152 | +#define TVE_CTRL TVE_REG(0x3E68) |
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| 153 | +#define TVE_INTR_STATUS TVE_REG(0x3E6C) |
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| 154 | +#define TVE_INTR_EN TVE_REG(0x3E70) |
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| 155 | +#define TVE_INTR_CLR TVE_REG(0x3E74) |
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| 156 | +#define TVE_COLOR_BUSRT_SAT TVE_REG(0x3E78) |
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| 157 | +#define TVE_CHROMA_BANDWIDTH TVE_REG(0x3E8C) |
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| 158 | +#define TVE_BRIGHTNESS_CONTRAST TVE_REG(0x3E90) |
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| 159 | +#define TVE_ID TVE_REG(0x3E98) |
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| 160 | +#define TVE_REVISION TVE_REG(0x3E9C) |
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| 161 | +#define TVE_CLAMP TVE_REG(0x3EA0) |
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| 162 | +#define TVE_MAX_REGISTER TVE_CLAMP |
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257 | 163 | |
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258 | 164 | struct rk630 { |
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259 | 165 | struct device *dev; |
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260 | 166 | struct i2c_client *client; |
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261 | | - struct clk *ref_clk; |
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262 | 167 | struct regmap *grf; |
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263 | | - struct regmap *pinctrl; |
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264 | 168 | struct regmap *cru; |
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265 | 169 | struct regmap *tve; |
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266 | | - struct regmap *rtc; |
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267 | | - struct regmap *efuse; |
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268 | | - struct regmap *codec; |
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269 | 170 | struct gpio_desc *reset_gpio; |
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270 | | - int irq; |
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271 | | - struct regmap_irq_chip_data *irq_data; |
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272 | | - const struct regmap_irq_chip *regmap_irq_chip; |
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273 | 171 | }; |
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274 | 172 | |
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275 | | -extern const struct regmap_config rk630_efuse_regmap_config; |
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276 | | -extern const struct regmap_config rk630_rtc_regmap_config; |
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277 | 173 | extern const struct regmap_config rk630_grf_regmap_config; |
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278 | | -extern const struct regmap_config rk630_pinctrl_regmap_config; |
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279 | 174 | extern const struct regmap_config rk630_cru_regmap_config; |
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280 | 175 | extern const struct regmap_config rk630_tve_regmap_config; |
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281 | | -extern const struct regmap_config rk630_codec_regmap_config; |
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282 | 176 | |
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283 | 177 | int rk630_core_probe(struct rk630 *rk630); |
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284 | 178 | int rk630_core_remove(struct rk630 *rk630); |
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