.. | .. |
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1 | 1 | // SPDX-License-Identifier: GPL-2.0 |
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2 | 2 | /* |
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3 | | - * SAMSUNG Exynos5433 TM2 board device tree source |
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| 3 | + * Samsung Exynos5433 TM2 board device tree source |
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4 | 4 | * |
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5 | 5 | * Copyright (c) 2016 Samsung Electronics Co., Ltd. |
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6 | 6 | * |
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.. | .. |
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33 | 33 | <&cmu_disp CLK_MOUT_DISP_PLL>, |
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34 | 34 | <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, |
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35 | 35 | <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, |
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36 | | - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; |
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| 36 | + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>, |
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| 37 | + <&cmu_disp CLK_MOUT_SCLK_DSD_USER>; |
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37 | 38 | assigned-clock-parents = <0>, <0>, |
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38 | 39 | <&cmu_mif CLK_ACLK_DISP_333>, |
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39 | 40 | <&cmu_mif CLK_SCLK_DSIM0_DISP>, |
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.. | .. |
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45 | 46 | <&cmu_disp CLK_FOUT_DISP_PLL>, |
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46 | 47 | <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, |
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47 | 48 | <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, |
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48 | | - <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; |
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| 49 | + <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, |
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| 50 | + <&cmu_mif CLK_SCLK_DSD_DISP>; |
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49 | 51 | assigned-clock-rates = <250000000>, <400000000>; |
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50 | 52 | }; |
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51 | 53 | |
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