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2023-12-08 01573e231f18eb2d99162747186f59511f56b64d

 kernel/arch/arm/boot/dts/sun8i-a33.dtsi
..
..
@@ -46,7 +46,7 @@
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 #include <dt-bindings/thermal/thermal.h>
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 / {
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-	cpu0_opp_table: opp_table0 {
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+	cpu0_opp_table: opp-table-cpu {
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 		compatible = "operating-points-v2";
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 		opp-shared;
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..
..
@@ -131,14 +131,14 @@
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 			#cooling-cells = <2>;
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 		};
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-		cpu@1 {
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+		cpu1: cpu@1 {
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 			clocks = <&ccu CLK_CPUX>;
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 			clock-names = "cpu";
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 			operating-points-v2 = <&cpu0_opp_table>;
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 			#cooling-cells = <2>;
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 		};
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-		cpu@2 {
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+		cpu2: cpu@2 {
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 			compatible = "arm,cortex-a7";
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 			device_type = "cpu";
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 			reg = <2>;
..
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@@ -148,7 +148,7 @@
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 			#cooling-cells = <2>;
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 		};
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-		cpu@3 {
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+		cpu3: cpu@3 {
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 			compatible = "arm,cortex-a7";
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 			device_type = "cpu";
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 			reg = <3>;
..
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@@ -159,18 +159,12 @@
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 		};
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 	};
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-	de: display-engine {
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-		compatible = "allwinner,sun8i-a33-display-engine";
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-		allwinner,pipelines = <&fe0>;
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-		status = "disabled";
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-	};
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-
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 	iio-hwmon {
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 		compatible = "iio-hwmon";
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 		io-channels = <&ths>;
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 	};
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-	mali_opp_table: gpu-opp-table {
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+	mali_opp_table: opp-table-gpu {
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 		compatible = "operating-points-v2";
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 		opp-144000000 {
..
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@@ -186,21 +180,17 @@
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 		};
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 	};
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-	memory {
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-		reg = <0x40000000 0x80000000>;
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-	};
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-
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 	sound: sound {
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 		compatible = "simple-audio-card";
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 		simple-audio-card,name = "sun8i-a33-audio";
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 		simple-audio-card,format = "i2s";
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 		simple-audio-card,frame-master = <&link_codec>;
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 		simple-audio-card,bitclock-master = <&link_codec>;
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-		simple-audio-card,mclk-fs = <512>;
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+		simple-audio-card,mclk-fs = <128>;
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 		simple-audio-card,aux-devs = <&codec_analog>;
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 		simple-audio-card,routing =
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-			"Left DAC", "AIF1 Slot 0 Left",
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-			"Right DAC", "AIF1 Slot 0 Right";
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+			"Left DAC", "DACL",
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+			"Right DAC", "DACR";
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 		status = "disabled";
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 		simple-audio-card,cpu {
..
..
@@ -212,50 +202,20 @@
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 		};
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 	};
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-	soc@1c00000 {
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-		tcon0: lcd-controller@1c0c000 {
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-			compatible = "allwinner,sun8i-a33-tcon";
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-			reg = <0x01c0c000 0x1000>;
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-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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-			clocks = <&ccu CLK_BUS_LCD>,
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-				 <&ccu CLK_LCD_CH0>;
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-			clock-names = "ahb",
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-				      "tcon-ch0";
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-			clock-output-names = "tcon-pixel-clock";
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-			resets = <&ccu RST_BUS_LCD>;
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-			reset-names = "lcd";
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-			status = "disabled";
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-
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-			ports {
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-				#address-cells = <1>;
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-				#size-cells = <0>;
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-
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-				tcon0_in: port@0 {
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-					#address-cells = <1>;
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-					#size-cells = <0>;
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-					reg = <0>;
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-
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-					tcon0_in_drc0: endpoint@0 {
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-						reg = <0>;
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-						remote-endpoint = <&drc0_out_tcon0>;
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-					};
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-				};
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-
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-				tcon0_out: port@1 {
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-					#address-cells = <1>;
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-					#size-cells = <0>;
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-					reg = <1>;
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-
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-					tcon0_out_dsi: endpoint@1 {
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-						reg = <1>;
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-						remote-endpoint = <&dsi_in_tcon0>;
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-					};
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-				};
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-			};
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+	soc {
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+		video-codec@1c0e000 {
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+			compatible = "allwinner,sun8i-a33-video-engine";
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+			reg = <0x01c0e000 0x1000>;
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+			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
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+				 <&ccu CLK_DRAM_VE>;
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+			clock-names = "ahb", "mod", "ram";
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+			resets = <&ccu RST_BUS_VE>;
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+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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+			allwinner,sram = <&ve_sram 1>;
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 		};
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216
 
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 		crypto: crypto-engine@1c15000 {
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-			compatible = "allwinner,sun4i-a10-crypto";
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+			compatible = "allwinner,sun8i-a33-crypto";
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 			reg = <0x01c15000 0x1000>;
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 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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 			clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
..
..
@@ -305,19 +265,12 @@
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 			phys = <&dphy>;
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 			phy-names = "dphy";
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 			status = "disabled";
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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-			ports {
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-				#address-cells = <1>;
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-				#size-cells = <0>;
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-
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-				port@0 {
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-					#address-cells = <1>;
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-					#size-cells = <0>;
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-					reg = <0>;
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-
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-					dsi_in_tcon0: endpoint {
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-						remote-endpoint = <&tcon0_out_dsi>;
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-					};
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+			port {
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+				dsi_in_tcon0: endpoint {
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+					remote-endpoint = <&tcon0_out_dsi>;
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 				};
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 			};
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 		};
..
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@@ -332,115 +285,6 @@
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 			status = "disabled";
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 			#phy-cells = <0>;
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 		};
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-
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-		fe0: display-frontend@1e00000 {
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-			compatible = "allwinner,sun8i-a33-display-frontend";
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-			reg = <0x01e00000 0x20000>;
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-			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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-			clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
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-				 <&ccu CLK_DRAM_DE_FE>;
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-			clock-names = "ahb", "mod",
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-				      "ram";
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-			resets = <&ccu RST_BUS_DE_FE>;
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-
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-			ports {
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-				#address-cells = <1>;
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-				#size-cells = <0>;
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-
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-				fe0_out: port@1 {
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-					#address-cells = <1>;
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-					#size-cells = <0>;
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-					reg = <1>;
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-
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-					fe0_out_be0: endpoint@0 {
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-						reg = <0>;
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-						remote-endpoint = <&be0_in_fe0>;
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-					};
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-				};
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-			};
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-		};
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-
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-		be0: display-backend@1e60000 {
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-			compatible = "allwinner,sun8i-a33-display-backend";
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-			reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
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-			reg-names = "be", "sat";
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-			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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-			clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
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-				 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
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-			clock-names = "ahb", "mod",
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-				      "ram", "sat";
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-			resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
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-			reset-names = "be", "sat";
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-			assigned-clocks = <&ccu CLK_DE_BE>;
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-			assigned-clock-rates = <300000000>;
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-
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-			ports {
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-				#address-cells = <1>;
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-				#size-cells = <0>;
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-
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-				be0_in: port@0 {
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-					#address-cells = <1>;
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-					#size-cells = <0>;
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-					reg = <0>;
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-
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-					be0_in_fe0: endpoint@0 {
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-						reg = <0>;
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-						remote-endpoint = <&fe0_out_be0>;
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-					};
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-				};
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-
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-				be0_out: port@1 {
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-					#address-cells = <1>;
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-					#size-cells = <0>;
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-					reg = <1>;
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-
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-					be0_out_drc0: endpoint@0 {
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-						reg = <0>;
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-						remote-endpoint = <&drc0_in_be0>;
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-					};
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-				};
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-			};
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-		};
404
-
405
-		drc0: drc@1e70000 {
406
-			compatible = "allwinner,sun8i-a33-drc";
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-			reg = <0x01e70000 0x10000>;
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-			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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-			clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
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-				 <&ccu CLK_DRAM_DRC>;
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-			clock-names = "ahb", "mod", "ram";
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-			resets = <&ccu RST_BUS_DRC>;
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-
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-			assigned-clocks = <&ccu CLK_DRC>;
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-			assigned-clock-rates = <300000000>;
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-
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-			ports {
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-				#address-cells = <1>;
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-				#size-cells = <0>;
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-
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-				drc0_in: port@0 {
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-					#address-cells = <1>;
423
-					#size-cells = <0>;
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-					reg = <0>;
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-
426
-					drc0_in_be0: endpoint@0 {
427
-						reg = <0>;
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-						remote-endpoint = <&be0_out_drc0>;
429
-					};
430
-				};
431
-
432
-				drc0_out: port@1 {
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-					#address-cells = <1>;
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-					#size-cells = <0>;
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-					reg = <1>;
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-
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-					drc0_out_tcon0: endpoint@0 {
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-						reg = <0>;
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-						remote-endpoint = <&tcon0_in_drc0>;
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-					};
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-				};
442
-			};
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-		};
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 	};
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 	thermal-zones {
..
..
@@ -453,11 +297,17 @@
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 			cooling-maps {
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 				map0 {
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 					trip = <&cpu_alert0>;
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-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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 				};
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 				map1 {
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 					trip = <&cpu_alert1>;
460
-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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 				};
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312
 
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 				map2 {
..
..
@@ -511,8 +361,33 @@
511
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 	};
512
362
 };
513
363
 
364
+&be0 {
365
+	compatible = "allwinner,sun8i-a33-display-backend";
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+	/* A33 has an extra "SAT" module packed inside the display backend */
367
+	reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
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+	reg-names = "be", "sat";
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+	clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
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+		 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
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+	clock-names = "ahb", "mod",
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+		      "ram", "sat";
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+	resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
374
+	reset-names = "be", "sat";
375
+};
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+
514
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 &ccu {
515
378
 	compatible = "allwinner,sun8i-a33-ccu";
379
+};
380
+
381
+&de {
382
+	compatible = "allwinner,sun8i-a33-display-engine";
383
+};
384
+
385
+&drc0 {
386
+	compatible = "allwinner,sun8i-a33-drc";
387
+};
388
+
389
+&fe0 {
390
+	compatible = "allwinner,sun8i-a33-display-frontend";
516
391
 };
517
392
 
518
393
 &mali {
..
..
@@ -524,13 +399,27 @@
524
399
 	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
525
400
 		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
526
401
 
527
-	uart0_pins_b: uart0@1 {
402
+	uart0_pb_pins: uart0-pb-pins {
528
403
 		pins = "PB0", "PB1";
529
404
 		function = "uart0";
530
405
 	};
531
406
 
532
407
 };
533
408
 
409
+&tcon0 {
410
+	compatible = "allwinner,sun8i-a33-tcon";
411
+};
412
+
413
+&tcon0_out {
414
+	#address-cells = <1>;
415
+	#size-cells = <0>;
416
+
417
+	tcon0_out_dsi: endpoint@1 {
418
+		reg = <1>;
419
+		remote-endpoint = <&dsi_in_tcon0>;
420
+	};
421
+};
422
+
534
423
 &usb_otg {
535
424
 	compatible = "allwinner,sun8i-a33-musb";
536
425
 };