~ljy/RK356X_SDK_RELEASE.git

..	..	@@ -16,82 +16,12 @@
16	16	"google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
17	17	"google,veyron-jaq-rev1", "google,veyron-jaq",
18	18	"google,veyron", "rockchip,rk3288";
19		-
20		- panel_regulator: panel-regulator {
21		- compatible = "regulator-fixed";
22		- enable-active-high;
23		- gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
24		- pinctrl-names = "default";
25		- pinctrl-0 = <&lcd_enable_h>;
26		- regulator-name = "panel_regulator";
27		- startup-delay-us = <100000>;
28		- vin-supply = <&vcc33_sys>;
29		- };
30		-
31		- vcc18_lcd: vcc18-lcd {
32		- compatible = "regulator-fixed";
33		- enable-active-high;
34		- gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
35		- pinctrl-names = "default";
36		- pinctrl-0 = <&avdd_1v8_disp_en>;
37		- regulator-name = "vcc18_lcd";
38		- regulator-always-on;
39		- regulator-boot-on;
40		- vin-supply = <&vcc18_wl>;
41		- };
42		-
43		- backlight_regulator: backlight-regulator {
44		- compatible = "regulator-fixed";
45		- enable-active-high;
46		- gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
47		- pinctrl-names = "default";
48		- pinctrl-0 = <&bl_pwr_en>;
49		- regulator-name = "backlight_regulator";
50		- vin-supply = <&vcc33_sys>;
51		- startup-delay-us = <15000>;
52		- };
53	19	};
54	20
55	21	&backlight {
56	22	/* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
57		- brightness-levels = <
58		- 0
59		- 8 9 10 11 12 13 14 15
60		- 16 17 18 19 20 21 22 23
61		- 24 25 26 27 28 29 30 31
62		- 32 33 34 35 36 37 38 39
63		- 40 41 42 43 44 45 46 47
64		- 48 49 50 51 52 53 54 55
65		- 56 57 58 59 60 61 62 63
66		- 64 65 66 67 68 69 70 71
67		- 72 73 74 75 76 77 78 79
68		- 80 81 82 83 84 85 86 87
69		- 88 89 90 91 92 93 94 95
70		- 96 97 98 99 100 101 102 103
71		- 104 105 106 107 108 109 110 111
72		- 112 113 114 115 116 117 118 119
73		- 120 121 122 123 124 125 126 127
74		- 128 129 130 131 132 133 134 135
75		- 136 137 138 139 140 141 142 143
76		- 144 145 146 147 148 149 150 151
77		- 152 153 154 155 156 157 158 159
78		- 160 161 162 163 164 165 166 167
79		- 168 169 170 171 172 173 174 175
80		- 176 177 178 179 180 181 182 183
81		- 184 185 186 187 188 189 190 191
82		- 192 193 194 195 196 197 198 199
83		- 200 201 202 203 204 205 206 207
84		- 208 209 210 211 212 213 214 215
85		- 216 217 218 219 220 221 222 223
86		- 224 225 226 227 228 229 230 231
87		- 232 233 234 235 236 237 238 239
88		- 240 241 242 243 244 245 246 247
89		- 248 249 250 251 252 253 254 255>;
90		- power-supply = <&backlight_regulator>;
91		-};
92		-
93		-&panel {
94		- power-supply = <&panel_regulator>;
	23	+ brightness-levels = <0 8 255>;
	24	+ num-interpolated-steps = <247>;
95	25	};
96	26
97	27	&rk808 {
..	..	@@ -114,10 +44,25 @@
114	44	};
115	45	};
116	46
	47	+&sdio0 {
	48	+ #address-cells = <1>;
	49	+ #size-cells = <0>;
	50	+
	51	+ btmrvl: btmrvl@2 {
	52	+ compatible = "marvell,sd8897-bt";
	53	+ reg = <2>;
	54	+ interrupt-parent = <&gpio4>;
	55	+ interrupts = <RK_PD7 IRQ_TYPE_LEVEL_LOW>;
	56	+ marvell,wakeup-pin = /bits/ 16 <13>;
	57	+ pinctrl-names = "default";
	58	+ pinctrl-0 = <&bt_host_wake_l>;
	59	+ };
	60	+};
	61	+
117	62	&sdmmc {
118	63	disable-wp;
119	64	pinctrl-names = "default";
120		- pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
	65	+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
121	66	&sdmmc_bus4>;
122	67	};
123	68
..	..	@@ -135,12 +80,235 @@
135	80	pinctrl-0 = <&vcc50_hdmi_en>;
136	81	};
137	82
	83	+&gpio0 {
	84	+ gpio-line-names = "PMIC_SLEEP_AP",
	85	+ "DDRIO_PWROFF",
	86	+ "DDRIO_RETEN",
	87	+ "TS3A227E_INT_L",
	88	+ "PMIC_INT_L",
	89	+ "PWR_KEY_L",
	90	+ "AP_LID_INT_L",
	91	+ "EC_IN_RW",
	92	+
	93	+ "AC_PRESENT_AP",
	94	+ /*
	95	+ * RECOVERY_SW_L is Chrome OS ABI. Schematics call
	96	+ * it REC_MODE_L.
	97	+ */
	98	+ "RECOVERY_SW_L",
	99	+ "OTP_OUT",
	100	+ "HOST1_PWR_EN",
	101	+ "USBOTG_PWREN_H",
	102	+ "AP_WARM_RESET_H",
	103	+ "nFALUT2",
	104	+ "I2C0_SDA_PMIC",
	105	+
	106	+ "I2C0_SCL_PMIC",
	107	+ "SUSPEND_L",
	108	+ "USB_INT";
	109	+};
	110	+
	111	+&gpio2 {
	112	+ gpio-line-names = "CONFIG0",
	113	+ "CONFIG1",
	114	+ "CONFIG2",
	115	+ "",
	116	+ "",
	117	+ "",
	118	+ "",
	119	+ "CONFIG3",
	120	+
	121	+ "",
	122	+ "EMMC_RST_L",
	123	+ "",
	124	+ "",
	125	+ "BL_PWR_EN",
	126	+ "AVDD_1V8_DISP_EN";
	127	+};
	128	+
	129	+&gpio3 {
	130	+ gpio-line-names = "FLASH0_D0",
	131	+ "FLASH0_D1",
	132	+ "FLASH0_D2",
	133	+ "FLASH0_D3",
	134	+ "FLASH0_D4",
	135	+ "FLASH0_D5",
	136	+ "FLASH0_D6",
	137	+ "FLASH0_D7",
	138	+
	139	+ "",
	140	+ "",
	141	+ "",
	142	+ "",
	143	+ "",
	144	+ "",
	145	+ "",
	146	+ "",
	147	+
	148	+ "FLASH0_CS2/EMMC_CMD",
	149	+ "",
	150	+ "FLASH0_DQS/EMMC_CLKO";
	151	+};
	152	+
	153	+&gpio4 {
	154	+ gpio-line-names = "",
	155	+ "",
	156	+ "",
	157	+ "",
	158	+ "",
	159	+ "",
	160	+ "",
	161	+ "",
	162	+
	163	+ "",
	164	+ "",
	165	+ "",
	166	+ "",
	167	+ "",
	168	+ "",
	169	+ "",
	170	+ "",
	171	+
	172	+ "UART0_RXD",
	173	+ "UART0_TXD",
	174	+ "UART0_CTS",
	175	+ "UART0_RTS",
	176	+ "SDIO0_D0",
	177	+ "SDIO0_D1",
	178	+ "SDIO0_D2",
	179	+ "SDIO0_D3",
	180	+
	181	+ "SDIO0_CMD",
	182	+ "SDIO0_CLK",
	183	+ "BT_DEV_WAKE", /* Maybe missing from mighty? */
	184	+ "",
	185	+ "WIFI_ENABLE_H",
	186	+ "BT_ENABLE_L",
	187	+ "WIFI_HOST_WAKE",
	188	+ "BT_HOST_WAKE";
	189	+};
	190	+
	191	+&gpio5 {
	192	+ gpio-line-names = "",
	193	+ "",
	194	+ "",
	195	+ "",
	196	+ "",
	197	+ "",
	198	+ "",
	199	+ "",
	200	+
	201	+ "",
	202	+ "",
	203	+ "",
	204	+ "",
	205	+ "SPI0_CLK",
	206	+ "SPI0_CS0",
	207	+ "SPI0_TXD",
	208	+ "SPI0_RXD",
	209	+
	210	+ "",
	211	+ "",
	212	+ "",
	213	+ "VCC50_HDMI_EN";
	214	+};
	215	+
	216	+&gpio6 {
	217	+ gpio-line-names = "I2S0_SCLK",
	218	+ "I2S0_LRCK_RX",
	219	+ "I2S0_LRCK_TX",
	220	+ "I2S0_SDI",
	221	+ "I2S0_SDO0",
	222	+ "HP_DET_H",
	223	+ "ALS_INT",
	224	+ "INT_CODEC",
	225	+
	226	+ "I2S0_CLK",
	227	+ "I2C2_SDA",
	228	+ "I2C2_SCL",
	229	+ "MICDET",
	230	+ "",
	231	+ "",
	232	+ "",
	233	+ "",
	234	+
	235	+ "SDMMC_D0",
	236	+ "SDMMC_D1",
	237	+ "SDMMC_D2",
	238	+ "SDMMC_D3",
	239	+ "SDMMC_CLK",
	240	+ "SDMMC_CMD";
	241	+};
	242	+
	243	+&gpio7 {
	244	+ gpio-line-names = "LCDC_BL",
	245	+ "PWM_LOG",
	246	+ "BL_EN",
	247	+ "TRACKPAD_INT",
	248	+ "TPM_INT_H",
	249	+ "SDMMC_DET_L",
	250	+ /*
	251	+ * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
	252	+ * it FW_WP_AP.
	253	+ */
	254	+ "AP_FLASH_WP_L",
	255	+ "EC_INT",
	256	+
	257	+ "CPU_NMI",
	258	+ "DVSOK",
	259	+ "SDMMC_WP", /* mighty only */
	260	+ "EDP_HPD",
	261	+ "DVS1",
	262	+ "nFALUT1", /* nFAULT1 on jaq */
	263	+ "LCD_EN",
	264	+ "DVS2",
	265	+
	266	+ "VCC5V_GOOD_H",
	267	+ "I2C4_SDA_TP",
	268	+ "I2C4_SCL_TP",
	269	+ "I2C5_SDA_HDMI",
	270	+ "I2C5_SCL_HDMI",
	271	+ "5V_DRV",
	272	+ "UART2_RXD",
	273	+ "UART2_TXD";
	274	+};
	275	+
	276	+&gpio8 {
	277	+ gpio-line-names = "RAM_ID0",
	278	+ "RAM_ID1",
	279	+ "RAM_ID2",
	280	+ "RAM_ID3",
	281	+ "I2C1_SDA_TPM",
	282	+ "I2C1_SCL_TPM",
	283	+ "SPI2_CLK",
	284	+ "SPI2_CS0",
	285	+
	286	+ "SPI2_RXD",
	287	+ "SPI2_TXD";
	288	+};
	289	+
138	290	&pinctrl {
139		- backlight {
140		- bl_pwr_en: bl_pwr_en {
141		- rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
142		- };
143		- };
	291	+ pinctrl-names = "default", "sleep";
	292	+ pinctrl-0 = <
	293	+ /* Common for sleep and wake, but no owners */
	294	+ &ddr0_retention
	295	+ &ddrio_pwroff
	296	+ &global_pwroff
	297	+
	298	+ /* Wake only */
	299	+ &suspend_l_wake
	300	+ &bt_dev_wake_awake
	301	+ >;
	302	+ pinctrl-1 = <
	303	+ /* Common for sleep and wake, but no owners */
	304	+ &ddr0_retention
	305	+ &ddrio_pwroff
	306	+ &global_pwroff
	307	+
	308	+ /* Sleep only */
	309	+ &suspend_l_sleep
	310	+ &bt_dev_wake_sleep
	311	+ >;
144	312
145	313	buck-5v {
146	314	drv_5v: drv-5v {
..	..	@@ -151,16 +319,6 @@
151	319	hdmi {
152	320	vcc50_hdmi_en: vcc50-hdmi-en {
153	321	rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
154		- };
155		- };
156		-
157		- lcd {
158		- lcd_enable_h: lcd-en {
159		- rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
160		- };
161		-
162		- avdd_1v8_disp_en: avdd-1v8-disp-en {
163		- rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
164	322	};
165	323	};
166	324