.. | .. |
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73 | 73 | flush_cache(aligned_input, aligned_len); |
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74 | 74 | } |
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75 | 75 | |
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| 76 | +static void crypto_invalidate_cacheline(uint32_t addr, uint32_t size) |
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| 77 | +{ |
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| 78 | + ulong alignment = CONFIG_SYS_CACHELINE_SIZE; |
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| 79 | + ulong aligned_input, aligned_len; |
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| 80 | + |
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| 81 | + if (!addr || !size) |
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| 82 | + return; |
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| 83 | + |
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| 84 | + /* Must invalidate dcache after crypto DMA write data region */ |
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| 85 | + aligned_input = round_down(addr, alignment); |
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| 86 | + aligned_len = round_up(size + (addr - aligned_input), alignment); |
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| 87 | + invalidate_dcache_range(aligned_input, aligned_input + aligned_len); |
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| 88 | +} |
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| 89 | + |
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76 | 90 | static uint32_t trusty_base_write_security_data(char *filename, |
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77 | 91 | uint32_t filename_size, |
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78 | 92 | uint8_t *data, |
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.. | .. |
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1014 | 1028 | &TeecOperation, |
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1015 | 1029 | &ErrorOrigin); |
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1016 | 1030 | |
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| 1031 | + crypto_invalidate_cacheline(dst_phys_addr, len); |
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| 1032 | + |
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1017 | 1033 | exit: |
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1018 | 1034 | TEEC_ReleaseSharedMemory(&SharedMem_config); |
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1019 | 1035 | TEEC_CloseSession(&TeecSession); |
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