~hc/RK356X_SDK_RELEASE.git

..	..	@@ -17,20 +17,24 @@
17	17	#include <linux/list.h>
18	18	#include <linux/log2.h>
19	19	#include <linux/media-bus-format.h>
20		-#include <clk.h>
21	20	#include <asm/arch/clock.h>
	21	+#include <asm/gpio.h>
22	22	#include <linux/err.h>
23	23	#include <linux/ioport.h>
24	24	#include <dm/device.h>
25	25	#include <dm/read.h>
	26	+#include <dm/ofnode.h>
26	27	#include <fixp-arith.h>
27	28	#include <syscon.h>
28	29	#include <linux/iopoll.h>
29	30	#include <dm/uclass-internal.h>
	31	+#include <stdlib.h>
30	32
31	33	#include "rockchip_display.h"
32	34	#include "rockchip_crtc.h"
33	35	#include "rockchip_connector.h"
	36	+#include "rockchip_phy.h"
	37	+#include "rockchip_post_csc.h"
34	38
35	39	/* System registers definition */
36	40	#define RK3568_REG_CFG_DONE 0x000
..	..	@@ -40,9 +44,12 @@
40	44	#define EN_MASK 1
41	45
42	46	#define RK3568_AUTO_GATING_CTRL 0x008
	47	+#define AUTO_GATING_EN_SHIFT 31
	48	+#define PORT_DCLK_AUTO_GATING_EN_SHIFT 14
43	49
44	50	#define RK3568_SYS_AXI_LUT_CTRL 0x024
45	51	#define LUT_DMA_EN_SHIFT 0
	52	+#define DSP_VS_T_SEL_SHIFT 16
46	53
47	54	#define RK3568_DSP_IF_EN 0x028
48	55	#define RGB_EN_SHIFT 0
..	..	@@ -81,6 +88,9 @@
81	88	#define LVDS_DUAL_EN_SHIFT 0
82	89	#define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1
83	90	#define LVDS_DUAL_SWAP_EN_SHIFT 2
	91	+#define BT656_UV_SWAP 4
	92	+#define BT656_YC_SWAP 5
	93	+#define BT656_DCLK_POL 6
84	94	#define RK3588_HDMI_DUAL_EN_SHIFT 8
85	95	#define RK3588_EDP_DUAL_EN_SHIFT 8
86	96	#define RK3588_DP_DUAL_EN_SHIFT 9
..	..	@@ -93,15 +103,22 @@
93	103	#define IF_CTRL_REG_DONE_IMD_SHIFT 28
94	104	#define IF_CRTL_MIPI_DCLK_POL_SHIT 19
95	105	#define IF_CRTL_EDP_DCLK_POL_SHIT 15
	106	+#define IF_CTRL_EDP_PIN_POL_MASK 0x7
	107	+#define IF_CTRL_EDP_PIN_POL_SHIFT 12
96	108	#define IF_CRTL_HDMI_DCLK_POL_SHIT 7
97	109	#define IF_CRTL_HDMI_PIN_POL_MASK 0x7
98	110	#define IF_CRTL_HDMI_PIN_POL_SHIT 4
	111	+#define IF_CTRL_RGB_LVDS_DCLK_POL_SHIFT 3
	112	+#define IF_CTRL_RGB_LVDS_PIN_POL_MASK 0x7
	113	+#define IF_CTRL_RGB_LVDS_PIN_POL_SHIFT 0
	114	+
	115	+#define RK3562_MIPI_DCLK_POL_SHIFT 15
	116	+#define RK3562_MIPI_PIN_POL_SHIFT 12
	117	+#define RK3562_IF_PIN_POL_MASK 0x7
99	118
100	119	#define RK3588_DP0_PIN_POL_SHIFT 8
101	120	#define RK3588_DP1_PIN_POL_SHIFT 12
102	121	#define RK3588_IF_PIN_POL_MASK 0x7
103		-
104		-#define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3
105	122
106	123	#define HDMI_EDP0_DCLK_DIV_SHIFT 16
107	124	#define HDMI_EDP0_PIXCLK_DIV_SHIFT 18
..	..	@@ -118,6 +135,8 @@
118	135	#define GAMMA_AHB_WRITE_SEL_MASK 0x3
119	136	#define GAMMA_AHB_WRITE_SEL_SHIFT 12
120	137	#define PORT_MERGE_EN_SHIFT 16
	138	+#define ESMART_LB_MODE_SEL_MASK 0x3
	139	+#define ESMART_LB_MODE_SEL_SHIFT 26
121	140
122	141	#define RK3568_SYS_PD_CTRL 0x034
123	142	#define RK3568_VP0_LINE_FLAG 0x70
..	..	@@ -145,6 +164,11 @@
145	164	#define RK3588_DSC_8K_PD_EN_SHIFT 5
146	165	#define RK3588_DSC_4K_PD_EN_SHIFT 6
147	166	#define RK3588_ESMART_PD_EN_SHIFT 7
	167	+
	168	+#define RK3588_SYS_VAR_FREQ_CTRL 0x038
	169	+#define RK3588_VP0_LINE_FLAG_OR_EN_SHIFT 20
	170	+#define RK3588_VP0_DSP_HOLD_OR_EN_SHIFT 24
	171	+#define RK3588_VP0_ALMOST_FULL_OR_EN_SHIFT 28
148	172
149	173	#define RK3568_SYS_STATUS0 0x60
150	174	#define RK3588_CLUSTER0_PD_STATUS_SHIFT 8
..	..	@@ -212,10 +236,27 @@
212	236	#define RK3588_DSC_8K_STATUS 0x220
213	237
214	238	/* Overlay registers definition */
	239	+#define RK3528_OVL_SYS 0x500
	240	+#define RK3528_OVL_SYS_PORT_SEL_IMD 0x504
	241	+#define RK3528_OVL_SYS_GATING_EN_IMD 0x508
	242	+#define RK3528_OVL_SYS_CLUSTER0_CTRL 0x510
	243	+#define RK3528_OVL_SYS_ESMART0_CTRL 0x520
	244	+#define ESMART_DLY_NUM_MASK 0xff
	245	+#define ESMART_DLY_NUM_SHIFT 0
	246	+#define RK3528_OVL_SYS_ESMART1_CTRL 0x524
	247	+#define RK3528_OVL_SYS_ESMART2_CTRL 0x528
	248	+#define RK3528_OVL_SYS_ESMART3_CTRL 0x52C
	249	+#define RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL 0x530
	250	+#define RK3528_CLUSTER0_MIX_DST_COLOR_CTRL 0x534
	251	+#define RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538
	252	+#define RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c
	253	+
	254	+#define RK3528_OVL_PORT0_CTRL 0x600
215	255	#define RK3568_OVL_CTRL 0x600
216	256	#define OVL_MODE_SEL_MASK 0x1
217	257	#define OVL_MODE_SEL_SHIFT 0
218	258	#define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28
	259	+#define RK3528_OVL_PORT0_LAYER_SEL 0x604
219	260	#define RK3568_OVL_LAYER_SEL 0x604
220	261	#define LAYER_SEL_MASK 0xf
221	262
..	..	@@ -229,10 +270,27 @@
229	270	#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
230	271	#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
231	272	#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
	273	+#define RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL 0x620
	274	+#define RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL 0x624
	275	+#define RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL 0x628
	276	+#define RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL 0x62C
	277	+#define RK3528_OVL_PORT0_MIX1_SRC_COLOR_CTRL 0x630
	278	+#define RK3528_OVL_PORT0_MIX1_DST_COLOR_CTRL 0x634
	279	+#define RK3528_OVL_PORT0_MIX1_SRC_ALPHA_CTRL 0x638
	280	+#define RK3528_OVL_PORT0_MIX1_DST_ALPHA_CTRL 0x63C
	281	+#define RK3528_OVL_PORT0_MIX2_SRC_COLOR_CTRL 0x640
	282	+#define RK3528_OVL_PORT0_MIX2_DST_COLOR_CTRL 0x644
	283	+#define RK3528_OVL_PORT0_MIX2_SRC_ALPHA_CTRL 0x648
	284	+#define RK3528_OVL_PORT0_MIX2_DST_ALPHA_CTRL 0x64C
232	285	#define RK3568_MIX0_SRC_COLOR_CTRL 0x650
233	286	#define RK3568_MIX0_DST_COLOR_CTRL 0x654
234	287	#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658
235	288	#define RK3568_MIX0_DST_ALPHA_CTRL 0x65C
	289	+#define RK3528_HDR_SRC_COLOR_CTRL 0x660
	290	+#define RK3528_HDR_DST_COLOR_CTRL 0x664
	291	+#define RK3528_HDR_SRC_ALPHA_CTRL 0x668
	292	+#define RK3528_HDR_DST_ALPHA_CTRL 0x66C
	293	+#define RK3528_OVL_PORT0_BG_MIX_CTRL 0x670
236	294	#define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0
237	295	#define RK3568_HDR0_DST_COLOR_CTRL 0x6C4
238	296	#define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8
..	..	@@ -244,6 +302,22 @@
244	302	#define RK3568_VP2_BG_MIX_CTRL 0x6E8
245	303	#define RK3568_CLUSTER_DLY_NUM 0x6F0
246	304	#define RK3568_SMART_DLY_NUM 0x6F8
	305	+
	306	+#define RK3528_OVL_PORT1_CTRL 0x700
	307	+#define RK3528_OVL_PORT1_LAYER_SEL 0x704
	308	+#define RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL 0x720
	309	+#define RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL 0x724
	310	+#define RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL 0x728
	311	+#define RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL 0x72C
	312	+#define RK3528_OVL_PORT1_MIX1_SRC_COLOR_CTRL 0x730
	313	+#define RK3528_OVL_PORT1_MIX1_DST_COLOR_CTRL 0x734
	314	+#define RK3528_OVL_PORT1_MIX1_SRC_ALPHA_CTRL 0x738
	315	+#define RK3528_OVL_PORT1_MIX1_DST_ALPHA_CTRL 0x73C
	316	+#define RK3528_OVL_PORT1_MIX2_SRC_COLOR_CTRL 0x740
	317	+#define RK3528_OVL_PORT1_MIX2_DST_COLOR_CTRL 0x744
	318	+#define RK3528_OVL_PORT1_MIX2_SRC_ALPHA_CTRL 0x748
	319	+#define RK3528_OVL_PORT1_MIX2_DST_ALPHA_CTRL 0x74C
	320	+#define RK3528_OVL_PORT1_BG_MIX_CTRL 0x770
247	321
248	322	/* Video Port registers definition */
249	323	#define RK3568_VP0_DSP_CTRL 0xC00
..	..	@@ -263,6 +337,7 @@
263	337	#define POST_DSP_OUT_R2Y_SHIFT 15
264	338	#define PRE_DITHER_DOWN_EN_SHIFT 16
265	339	#define DITHER_DOWN_EN_SHIFT 17
	340	+#define DITHER_DOWN_MODE_SHIFT 20
266	341	#define GAMMA_UPDATE_EN_SHIFT 22
267	342	#define DSP_LUT_EN_SHIFT 28
268	343
..	..	@@ -279,6 +354,9 @@
279	354
280	355
281	356	#define RK3568_VP0_COLOR_BAR_CTRL 0xC08
	357	+
	358	+#define RK3568_VP0_DCLK_SEL 0xC0C
	359	+
282	360	#define RK3568_VP0_3D_LUT_CTRL 0xC10
283	361	#define VP0_3D_LUT_EN_SHIFT 0
284	362	#define VP0_3D_LUT_UPDATE_SHIFT 2
..	..	@@ -333,6 +411,50 @@
333	411	#define BCSH_EN_SHIFT 31
334	412	#define BCSH_EN_MASK 1
335	413
	414	+#define RK3528_VP0_ACM_CTRL 0xCD0
	415	+#define POST_CSC_COE00_MASK 0xFFFF
	416	+#define POST_CSC_COE00_SHIFT 16
	417	+#define POST_R2Y_MODE_MASK 0x7
	418	+#define POST_R2Y_MODE_SHIFT 8
	419	+#define POST_CSC_MODE_MASK 0x7
	420	+#define POST_CSC_MODE_SHIFT 3
	421	+#define POST_R2Y_EN_MASK 0x1
	422	+#define POST_R2Y_EN_SHIFT 2
	423	+#define POST_CSC_EN_MASK 0x1
	424	+#define POST_CSC_EN_SHIFT 1
	425	+#define POST_ACM_BYPASS_EN_MASK 0x1
	426	+#define POST_ACM_BYPASS_EN_SHIFT 0
	427	+#define RK3528_VP0_CSC_COE01_02 0xCD4
	428	+#define RK3528_VP0_CSC_COE10_11 0xCD8
	429	+#define RK3528_VP0_CSC_COE12_20 0xCDC
	430	+#define RK3528_VP0_CSC_COE21_22 0xCE0
	431	+#define RK3528_VP0_CSC_OFFSET0 0xCE4
	432	+#define RK3528_VP0_CSC_OFFSET1 0xCE8
	433	+#define RK3528_VP0_CSC_OFFSET2 0xCEC
	434	+
	435	+#define RK3562_VP0_MCU_CTRL 0xCF8
	436	+#define MCU_TYPE_SHIFT 31
	437	+#define MCU_BYPASS_SHIFT 30
	438	+#define MCU_RS_SHIFT 29
	439	+#define MCU_FRAME_ST_SHIFT 28
	440	+#define MCU_HOLD_MODE_SHIFT 27
	441	+#define MCU_CLK_SEL_SHIFT 26
	442	+#define MCU_CLK_SEL_MASK 0x1
	443	+#define MCU_RW_PEND_SHIFT 20
	444	+#define MCU_RW_PEND_MASK 0x3F
	445	+#define MCU_RW_PST_SHIFT 16
	446	+#define MCU_RW_PST_MASK 0xF
	447	+#define MCU_CS_PEND_SHIFT 10
	448	+#define MCU_CS_PEND_MASK 0x3F
	449	+#define MCU_CS_PST_SHIFT 6
	450	+#define MCU_CS_PST_MASK 0xF
	451	+#define MCU_PIX_TOTAL_SHIFT 0
	452	+#define MCU_PIX_TOTAL_MASK 0x3F
	453	+
	454	+#define RK3562_VP0_MCU_RW_BYPASS_PORT 0xCFC
	455	+#define MCU_WRITE_DATA_BYPASS_SHIFT 0
	456	+#define MCU_WRITE_DATA_BYPASS_MASK 0xFFFFFFFF
	457	+
336	458	#define RK3568_VP1_DSP_CTRL 0xD00
337	459	#define RK3568_VP1_MIPI_CTRL 0xD04
338	460	#define RK3568_VP1_COLOR_BAR_CTRL 0xD08
..	..	@@ -374,9 +496,20 @@
374	496	#define CLUSTER_YUV2RGB_EN_SHIFT 8
375	497	#define CLUSTER_RGB2YUV_EN_SHIFT 9
376	498	#define CLUSTER_CSC_MODE_SHIFT 10
377		-#define CLUSTER_YRGB_XSCL_MODE_SHIFT 12
378		-#define CLUSTER_YRGB_YSCL_MODE_SHIFT 14
	499	+#define CLUSTER_DITHER_UP_EN_SHIFT 18
379	500	#define RK3568_CLUSTER0_WIN0_CTRL1 0x1004
	501	+#define RK3568_CLUSTER_YRGB_XSCL_MODE_SHIFT 12
	502	+#define RK3568_CLUSTER_YRGB_YSCL_MODE_SHIFT 14
	503	+#define RK3528_CLUSTER_YRGB_YSCL_MODE_SHIFT 14
	504	+#define AVG2_MASK 0x1
	505	+#define CLUSTER_AVG2_SHIFT 18
	506	+#define AVG4_MASK 0x1
	507	+#define CLUSTER_AVG4_SHIFT 19
	508	+#define RK3528_CLUSTER_YRGB_XSCL_MODE_SHIFT 22
	509	+#define CLUSTER_XGT_EN_SHIFT 24
	510	+#define XGT_MODE_MASK 0x3
	511	+#define CLUSTER_XGT_MODE_SHIFT 25
	512	+#define CLUSTER_XAVG_EN_SHIFT 27
380	513	#define CLUSTER_YRGB_GT2_SHIFT 28
381	514	#define CLUSTER_YRGB_GT4_SHIFT 29
382	515	#define RK3568_CLUSTER0_WIN0_CTRL2 0x1008
..	..	@@ -399,6 +532,7 @@
399	532	#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064
400	533	#define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068
401	534	#define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C
	535	+#define CLUSTER_AFBCD_HALF_BLOCK_SHIFT 7
402	536
403	537	#define RK3568_CLUSTER0_WIN1_CTRL0 0x1080
404	538	#define RK3568_CLUSTER0_WIN1_CTRL1 0x1084
..	..	@@ -463,6 +597,8 @@
463	597	#define RGB2YUV_EN_SHIFT 1
464	598	#define CSC_MODE_SHIFT 2
465	599	#define CSC_MODE_MASK 0x3
	600	+#define ESMART_LB_SELECT_SHIFT 12
	601	+#define ESMART_LB_SELECT_MASK 0x3
466	602
467	603	#define RK3568_ESMART0_CTRL1 0x1804
468	604	#define ESMART_AXI_YRGB_ID_MASK 0x1f
..	..	@@ -476,10 +612,14 @@
476	612	#define ESMART_AXI_ID_SHIFT 1
477	613
478	614	#define RK3568_ESMART0_REGION0_CTRL 0x1810
479		-#define REGION0_RB_SWAP_SHIFT 14
480	615	#define WIN_EN_SHIFT 0
481	616	#define WIN_FORMAT_MASK 0x1f
482	617	#define WIN_FORMAT_SHIFT 1
	618	+#define REGION0_DITHER_UP_EN_SHIFT 12
	619	+#define REGION0_RB_SWAP_SHIFT 14
	620	+#define ESMART_XAVG_EN_SHIFT 20
	621	+#define ESMART_XGT_EN_SHIFT 21
	622	+#define ESMART_XGT_MODE_SHIFT 22
483	623
484	624	#define RK3568_ESMART0_REGION0_YRGB_MST 0x1814
485	625	#define RK3568_ESMART0_REGION0_CBR_MST 0x1818
..	..	@@ -680,6 +820,13 @@
680	820	#define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8
681	821	#define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC
682	822
	823	+/* HDR register definition */
	824	+#define RK3568_HDR_LUT_CTRL 0x2000
	825	+
	826	+#define RK3588_VP3_DSP_CTRL 0xF00
	827	+#define RK3588_CLUSTER2_WIN0_CTRL0 0x1400
	828	+#define RK3588_CLUSTER3_WIN0_CTRL0 0x1600
	829	+
683	830	/* DSC 8K/4K register definition */
684	831	#define RK3588_DSC_8K_PPS0_3 0x4000
685	832	#define RK3588_DSC_8K_CTRL0 0x40A0
..	..	@@ -690,10 +837,14 @@
690	837	#define DSC_MER_SHIFT 5
691	838	#define DSC_EPB_SHIFT 6
692	839	#define DSC_EPL_SHIFT 7
	840	+#define DSC_NSLC_MASK 0x7
693	841	#define DSC_NSLC_SHIFT 16
694	842	#define DSC_SBO_SHIFT 28
695	843	#define DSC_IFEP_SHIFT 29
696	844	#define DSC_PPS_UPD_SHIFT 31
	845	+#define DSC_CTRL0_DEF_CON ((1 << DSC_EN_SHIFT) \| (1 << DSC_RBIT_SHIFT) \| (0 << DSC_RBYT_SHIFT) \| \
	846	+ (1 << DSC_FLAL_SHIFT) \| (1 << DSC_MER_SHIFT) \| (0 << DSC_EPB_SHIFT) \| \
	847	+ (1 << DSC_EPL_SHIFT) \| (1 << DSC_SBO_SHIFT))
697	848
698	849	#define RK3588_DSC_8K_CTRL1 0x40A4
699	850	#define RK3588_DSC_8K_STS0 0x40A8
..	..	@@ -705,8 +856,24 @@
705	856	#define RK3588_DSC_4K_STS0 0x41A8
706	857	#define RK3588_DSC_4K_ERS 0x41C4
707	858
	859	+/* RK3528 HDR register definition */
	860	+#define RK3528_HDR_LUT_CTRL 0x2000
	861	+
	862	+/* RK3528 ACM register definition */
	863	+#define RK3528_ACM_CTRL 0x6400
	864	+#define RK3528_ACM_DELTA_RANGE 0x6404
	865	+#define RK3528_ACM_FETCH_START 0x6408
	866	+#define RK3528_ACM_FETCH_DONE 0x6420
	867	+#define RK3528_ACM_YHS_DEL_HY_SEG0 0x6500
	868	+#define RK3528_ACM_YHS_DEL_HY_SEG152 0x6760
	869	+#define RK3528_ACM_YHS_DEL_HS_SEG0 0x6764
	870	+#define RK3528_ACM_YHS_DEL_HS_SEG220 0x6ad4
	871	+#define RK3528_ACM_YHS_DEL_HGAIN_SEG0 0x6ad8
	872	+#define RK3528_ACM_YHS_DEL_HGAIN_SEG64 0x6bd8
	873	+
708	874	#define RK3568_MAX_REG 0x1ED0
709	875
	876	+#define RK3562_GRF_IOC_VO_IO_CON 0x10500
710	877	#define RK3568_GRF_VO_CON1 0x0364
711	878	#define GRF_BT656_CLK_INV_SHIFT 1
712	879	#define GRF_BT1120_CLK_INV_SHIFT 2
..	..	@@ -771,11 +938,52 @@
771	938
772	939	#define VOP2_PLANE_NO_SCALING BIT(16)
773	940
774		-enum vop2_csc_format {
	941	+#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
	942	+#define VOP_FEATURE_AFBDC BIT(1)
	943	+#define VOP_FEATURE_ALPHA_SCALE BIT(2)
	944	+#define VOP_FEATURE_HDR10 BIT(3)
	945	+#define VOP_FEATURE_NEXT_HDR BIT(4)
	946	+/* a feature to splice two windows and two vps to support resolution > 4096 */
	947	+#define VOP_FEATURE_SPLICE BIT(5)
	948	+#define VOP_FEATURE_OVERSCAN BIT(6)
	949	+#define VOP_FEATURE_VIVID_HDR BIT(7)
	950	+#define VOP_FEATURE_POST_ACM BIT(8)
	951	+#define VOP_FEATURE_POST_CSC BIT(9)
	952	+
	953	+#define WIN_FEATURE_HDR2SDR BIT(0)
	954	+#define WIN_FEATURE_SDR2HDR BIT(1)
	955	+#define WIN_FEATURE_PRE_OVERLAY BIT(2)
	956	+#define WIN_FEATURE_AFBDC BIT(3)
	957	+#define WIN_FEATURE_CLUSTER_MAIN BIT(4)
	958	+#define WIN_FEATURE_CLUSTER_SUB BIT(5)
	959	+/* a mirror win can only get fb address
	960	+ * from source win:
	961	+ * Cluster1---->Cluster0
	962	+ * Esmart1 ---->Esmart0
	963	+ * Smart1 ---->Smart0
	964	+ * This is a feather on rk3566
	965	+ */
	966	+#define WIN_FEATURE_MIRROR BIT(6)
	967	+#define WIN_FEATURE_MULTI_AREA BIT(7)
	968	+#define WIN_FEATURE_Y2R_13BIT_DEPTH BIT(8)
	969	+
	970	+#define V4L2_COLORSPACE_BT709F 0xfe
	971	+#define V4L2_COLORSPACE_BT2020F 0xff
	972	+
	973	+enum vop_csc_format {
775	974	CSC_BT601L,
776	975	CSC_BT709L,
777	976	CSC_BT601F,
778	977	CSC_BT2020,
	978	+ CSC_BT709L_13BIT,
	979	+ CSC_BT709F_13BIT,
	980	+ CSC_BT2020L_13BIT,
	981	+ CSC_BT2020F_13BIT,
	982	+};
	983	+
	984	+enum vop_csc_bit_depth {
	985	+ CSC_10BIT_DEPTH,
	986	+ CSC_13BIT_DEPTH,
779	987	};
780	988
781	989	enum vop2_pol {
..	..	@@ -861,6 +1069,19 @@
861	1069	VOP_DSC_IF_MIPI_VIDEO_MODE = 3,
862	1070	};
863	1071
	1072	+enum vop3_pre_scale_down_mode {
	1073	+ VOP3_PRE_SCALE_UNSPPORT,
	1074	+ VOP3_PRE_SCALE_DOWN_GT,
	1075	+ VOP3_PRE_SCALE_DOWN_AVG,
	1076	+};
	1077	+
	1078	+enum vop3_esmart_lb_mode {
	1079	+ VOP3_ESMART_8K_MODE,
	1080	+ VOP3_ESMART_4K_4K_MODE,
	1081	+ VOP3_ESMART_4K_2K_2K_MODE,
	1082	+ VOP3_ESMART_2K_2K_2K_2K_MODE,
	1083	+};
	1084	+
864	1085	struct vop2_layer {
865	1086	u8 id;
866	1087	/**
..	..	@@ -886,12 +1107,19 @@
886	1107	u8 phys_id;
887	1108	enum vop2_layer_type type;
888	1109	u8 win_sel_port_offset;
889		- u8 layer_sel_win_id;
	1110	+ u8 layer_sel_win_id[VOP2_VP_MAX];
890	1111	u8 axi_id;
891	1112	u8 axi_uv_id;
892	1113	u8 axi_yrgb_id;
893	1114	u8 splice_win_id;
894	1115	u8 pd_id;
	1116	+ u8 hsu_filter_mode;
	1117	+ u8 hsd_filter_mode;
	1118	+ u8 vsu_filter_mode;
	1119	+ u8 vsd_filter_mode;
	1120	+ u8 hsd_pre_filter_mode;
	1121	+ u8 vsd_pre_filter_mode;
	1122	+ u8 scale_engine_num;
895	1123	u32 reg_offset;
896	1124	u32 max_upscale_factor;
897	1125	u32 max_downscale_factor;
..	..	@@ -901,6 +1129,9 @@
901	1129	struct vop2_vp_data {
902	1130	u32 feature;
903	1131	u8 pre_scan_max_dly;
	1132	+ u8 layer_mix_dly;
	1133	+ u8 hdr_mix_dly;
	1134	+ u8 win_dly;
904	1135	u8 splice_vp_id;
905	1136	struct vop_rect max_output;
906	1137	u32 max_dclk;
..	..	@@ -936,8 +1167,18 @@
936	1167	char dsc_error_info[50];
937	1168	};
938	1169
	1170	+struct vop2_dump_regs {
	1171	+ u32 offset;
	1172	+ const char *name;
	1173	+ u32 state_base;
	1174	+ u32 state_mask;
	1175	+ u32 state_shift;
	1176	+ bool enable_state;
	1177	+};
	1178	+
939	1179	struct vop2_data {
940	1180	u32 version;
	1181	+ u32 esmart_lb_mode;
941	1182	struct vop2_vp_data *vp_data;
942	1183	struct vop2_win_data *win_data;
943	1184	struct vop2_vp_plane_mask *plane_mask;
..	..	@@ -946,6 +1187,8 @@
946	1187	struct vop2_dsc_data *dsc;
947	1188	struct dsc_error_info *dsc_error_ecw;
948	1189	struct dsc_error_info *dsc_error_buffer_flow;
	1190	+ struct vop2_dump_regs *dump_regs;
	1191	+ u8 *vp_primary_plane_order;
949	1192	u8 nr_vps;
950	1193	u8 nr_layers;
951	1194	u8 nr_mixers;
..	..	@@ -955,6 +1198,7 @@
955	1198	u8 nr_dsc_ecw;
956	1199	u8 nr_dsc_buffer_flow;
957	1200	u32 reg_len;
	1201	+ u32 dump_regs_size;
958	1202	};
959	1203
960	1204	struct vop2 {
..	..	@@ -966,12 +1210,22 @@
966	1210	void *sys_pmu;
967	1211	u32 reg_len;
968	1212	u32 version;
	1213	+ u32 esmart_lb_mode;
969	1214	bool global_init;
970	1215	const struct vop2_data *data;
971	1216	struct vop2_vp_plane_mask vp_plane_mask[VOP2_VP_MAX];
972	1217	};
973	1218
974	1219	static struct vop2 *rockchip_vop2;
	1220	+
	1221	+static inline bool is_vop3(struct vop2 *vop2)
	1222	+{
	1223	+ if (vop2->version == VOP_VERSION_RK3568 \|\| vop2->version == VOP_VERSION_RK3588)
	1224	+ return false;
	1225	+ else
	1226	+ return true;
	1227	+}
	1228	+
975	1229	/*
976	1230	* bli_sd_factor = (src - 1) / (dst - 1) << 12;
977	1231	* avg_sd_factor:
..	..	@@ -979,8 +1233,8 @@
979	1233	* bic_su_factor:
980	1234	* = (src - 1) / (dst - 1) << 16;
981	1235	*
982		- * gt2 enable: dst get one line from two line of the src
983		- * gt4 enable: dst get one line from four line of the src.
	1236	+ * ygt2 enable: dst get one line from two line of the src
	1237	+ * ygt4 enable: dst get one line from four line of the src.
984	1238	*
985	1239	*/
986	1240	#define VOP2_BILI_SCL_DN(src, dst) (((src - 1) << 12) / (dst - 1))
..	..	@@ -989,6 +1243,8 @@
989	1243	#define VOP2_BILI_SCL_FAC_CHECK(src, dst, fac) \
990	1244	(fac * (dst - 1) >> 12 < (src - 1))
991	1245	#define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \
	1246	+ (fac * (dst - 1) >> 16 < (src - 1))
	1247	+#define VOP3_COMMON_HOR_SCL_FAC_CHECK(src, dst, fac) \
992	1248	(fac * (dst - 1) >> 16 < (src - 1))
993	1249
994	1250	static uint16_t vop2_scale_factor(enum scale_mode mode,
..	..	@@ -1030,6 +1286,51 @@
1030	1286	return fac;
1031	1287	}
1032	1288
	1289	+static bool vop3_scale_up_fac_check(uint32_t src, uint32_t dst, uint32_t fac, bool is_hor)
	1290	+{
	1291	+ if (is_hor)
	1292	+ return VOP3_COMMON_HOR_SCL_FAC_CHECK(src, dst, fac);
	1293	+ return VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac);
	1294	+}
	1295	+
	1296	+static uint16_t vop3_scale_factor(enum scale_mode mode,
	1297	+ uint32_t src, uint32_t dst, bool is_hor)
	1298	+{
	1299	+ uint32_t fac = 0;
	1300	+ int i = 0;
	1301	+
	1302	+ if (mode == SCALE_NONE)
	1303	+ return 0;
	1304	+
	1305	+ /*
	1306	+ * A workaround to avoid zero div.
	1307	+ */
	1308	+ if ((dst == 1) \|\| (src == 1)) {
	1309	+ dst = dst + 1;
	1310	+ src = src + 1;
	1311	+ }
	1312	+
	1313	+ if (mode == SCALE_DOWN) {
	1314	+ fac = VOP2_BILI_SCL_DN(src, dst);
	1315	+ for (i = 0; i < 100; i++) {
	1316	+ if (VOP2_BILI_SCL_FAC_CHECK(src, dst, fac))
	1317	+ break;
	1318	+ fac -= 1;
	1319	+ printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac);
	1320	+ }
	1321	+ } else {
	1322	+ fac = VOP2_COMMON_SCL(src, dst);
	1323	+ for (i = 0; i < 100; i++) {
	1324	+ if (vop3_scale_up_fac_check(src, dst, fac, is_hor))
	1325	+ break;
	1326	+ fac -= 1;
	1327	+ printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac);
	1328	+ }
	1329	+ }
	1330	+
	1331	+ return fac;
	1332	+}
	1333	+
1033	1334	static inline enum scale_mode scl_get_scl_mode(int src, int dst)
1034	1335	{
1035	1336	if (src < dst)
..	..	@@ -1040,19 +1341,6 @@
1040	1341	return SCALE_NONE;
1041	1342	}
1042	1343
1043		-static u8 rk3588_vop2_vp_primary_plane_order[VOP2_VP_MAX] = {
1044		- ROCKCHIP_VOP2_ESMART0,
1045		- ROCKCHIP_VOP2_ESMART1,
1046		- ROCKCHIP_VOP2_ESMART2,
1047		- ROCKCHIP_VOP2_ESMART3,
1048		-};
1049		-
1050		-static u8 rk3568_vop2_vp_primary_plane_order[VOP2_VP_MAX] = {
1051		- ROCKCHIP_VOP2_SMART0,
1052		- ROCKCHIP_VOP2_SMART1,
1053		- ROCKCHIP_VOP2_ESMART1,
1054		-};
1055		-
1056	1344	static inline int interpolate(int x1, int y1, int x2, int y2, int x)
1057	1345	{
1058	1346	return y1 + (y2 - y1) * (x - x1) / (x2 - x1);
..	..	@@ -1061,23 +1349,13 @@
1061	1349	static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask)
1062	1350	{
1063	1351	int i = 0;
1064		- u8 *vop2_vp_primary_plane_order;
1065		- u8 default_primary_plane;
1066	1352
1067		- if (vop2->version == VOP_VERSION_RK3588) {
1068		- vop2_vp_primary_plane_order = rk3588_vop2_vp_primary_plane_order;
1069		- default_primary_plane = ROCKCHIP_VOP2_ESMART0;
1070		- } else {
1071		- vop2_vp_primary_plane_order = rk3568_vop2_vp_primary_plane_order;
1072		- default_primary_plane = ROCKCHIP_VOP2_SMART0;
	1353	+ for (i = 0; i < vop2->data->nr_layers; i++) {
	1354	+ if (plane_mask & BIT(vop2->data->vp_primary_plane_order[i]))
	1355	+ return vop2->data->vp_primary_plane_order[i];
1073	1356	}
1074	1357
1075		- for (i = 0; i < vop2->data->nr_vps; i++) {
1076		- if (plane_mask & BIT(vop2_vp_primary_plane_order[i]))
1077		- return vop2_vp_primary_plane_order[i];
1078		- }
1079		-
1080		- return default_primary_plane;
	1358	+ return vop2->data->vp_primary_plane_order[0];
1081	1359	}
1082	1360
1083	1361	static inline u16 scl_cal_scale(int src, int dst, int shift)
..	..	@@ -1210,6 +1488,7 @@
1210	1488	switch (bus_format) {
1211	1489	case MEDIA_BUS_FMT_YUV8_1X24:
1212	1490	case MEDIA_BUS_FMT_YUV10_1X30:
	1491	+ case MEDIA_BUS_FMT_YUYV10_1X20:
1213	1492	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1214	1493	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1215	1494	case MEDIA_BUS_FMT_YUYV8_2X8:
..	..	@@ -1226,7 +1505,7 @@
1226	1505	}
1227	1506	}
1228	1507
1229		-static int vop2_convert_csc_mode(int csc_mode)
	1508	+static int vop2_convert_csc_mode(int csc_mode, int bit_depth)
1230	1509	{
1231	1510	switch (csc_mode) {
1232	1511	case V4L2_COLORSPACE_SMPTE170M:
..	..	@@ -1236,11 +1515,31 @@
1236	1515	case V4L2_COLORSPACE_REC709:
1237	1516	case V4L2_COLORSPACE_SMPTE240M:
1238	1517	case V4L2_COLORSPACE_DEFAULT:
1239		- return CSC_BT709L;
	1518	+ if (bit_depth == CSC_13BIT_DEPTH)
	1519	+ return CSC_BT709L_13BIT;
	1520	+ else
	1521	+ return CSC_BT709L;
1240	1522	case V4L2_COLORSPACE_JPEG:
1241	1523	return CSC_BT601F;
1242	1524	case V4L2_COLORSPACE_BT2020:
1243		- return CSC_BT2020;
	1525	+ if (bit_depth == CSC_13BIT_DEPTH)
	1526	+ return CSC_BT2020L_13BIT;
	1527	+ else
	1528	+ return CSC_BT2020;
	1529	+ case V4L2_COLORSPACE_BT709F:
	1530	+ if (bit_depth == CSC_10BIT_DEPTH) {
	1531	+ printf("WARN: Unsupported bt709f at 10bit csc depth, use bt601f instead\n");
	1532	+ return CSC_BT601F;
	1533	+ } else {
	1534	+ return CSC_BT709F_13BIT;
	1535	+ }
	1536	+ case V4L2_COLORSPACE_BT2020F:
	1537	+ if (bit_depth == CSC_10BIT_DEPTH) {
	1538	+ printf("WARN: Unsupported bt2020f at 10bit csc depth, use bt601f instead\n");
	1539	+ return CSC_BT601F;
	1540	+ } else {
	1541	+ return CSC_BT2020F_13BIT;
	1542	+ }
1244	1543	default:
1245	1544	return CSC_BT709L;
1246	1545	}
..	..	@@ -1265,6 +1564,19 @@
1265	1564	bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
1266	1565	(output_mode == ROCKCHIP_OUT_MODE_AAAA \|\|
1267	1566	output_mode == ROCKCHIP_OUT_MODE_P888)))
	1567	+ return true;
	1568	+ else
	1569	+ return false;
	1570	+}
	1571	+
	1572	+static bool is_rb_swap(u32 bus_format, u32 output_mode)
	1573	+{
	1574	+ /*
	1575	+ * The default component order of serial rgb3x8 formats
	1576	+ * is BGR. So it is needed to enable RB swap.
	1577	+ */
	1578	+ if (bus_format == MEDIA_BUS_FMT_SRGB888_3X8 \|\|
	1579	+ bus_format == MEDIA_BUS_FMT_SRGB888_DUMMY_4X8)
1268	1580	return true;
1269	1581	else
1270	1582	return false;
..	..	@@ -1533,7 +1845,7 @@
1533	1845	cstate->post_y2r_en = 1;
1534	1846	}
1535	1847
1536		- cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space);
	1848	+ cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_10BIT_DEPTH);
1537	1849
1538	1850	if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT)
1539	1851	brightness = interpolate(0, -128, 100, 127,
..	..	@@ -1578,7 +1890,7 @@
1578	1890	u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
1579	1891
1580	1892	bg_ovl_dly = cstate->crtc->vps[crtc_id].bg_ovl_dly;
1581		- bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly;
	1893	+ bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly;
1582	1894	bg_dly -= bg_ovl_dly;
1583	1895
1584	1896	if (cstate->splice_mode)
..	..	@@ -1590,6 +1902,33 @@
1590	1902	hsync_len = 8;
1591	1903	pre_scan_dly = (pre_scan_dly << 16) \| hsync_len;
1592	1904	vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + crtc_id * 4,
	1905	+ BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false);
	1906	+ vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly);
	1907	+}
	1908	+
	1909	+static void vop3_setup_pipe_dly(struct display_state state, struct vop2 vop2, int crtc_id)
	1910	+{
	1911	+ struct connector_state *conn_state = &state->conn_state;
	1912	+ struct drm_display_mode *mode = &conn_state->mode;
	1913	+ struct crtc_state *cstate = &state->crtc_state;
	1914	+ struct vop2_win_data *win_data;
	1915	+ u32 bg_dly, pre_scan_dly;
	1916	+ u16 hdisplay = mode->crtc_hdisplay;
	1917	+ u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
	1918	+ u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id;
	1919	+ u8 win_id;
	1920	+
	1921	+ win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id);
	1922	+ win_id = atoi(&win_data->name[strlen(win_data->name) - 1]);
	1923	+ vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART0_CTRL + win_id * 4,
	1924	+ ESMART_DLY_NUM_MASK, ESMART_DLY_NUM_SHIFT, 0, false);
	1925	+
	1926	+ bg_dly = vop2->data->vp_data[crtc_id].win_dly +
	1927	+ vop2->data->vp_data[crtc_id].layer_mix_dly +
	1928	+ vop2->data->vp_data[crtc_id].hdr_mix_dly;
	1929	+ pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
	1930	+ pre_scan_dly = (pre_scan_dly << 16) \| hsync_len;
	1931	+ vop2_mask_write(vop2, RK3528_OVL_PORT0_BG_MIX_CTRL + crtc_id * 0x100,
1593	1932	BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false);
1594	1933	vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly);
1595	1934	}
..	..	@@ -1644,9 +1983,176 @@
1644	1983	vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val);
1645	1984	}
1646	1985
1647		- vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id);
1648		- if (cstate->splice_mode)
1649		- vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id);
	1986	+ if (is_vop3(vop2)) {
	1987	+ vop3_setup_pipe_dly(state, vop2, cstate->crtc_id);
	1988	+ } else {
	1989	+ vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id);
	1990	+ if (cstate->splice_mode)
	1991	+ vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id);
	1992	+ }
	1993	+}
	1994	+
	1995	+static void vop3_post_acm_config(struct display_state state, struct vop2 vop2)
	1996	+{
	1997	+ struct connector_state *conn_state = &state->conn_state;
	1998	+ struct crtc_state *cstate = &state->crtc_state;
	1999	+ struct acm_data *acm = &conn_state->disp_info->acm_data;
	2000	+ struct drm_display_mode *mode = &conn_state->mode;
	2001	+ u32 vp_offset = (cstate->crtc_id * 0x100);
	2002	+ s16 *lut_y;
	2003	+ s16 *lut_h;
	2004	+ s16 *lut_s;
	2005	+ u32 value;
	2006	+ int i;
	2007	+
	2008	+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
	2009	+ POST_ACM_BYPASS_EN_MASK, POST_ACM_BYPASS_EN_SHIFT, 0, false);
	2010	+ if (!acm->acm_enable) {
	2011	+ writel(0, vop2->regs + RK3528_ACM_CTRL);
	2012	+ return;
	2013	+ }
	2014	+
	2015	+ printf("post acm enable\n");
	2016	+
	2017	+ writel(1, vop2->regs + RK3528_ACM_FETCH_START);
	2018	+
	2019	+ value = (acm->acm_enable & 0x1) + ((mode->hdisplay & 0xfff) << 8) +
	2020	+ ((mode->vdisplay & 0xfff) << 20);
	2021	+ writel(value, vop2->regs + RK3528_ACM_CTRL);
	2022	+
	2023	+ value = (acm->y_gain & 0x3ff) + ((acm->h_gain << 10) & 0xffc00) +
	2024	+ ((acm->s_gain << 20) & 0x3ff00000);
	2025	+ writel(value, vop2->regs + RK3528_ACM_DELTA_RANGE);
	2026	+
	2027	+ lut_y = &acm->gain_lut_hy[0];
	2028	+ lut_h = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH];
	2029	+ lut_s = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH * 2];
	2030	+ for (i = 0; i < ACM_GAIN_LUT_HY_LENGTH; i++) {
	2031	+ value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) +
	2032	+ ((lut_s[i] << 16) & 0xff0000);
	2033	+ writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HY_SEG0 + (i << 2));
	2034	+ }
	2035	+
	2036	+ lut_y = &acm->gain_lut_hs[0];
	2037	+ lut_h = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH];
	2038	+ lut_s = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH * 2];
	2039	+ for (i = 0; i < ACM_GAIN_LUT_HS_LENGTH; i++) {
	2040	+ value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) +
	2041	+ ((lut_s[i] << 16) & 0xff0000);
	2042	+ writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HS_SEG0 + (i << 2));
	2043	+ }
	2044	+
	2045	+ lut_y = &acm->delta_lut_h[0];
	2046	+ lut_h = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH];
	2047	+ lut_s = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH * 2];
	2048	+ for (i = 0; i < ACM_DELTA_LUT_H_LENGTH; i++) {
	2049	+ value = (lut_y[i] & 0x3ff) + ((lut_h[i] << 12) & 0xff000) +
	2050	+ ((lut_s[i] << 20) & 0x3ff00000);
	2051	+ writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HGAIN_SEG0 + (i << 2));
	2052	+ }
	2053	+
	2054	+ writel(1, vop2->regs + RK3528_ACM_FETCH_DONE);
	2055	+}
	2056	+
	2057	+static void vop3_post_csc_config(struct display_state state, struct vop2 vop2)
	2058	+{
	2059	+ struct connector_state *conn_state = &state->conn_state;
	2060	+ struct crtc_state *cstate = &state->crtc_state;
	2061	+ struct acm_data *acm = &conn_state->disp_info->acm_data;
	2062	+ struct csc_info *csc = &conn_state->disp_info->csc_info;
	2063	+ struct post_csc_coef csc_coef;
	2064	+ bool is_input_yuv = false;
	2065	+ bool is_output_yuv = false;
	2066	+ bool post_r2y_en = false;
	2067	+ bool post_csc_en = false;
	2068	+ u32 vp_offset = (cstate->crtc_id * 0x100);
	2069	+ u32 value;
	2070	+ int range_type;
	2071	+
	2072	+ printf("post csc enable\n");
	2073	+
	2074	+ if (acm->acm_enable) {
	2075	+ if (!cstate->yuv_overlay)
	2076	+ post_r2y_en = true;
	2077	+
	2078	+ /* do y2r in csc module */
	2079	+ if (!is_yuv_output(conn_state->bus_format))
	2080	+ post_csc_en = true;
	2081	+ } else {
	2082	+ if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format))
	2083	+ post_r2y_en = true;
	2084	+
	2085	+ /* do y2r in csc module */
	2086	+ if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format))
	2087	+ post_csc_en = true;
	2088	+ }
	2089	+
	2090	+ if (csc->csc_enable)
	2091	+ post_csc_en = true;
	2092	+
	2093	+ if (cstate->yuv_overlay \|\| post_r2y_en)
	2094	+ is_input_yuv = true;
	2095	+
	2096	+ if (is_yuv_output(conn_state->bus_format))
	2097	+ is_output_yuv = true;
	2098	+
	2099	+ cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_13BIT_DEPTH);
	2100	+
	2101	+ if (post_csc_en) {
	2102	+ rockchip_calc_post_csc(csc, &csc_coef, cstate->post_csc_mode, is_input_yuv,
	2103	+ is_output_yuv);
	2104	+
	2105	+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
	2106	+ POST_CSC_COE00_MASK, POST_CSC_COE00_SHIFT,
	2107	+ csc_coef.csc_coef00, false);
	2108	+ value = csc_coef.csc_coef01 & 0xffff;
	2109	+ value \|= (csc_coef.csc_coef02 << 16) & 0xffff0000;
	2110	+ writel(value, vop2->regs + RK3528_VP0_CSC_COE01_02);
	2111	+ value = csc_coef.csc_coef10 & 0xffff;
	2112	+ value \|= (csc_coef.csc_coef11 << 16) & 0xffff0000;
	2113	+ writel(value, vop2->regs + RK3528_VP0_CSC_COE10_11);
	2114	+ value = csc_coef.csc_coef12 & 0xffff;
	2115	+ value \|= (csc_coef.csc_coef20 << 16) & 0xffff0000;
	2116	+ writel(value, vop2->regs + RK3528_VP0_CSC_COE12_20);
	2117	+ value = csc_coef.csc_coef21 & 0xffff;
	2118	+ value \|= (csc_coef.csc_coef22 << 16) & 0xffff0000;
	2119	+ writel(value, vop2->regs + RK3528_VP0_CSC_COE21_22);
	2120	+ writel(csc_coef.csc_dc0, vop2->regs + RK3528_VP0_CSC_OFFSET0);
	2121	+ writel(csc_coef.csc_dc1, vop2->regs + RK3528_VP0_CSC_OFFSET1);
	2122	+ writel(csc_coef.csc_dc2, vop2->regs + RK3528_VP0_CSC_OFFSET2);
	2123	+
	2124	+ range_type = csc_coef.range_type ? 0 : 1;
	2125	+ range_type <<= is_input_yuv ? 0 : 1;
	2126	+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
	2127	+ POST_CSC_MODE_MASK, POST_CSC_MODE_SHIFT, range_type, false);
	2128	+ }
	2129	+
	2130	+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
	2131	+ POST_R2Y_EN_MASK, POST_R2Y_EN_SHIFT, post_r2y_en ? 1 : 0, false);
	2132	+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
	2133	+ POST_CSC_EN_MASK, POST_CSC_EN_SHIFT, post_csc_en ? 1 : 0, false);
	2134	+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
	2135	+ POST_R2Y_MODE_MASK, POST_R2Y_MODE_SHIFT, cstate->post_csc_mode, false);
	2136	+}
	2137	+
	2138	+static void vop3_post_config(struct display_state state, struct vop2 vop2)
	2139	+{
	2140	+ struct connector_state *conn_state = &state->conn_state;
	2141	+ struct base2_disp_info *disp_info = conn_state->disp_info;
	2142	+ const char *enable_flag;
	2143	+ if (!disp_info) {
	2144	+ printf("disp_info is empty\n");
	2145	+ return;
	2146	+ }
	2147	+
	2148	+ enable_flag = (const char *)&disp_info->cacm_header;
	2149	+ if (strncasecmp(enable_flag, "CACM", 4)) {
	2150	+ printf("acm and csc is not support\n");
	2151	+ return;
	2152	+ }
	2153	+
	2154	+ vop3_post_acm_config(state, vop2);
	2155	+ vop3_post_csc_config(state, vop2);
1650	2156	}
1651	2157
1652	2158	/*
..	..	@@ -1731,112 +2237,55 @@
1731	2237	vop2->regsbak[i] = base[i];
1732	2238	}
1733	2239
1734		-static void vop2_global_initial(struct vop2 vop2, struct display_state state)
	2240	+static void vop3_overlay_init(struct vop2 vop2, struct display_state state)
	2241	+{
	2242	+ struct vop2_win_data *win_data;
	2243	+ int layer_phy_id = 0;
	2244	+ int i, j;
	2245	+ u32 ovl_port_offset = 0;
	2246	+ u32 layer_nr = 0;
	2247	+ u8 shift = 0;
	2248	+
	2249	+ /* layer sel win id */
	2250	+ for (i = 0; i < vop2->data->nr_vps; i++) {
	2251	+ shift = 0;
	2252	+ ovl_port_offset = 0x100 * i;
	2253	+ layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
	2254	+ for (j = 0; j < layer_nr; j++) {
	2255	+ layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
	2256	+ win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id);
	2257	+ vop2_mask_write(vop2, RK3528_OVL_PORT0_LAYER_SEL + ovl_port_offset, LAYER_SEL_MASK,
	2258	+ shift, win_data->layer_sel_win_id[i], false);
	2259	+ shift += 4;
	2260	+ }
	2261	+ }
	2262	+
	2263	+ /* win sel port */
	2264	+ for (i = 0; i < vop2->data->nr_vps; i++) {
	2265	+ layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
	2266	+ for (j = 0; j < layer_nr; j++) {
	2267	+ if (!vop2->vp_plane_mask[i].attached_layers[j])
	2268	+ continue;
	2269	+ layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
	2270	+ win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id);
	2271	+ shift = win_data->win_sel_port_offset * 2;
	2272	+ vop2_mask_write(vop2, RK3528_OVL_SYS_PORT_SEL_IMD, LAYER_SEL_PORT_MASK,
	2273	+ shift, i, false);
	2274	+ }
	2275	+ }
	2276	+}
	2277	+
	2278	+static void vop2_overlay_init(struct vop2 vop2, struct display_state state)
1735	2279	{
1736	2280	struct crtc_state *cstate = &state->crtc_state;
1737		- int i, j, port_mux = 0, total_used_layer = 0;
1738		- u8 shift = 0;
1739		- int layer_phy_id = 0;
1740		- u32 layer_nr = 0;
1741	2281	struct vop2_win_data *win_data;
1742		- struct vop2_vp_plane_mask *plane_mask;
	2282	+ int layer_phy_id = 0;
	2283	+ int total_used_layer = 0;
	2284	+ int port_mux = 0;
	2285	+ int i, j;
	2286	+ u32 layer_nr = 0;
	2287	+ u8 shift = 0;
1743	2288
1744		- if (vop2->global_init)
1745		- return;
1746		-
1747		- /* OTP must enable at the first time, otherwise mirror layer register is error */
1748		- if (soc_is_rk3566())
1749		- vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK,
1750		- OTP_WIN_EN_SHIFT, 1, false);
1751		-
1752		- if (cstate->crtc->assign_plane) {/* dts assign plane */
1753		- u32 plane_mask;
1754		- int primary_plane_id;
1755		-
1756		- for (i = 0; i < vop2->data->nr_vps; i++) {
1757		- plane_mask = cstate->crtc->vps[i].plane_mask;
1758		- vop2->vp_plane_mask[i].plane_mask = plane_mask;
1759		- layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */
1760		- vop2->vp_plane_mask[i].attached_layers_nr = layer_nr;
1761		- primary_plane_id = cstate->crtc->vps[i].primary_plane_id;
1762		- if (primary_plane_id < 0)
1763		- primary_plane_id = vop2_get_primary_plane(vop2, plane_mask);
1764		- vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id;
1765		- vop2->vp_plane_mask[i].plane_mask = plane_mask;
1766		-
1767		- /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/
1768		- for (j = 0; j < layer_nr; j++) {
1769		- vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1;
1770		- plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]);
1771		- }
1772		- }
1773		- } else {/* need soft assign plane mask */
1774		- /* find the first unplug devices and set it as main display */
1775		- int main_vp_index = -1;
1776		- int active_vp_num = 0;
1777		-
1778		- for (i = 0; i < vop2->data->nr_vps; i++) {
1779		- if (cstate->crtc->vps[i].enable)
1780		- active_vp_num++;
1781		- }
1782		- printf("VOP have %d active VP\n", active_vp_num);
1783		-
1784		- if (soc_is_rk3566() && active_vp_num > 2)
1785		- printf("ERROR: rk3566 only support 2 display output!!\n");
1786		- plane_mask = vop2->data->plane_mask;
1787		- plane_mask += (active_vp_num - 1) * VOP2_VP_MAX;
1788		-
1789		- for (i = 0; i < vop2->data->nr_vps; i++) {
1790		- if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) {
1791		- vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/
1792		- main_vp_index = i;
1793		- break;
1794		- }
1795		- }
1796		-
1797		- /* if no find unplug devices, use vp0 as main display */
1798		- if (main_vp_index < 0) {
1799		- main_vp_index = 0;
1800		- vop2->vp_plane_mask[0] = plane_mask[0];
1801		- }
1802		-
1803		- j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */
1804		-
1805		- /* init other display except main display */
1806		- for (i = 0; i < vop2->data->nr_vps; i++) {
1807		- if (i == main_vp_index \|\| !cstate->crtc->vps[i].enable) /* main display or no connect devices */
1808		- continue;
1809		- vop2->vp_plane_mask[i] = plane_mask[j++];
1810		- }
1811		-
1812		- /* store plane mask for vop2_fixup_dts */
1813		- for (i = 0; i < vop2->data->nr_vps; i++) {
1814		- layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
1815		- for (j = 0; j < layer_nr; j++) {
1816		- layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
1817		- vop2->vp_plane_mask[i].plane_mask \|= BIT(layer_phy_id);
1818		- }
1819		- }
1820		- }
1821		-
1822		- if (vop2->version == VOP_VERSION_RK3588)
1823		- rk3588_vop2_regsbak(vop2);
1824		- else
1825		- memcpy(vop2->regsbak, vop2->regs, vop2->reg_len);
1826		-
1827		- vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK,
1828		- OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false);
1829		- vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
1830		- IF_CTRL_REG_DONE_IMD_SHIFT, 1, false);
1831		-
1832		- for (i = 0; i < vop2->data->nr_vps; i++) {
1833		- printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr);
1834		- for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++)
1835		- printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]);
1836		- printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id);
1837		- }
1838		-
1839		- shift = 0;
1840	2289	/* layer sel win id */
1841	2290	for (i = 0; i < vop2->data->nr_vps; i++) {
1842	2291	layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
..	..	@@ -1844,7 +2293,7 @@
1844	2293	layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
1845	2294	win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id);
1846	2295	vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK,
1847		- shift, win_data->layer_sel_win_id, false);
	2296	+ shift, win_data->layer_sel_win_id[i], false);
1848	2297	shift += 4;
1849	2298	}
1850	2299	}
..	..	@@ -1882,6 +2331,190 @@
1882	2331	vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK,
1883	2332	PORT_MUX_SHIFT + shift, port_mux, false);
1884	2333	}
	2334	+}
	2335	+
	2336	+static bool vop3_ignore_plane(struct vop2 vop2, struct vop2_win_data win)
	2337	+{
	2338	+ if (!is_vop3(vop2))
	2339	+ return false;
	2340	+
	2341	+ if (vop2->esmart_lb_mode == VOP3_ESMART_8K_MODE &&
	2342	+ win->phys_id != ROCKCHIP_VOP2_ESMART0)
	2343	+ return true;
	2344	+ else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_4K_MODE &&
	2345	+ (win->phys_id == ROCKCHIP_VOP2_ESMART1 \|\| win->phys_id == ROCKCHIP_VOP2_ESMART3))
	2346	+ return true;
	2347	+ else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_2K_2K_MODE &&
	2348	+ win->phys_id == ROCKCHIP_VOP2_ESMART1)
	2349	+ return true;
	2350	+ else
	2351	+ return false;
	2352	+}
	2353	+
	2354	+static void vop3_init_esmart_scale_engine(struct vop2 *vop2)
	2355	+{
	2356	+ struct vop2_win_data *win_data;
	2357	+ int i;
	2358	+ u8 scale_engine_num = 0;
	2359	+
	2360	+ /* store plane mask for vop2_fixup_dts */
	2361	+ for (i = 0; i < vop2->data->nr_layers; i++) {
	2362	+ win_data = &vop2->data->win_data[i];
	2363	+ if (win_data->type == CLUSTER_LAYER \|\| vop3_ignore_plane(vop2, win_data))
	2364	+ continue;
	2365	+
	2366	+ win_data->scale_engine_num = scale_engine_num++;
	2367	+ }
	2368	+}
	2369	+
	2370	+static void vop2_global_initial(struct vop2 vop2, struct display_state state)
	2371	+{
	2372	+ struct crtc_state *cstate = &state->crtc_state;
	2373	+ struct vop2_vp_plane_mask *plane_mask;
	2374	+ int layer_phy_id = 0;
	2375	+ int i, j;
	2376	+ int ret;
	2377	+ u32 layer_nr = 0;
	2378	+
	2379	+ if (vop2->global_init)
	2380	+ return;
	2381	+
	2382	+ /* OTP must enable at the first time, otherwise mirror layer register is error */
	2383	+ if (soc_is_rk3566())
	2384	+ vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK,
	2385	+ OTP_WIN_EN_SHIFT, 1, false);
	2386	+
	2387	+ if (cstate->crtc->assign_plane) {/* dts assign plane */
	2388	+ u32 plane_mask;
	2389	+ int primary_plane_id;
	2390	+
	2391	+ for (i = 0; i < vop2->data->nr_vps; i++) {
	2392	+ plane_mask = cstate->crtc->vps[i].plane_mask;
	2393	+ vop2->vp_plane_mask[i].plane_mask = plane_mask;
	2394	+ layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */
	2395	+ vop2->vp_plane_mask[i].attached_layers_nr = layer_nr;
	2396	+ primary_plane_id = cstate->crtc->vps[i].primary_plane_id;
	2397	+ if (primary_plane_id >= ROCKCHIP_VOP2_LAYER_MAX)
	2398	+ primary_plane_id = vop2_get_primary_plane(vop2, plane_mask);
	2399	+ vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id;
	2400	+ vop2->vp_plane_mask[i].plane_mask = plane_mask;
	2401	+
	2402	+ /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/
	2403	+ for (j = 0; j < layer_nr; j++) {
	2404	+ vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1;
	2405	+ plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]);
	2406	+ }
	2407	+ }
	2408	+ } else {/* need soft assign plane mask */
	2409	+ /* find the first unplug devices and set it as main display */
	2410	+ int main_vp_index = -1;
	2411	+ int active_vp_num = 0;
	2412	+
	2413	+ for (i = 0; i < vop2->data->nr_vps; i++) {
	2414	+ if (cstate->crtc->vps[i].enable)
	2415	+ active_vp_num++;
	2416	+ }
	2417	+ printf("VOP have %d active VP\n", active_vp_num);
	2418	+
	2419	+ if (soc_is_rk3566() && active_vp_num > 2)
	2420	+ printf("ERROR: rk3566 only support 2 display output!!\n");
	2421	+ plane_mask = vop2->data->plane_mask;
	2422	+ plane_mask += (active_vp_num - 1) * VOP2_VP_MAX;
	2423	+ /*
	2424	+ * For rk3528, one display policy for hdmi store in plane_mask[0], and the other
	2425	+ * for cvbs store in plane_mask[2].
	2426	+ */
	2427	+ if (vop2->version == VOP_VERSION_RK3528 && active_vp_num == 1 &&
	2428	+ cstate->crtc->vps[1].output_type == DRM_MODE_CONNECTOR_TV)
	2429	+ plane_mask += 2 * VOP2_VP_MAX;
	2430	+
	2431	+ if (vop2->version == VOP_VERSION_RK3528) {
	2432	+ /*
	2433	+ * For rk3528, the plane mask of vp is limited, only esmart2 can be selected
	2434	+ * by both vp0 and vp1.
	2435	+ */
	2436	+ j = 0;
	2437	+ } else {
	2438	+ for (i = 0; i < vop2->data->nr_vps; i++) {
	2439	+ if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) {
	2440	+ vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/
	2441	+ main_vp_index = i;
	2442	+ break;
	2443	+ }
	2444	+ }
	2445	+
	2446	+ /* if no find unplug devices, use vp0 as main display */
	2447	+ if (main_vp_index < 0) {
	2448	+ main_vp_index = 0;
	2449	+ vop2->vp_plane_mask[0] = plane_mask[0];
	2450	+ }
	2451	+
	2452	+ j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */
	2453	+ }
	2454	+
	2455	+ /* init other display except main display */
	2456	+ for (i = 0; i < vop2->data->nr_vps; i++) {
	2457	+ if (i == main_vp_index \|\| !cstate->crtc->vps[i].enable) /* main display or no connect devices */
	2458	+ continue;
	2459	+ vop2->vp_plane_mask[i] = plane_mask[j++];
	2460	+ }
	2461	+
	2462	+ /* store plane mask for vop2_fixup_dts */
	2463	+ for (i = 0; i < vop2->data->nr_vps; i++) {
	2464	+ layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
	2465	+ for (j = 0; j < layer_nr; j++) {
	2466	+ layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
	2467	+ vop2->vp_plane_mask[i].plane_mask \|= BIT(layer_phy_id);
	2468	+ }
	2469	+ }
	2470	+ }
	2471	+
	2472	+ if (vop2->version == VOP_VERSION_RK3588)
	2473	+ rk3588_vop2_regsbak(vop2);
	2474	+ else
	2475	+ memcpy(vop2->regsbak, vop2->regs, vop2->reg_len);
	2476	+
	2477	+ vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK,
	2478	+ OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false);
	2479	+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
	2480	+ IF_CTRL_REG_DONE_IMD_SHIFT, 1, false);
	2481	+
	2482	+ for (i = 0; i < vop2->data->nr_vps; i++) {
	2483	+ printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr);
	2484	+ for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++)
	2485	+ printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]);
	2486	+ printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id);
	2487	+ }
	2488	+
	2489	+ if (is_vop3(vop2))
	2490	+ vop3_overlay_init(vop2, state);
	2491	+ else
	2492	+ vop2_overlay_init(vop2, state);
	2493	+
	2494	+ if (is_vop3(vop2)) {
	2495	+ /*
	2496	+ * you can rewrite at dts vop node:
	2497	+ *
	2498	+ * VOP3_ESMART_8K_MODE = 0,
	2499	+ * VOP3_ESMART_4K_4K_MODE = 1,
	2500	+ * VOP3_ESMART_4K_2K_2K_MODE = 2,
	2501	+ * VOP3_ESMART_2K_2K_2K_2K_MODE = 3,
	2502	+ *
	2503	+ * &vop {
	2504	+ * esmart_lb_mode = /bits/ 8 <2>;
	2505	+ * };
	2506	+ */
	2507	+ ret = ofnode_read_u32(cstate->node, "esmart_lb_mode", &vop2->esmart_lb_mode);
	2508	+ if (ret < 0)
	2509	+ vop2->esmart_lb_mode = vop2->data->esmart_lb_mode;
	2510	+ vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, ESMART_LB_MODE_SEL_MASK,
	2511	+ ESMART_LB_MODE_SEL_SHIFT, vop2->esmart_lb_mode, false);
	2512	+
	2513	+ vop3_init_esmart_scale_engine(vop2);
	2514	+
	2515	+ vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, EN_MASK,
	2516	+ DSP_VS_T_SEL_SHIFT, 0, false);
	2517	+ }
1885	2518
1886	2519	if (vop2->version == VOP_VERSION_RK3568)
1887	2520	vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0);
..	..	@@ -1891,14 +2524,6 @@
1891	2524
1892	2525	static int vop2_initial(struct vop2 vop2, struct display_state state)
1893	2526	{
1894		- struct crtc_state *cstate = &state->crtc_state;
1895		- int ret;
1896		-
1897		- /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
1898		- ret = clk_set_defaults(cstate->dev);
1899		- if (ret)
1900		- debug("%s clk_set_defaults failed %d\n", __func__, ret);
1901		-
1902	2527	rockchip_vop2_gamma_lut_init(vop2, state);
1903	2528	rockchip_vop2_cubic_lut_init(vop2, state);
1904	2529
..	..	@@ -1918,12 +2543,17 @@
1918	2543	rockchip_vop2 = calloc(1, sizeof(struct vop2));
1919	2544	if (!rockchip_vop2)
1920	2545	return -ENOMEM;
1921		- rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev);
	2546	+ memset(rockchip_vop2, 0, sizeof(struct vop2));
1922	2547	rockchip_vop2->regsbak = malloc(RK3568_MAX_REG);
1923	2548	rockchip_vop2->reg_len = RK3568_MAX_REG;
	2549	+#ifdef CONFIG_SPL_BUILD
	2550	+ rockchip_vop2->regs = (void *)RK3528_VOP_BASE;
	2551	+#else
	2552	+ rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev);
1924	2553	rockchip_vop2->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1925	2554	if (rockchip_vop2->grf <= 0)
1926	2555	printf("%s: Get syscon grf failed (ret=%p)\n", __func__, rockchip_vop2->grf);
	2556	+#endif
1927	2557	rockchip_vop2->version = vop2_data->version;
1928	2558	rockchip_vop2->data = vop2_data;
1929	2559	if (rockchip_vop2->version == VOP_VERSION_RK3588) {
..	..	@@ -2021,11 +2651,12 @@
2021	2651	}
2022	2652
2023	2653	if (v_pixclk > VOP2_MAX_DCLK_RATE)
2024		- dclk_rate = vop2_calc_dclk(dclk_core_rate, vop2->data->vp_data->max_dclk);
	2654	+ dclk_rate = vop2_calc_dclk(dclk_core_rate,
	2655	+ vop2->data->vp_data[cstate->crtc_id].max_dclk);
2025	2656
2026	2657	if (!dclk_rate) {
2027	2658	printf("DP if_pixclk_rate out of range(max_dclk: %d KHZ, dclk_core: %lld KHZ)\n",
2028		- vop2->data->vp_data->max_dclk, if_pixclk_rate);
	2659	+ vop2->data->vp_data[cstate->crtc_id].max_dclk, if_pixclk_rate);
2029	2660	return -EINVAL;
2030	2661	}
2031	2662	*if_pixclk_div = dclk_rate / if_pixclk_rate;
..	..	@@ -2045,10 +2676,11 @@
2045	2676	dclk_out_rate = v_pixclk >> 2;
2046	2677	dclk_out_rate = dclk_out_rate / K;
2047	2678
2048		- dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk);
	2679	+ dclk_rate = vop2_calc_dclk(dclk_out_rate,
	2680	+ vop2->data->vp_data[cstate->crtc_id].max_dclk);
2049	2681	if (!dclk_rate) {
2050	2682	printf("DP dclk_core out of range(max_dclk: %d KHZ, dclk_core: %ld KHZ)\n",
2051		- vop2->data->vp_data->max_dclk, dclk_core_rate);
	2683	+ vop2->data->vp_data[cstate->crtc_id].max_dclk, dclk_core_rate);
2052	2684	return -EINVAL;
2053	2685	}
2054	2686	*dclk_out_div = dclk_rate / dclk_out_rate;
..	..	@@ -2064,21 +2696,22 @@
2064	2696	/* dclk_core = dclk_out * K = if_pixclk * K = v_pixclk / 4 */
2065	2697	dclk_out_rate = dclk_core_rate / K;
2066	2698	/* dclk_rate = N * dclk_core_rate N = (1,2,4 ), we get a little factor here */
2067		- dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk);
	2699	+ dclk_rate = vop2_calc_dclk(dclk_out_rate,
	2700	+ vop2->data->vp_data[cstate->crtc_id].max_dclk);
2068	2701	if (!dclk_rate) {
2069	2702	printf("MIPI dclk out of range(max_dclk: %d KHZ, dclk_rate: %ld KHZ)\n",
2070		- vop2->data->vp_data->max_dclk, dclk_rate);
	2703	+ vop2->data->vp_data[cstate->crtc_id].max_dclk, dclk_rate);
2071	2704	return -EINVAL;
2072	2705	}
2073	2706
2074	2707	if (cstate->dsc_enable)
2075		- dclk_rate = dclk_rate >> 1;
	2708	+ dclk_rate /= cstate->dsc_slice_num;
2076	2709
2077	2710	*dclk_out_div = dclk_rate / dclk_out_rate;
2078	2711	*dclk_core_div = dclk_rate / dclk_core_rate;
2079	2712	if_pixclk_div = 1; /mipi pixclk == dclk_out*/
2080	2713	if (cstate->dsc_enable)
2081		- *if_pixclk_div = dclk_out_rate / if_pixclk_rate;
	2714	+ if_pixclk_div = dclk_out_rate 1000LL / if_pixclk_rate;
2082	2715
2083	2716	} else if (output_type == DRM_MODE_CONNECTOR_DPI) {
2084	2717	dclk_rate = v_pixclk;
..	..	@@ -2098,7 +2731,7 @@
2098	2731	struct connector_state *conn_state = &state->conn_state;
2099	2732	struct drm_display_mode *mode = &conn_state->mode;
2100	2733	struct crtc_state *cstate = &state->crtc_state;
2101		- u64 v_pixclk = mode->clock; /* video timing pixclk */
	2734	+ u64 v_pixclk = mode->crtc_clock * 1000LL; /* video timing pixclk */
2102	2735	u8 k = 1;
2103	2736
2104	2737	if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
..	..	@@ -2201,8 +2834,7 @@
2201	2834
2202	2835	if (conn_state->hold_mode) {
2203	2836	vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
2204		- EN_MASK, EDPI_TE_EN, 1, false);
2205		-
	2837	+ EN_MASK, EDPI_TE_EN, !cstate->soft_te, false);
2206	2838	vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
2207	2839	EN_MASK, EDPI_WMS_HOLD_EN, 1, false);
2208	2840	}
..	..	@@ -2227,14 +2859,8 @@
2227	2859	if_pixclk_div, false);
2228	2860
2229	2861	if (conn_state->hold_mode) {
2230		- /* UNDO: RK3588 VP1->DSC1->DSI1 only can support soft TE mode */
2231		- if (vop2->version == VOP_VERSION_RK3588 && val == 3)
2232		- vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
2233		- EN_MASK, EDPI_TE_EN, 0, false);
2234		- else
2235		- vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
2236		- EN_MASK, EDPI_TE_EN, 1, false);
2237		-
	2862	+ vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
	2863	+ EN_MASK, EDPI_TE_EN, !cstate->soft_te, false);
2238	2864	vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
2239	2865	EN_MASK, EDPI_WMS_HOLD_EN, 1, false);
2240	2866	}
..	..	@@ -2371,7 +2997,7 @@
2371	2997	bool dclk_inv;
2372	2998	u32 val;
2373	2999
2374		- dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1;
	3000	+ dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
2375	3001	val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
2376	3002	val \|= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
2377	3003
..	..	@@ -2380,6 +3006,8 @@
2380	3006	1, false);
2381	3007	vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
2382	3008	RGB_MUX_SHIFT, cstate->crtc_id, false);
	3009	+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK,
	3010	+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
2383	3011	vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK,
2384	3012	GRF_RGB_DCLK_INV_SHIFT, dclk_inv);
2385	3013	}
..	..	@@ -2409,8 +3037,10 @@
2409	3037	1, false);
2410	3038	vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
2411	3039	LVDS0_MUX_SHIFT, cstate->crtc_id, false);
	3040	+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK,
	3041	+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
2412	3042	vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
2413		- IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false);
	3043	+ IF_CTRL_RGB_LVDS_DCLK_POL_SHIFT, dclk_inv, false);
2414	3044	}
2415	3045
2416	3046	if (conn_state->output_if & VOP_OUTPUT_IF_LVDS1) {
..	..	@@ -2418,8 +3048,10 @@
2418	3048	1, false);
2419	3049	vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
2420	3050	LVDS1_MUX_SHIFT, cstate->crtc_id, false);
	3051	+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK,
	3052	+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
2421	3053	vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
2422		- IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false);
	3054	+ IF_CTRL_RGB_LVDS_DCLK_POL_SHIFT, dclk_inv, false);
2423	3055	}
2424	3056
2425	3057	if (conn_state->output_flags &
..	..	@@ -2472,6 +3104,8 @@
2472	3104	EDP0_MUX_SHIFT, cstate->crtc_id, false);
2473	3105	vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
2474	3106	IF_CRTL_EDP_DCLK_POL_SHIT, dclk_inv, false);
	3107	+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_EDP_PIN_POL_MASK,
	3108	+ IF_CTRL_EDP_PIN_POL_SHIFT, val, false);
2475	3109	}
2476	3110
2477	3111	if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) {
..	..	@@ -2489,6 +3123,88 @@
2489	3123	return mode->clock;
2490	3124	}
2491	3125
	3126	+static unsigned long rk3528_vop2_if_cfg(struct display_state *state)
	3127	+{
	3128	+ struct crtc_state *cstate = &state->crtc_state;
	3129	+ struct connector_state *conn_state = &state->conn_state;
	3130	+ struct drm_display_mode *mode = &conn_state->mode;
	3131	+ struct vop2 *vop2 = cstate->private;
	3132	+ u32 val;
	3133	+
	3134	+ val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
	3135	+ val \|= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
	3136	+
	3137	+ if (conn_state->output_if & VOP_OUTPUT_IF_BT656) {
	3138	+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT,
	3139	+ 1, false);
	3140	+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
	3141	+ RGB_MUX_SHIFT, cstate->crtc_id, false);
	3142	+ }
	3143	+
	3144	+ if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) {
	3145	+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT,
	3146	+ 1, false);
	3147	+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
	3148	+ HDMI0_MUX_SHIFT, cstate->crtc_id, false);
	3149	+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
	3150	+ IF_CRTL_HDMI_DCLK_POL_SHIT, 1, false);
	3151	+ vop2_mask_write(vop2, RK3568_DSP_IF_POL,
	3152	+ IF_CRTL_HDMI_PIN_POL_MASK,
	3153	+ IF_CRTL_HDMI_PIN_POL_SHIT, val, false);
	3154	+ }
	3155	+
	3156	+ return mode->crtc_clock;
	3157	+}
	3158	+
	3159	+static unsigned long rk3562_vop2_if_cfg(struct display_state *state)
	3160	+{
	3161	+ struct crtc_state *cstate = &state->crtc_state;
	3162	+ struct connector_state *conn_state = &state->conn_state;
	3163	+ struct drm_display_mode *mode = &conn_state->mode;
	3164	+ struct vop2 *vop2 = cstate->private;
	3165	+ bool dclk_inv;
	3166	+ u32 val;
	3167	+
	3168	+ dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
	3169	+ val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
	3170	+ val \|= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
	3171	+
	3172	+ if (conn_state->output_if & VOP_OUTPUT_IF_RGB) {
	3173	+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT,
	3174	+ 1, false);
	3175	+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
	3176	+ RGB_MUX_SHIFT, cstate->crtc_id, false);
	3177	+ vop2_grf_writel(vop2, vop2->grf, RK3562_GRF_IOC_VO_IO_CON, EN_MASK,
	3178	+ GRF_RGB_DCLK_INV_SHIFT, dclk_inv);
	3179	+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK,
	3180	+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
	3181	+ }
	3182	+
	3183	+ if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) {
	3184	+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT,
	3185	+ 1, false);
	3186	+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
	3187	+ LVDS0_MUX_SHIFT, cstate->crtc_id, false);
	3188	+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
	3189	+ IF_CTRL_RGB_LVDS_DCLK_POL_SHIFT, dclk_inv, false);
	3190	+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK,
	3191	+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
	3192	+ }
	3193	+
	3194	+ if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) {
	3195	+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT,
	3196	+ 1, false);
	3197	+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
	3198	+ MIPI0_MUX_SHIFT, cstate->crtc_id, false);
	3199	+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
	3200	+ RK3562_MIPI_DCLK_POL_SHIFT, dclk_inv, false);
	3201	+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK,
	3202	+ RK3562_MIPI_PIN_POL_SHIFT, val, false);
	3203	+ }
	3204	+
	3205	+ return mode->crtc_clock;
	3206	+}
	3207	+
2492	3208	static void vop2_post_color_swap(struct display_state *state)
2493	3209	{
2494	3210	struct crtc_state *cstate = &state->crtc_state;
..	..	@@ -2498,7 +3214,8 @@
2498	3214	u32 output_type = conn_state->type;
2499	3215	u32 data_swap = 0;
2500	3216
2501		- if (is_uv_swap(conn_state->bus_format, conn_state->output_mode))
	3217	+ if (is_uv_swap(conn_state->bus_format, conn_state->output_mode) \|\|
	3218	+ is_rb_swap(conn_state->bus_format, conn_state->output_mode))
2502	3219	data_swap = DSP_RB_SWAP;
2503	3220
2504	3221	if (vop2->version == VOP_VERSION_RK3588 &&
..	..	@@ -2603,10 +3320,10 @@
2603	3320	u16 vact_end = vact_st + vdisplay;
2604	3321	u32 ctrl_regs_offset = (dsc_id * 0x30);
2605	3322	u32 decoder_regs_offset = (dsc_id * 0x100);
2606		- u32 backup_regs_offset = 0;
2607	3323	int dsc_txp_clk_div = 0;
2608	3324	int dsc_pxl_clk_div = 0;
2609	3325	int dsc_cds_clk_div = 0;
	3326	+ int val = 0;
2610	3327
2611	3328	if (!vop2->data->nr_dscs) {
2612	3329	printf("Unsupported DSC\n");
..	..	@@ -2678,21 +3395,42 @@
2678	3395	* dly_num = delay_line_num * T(one-line) / T (dsc_cds)
2679	3396	* T (one-line) = 1/v_pixclk_mhz * htotal = htotal/v_pixclk_mhz
2680	3397	* T (dsc_cds) = 1 / dsc_cds_rate_mhz
	3398	+ *
	3399	+ * HDMI:
2681	3400	* delay_line_num: according the pps initial_xmit_delay to adjust vop dsc delay
2682	3401	* delay_line_num = 4 - BPP / 8
2683	3402	* = (64 - target_bpp / 8) / 16
2684		- *
2685	3403	* dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
	3404	+ *
	3405	+ * MIPI DSI[4320 and 9216 is buffer size for DSC]:
	3406	+ * DSC0:delay_line_num = 4320 * 8 / slince_num / chunk_size;
	3407	+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	3408	+ * DSC1:delay_line_num = 9216 * 2 / slince_num / chunk_size;
	3409	+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	3410	+ * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num
2686	3411	*/
2687	3412	do_div(dsc_cds_rate, 1000000); /* hz to Mhz */
2688	3413	dsc_cds_rate_mhz = dsc_cds_rate;
2689		- dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
	3414	+ dsc_hsync = hsync_len / 2;
	3415	+ if (dsc_interface_mode == VOP_DSC_IF_HDMI) {
	3416	+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
	3417	+ } else {
	3418	+ int dsc_buf_size = dsc_id == 0 ? 4320 * 8 : 9216 * 2;
	3419	+ int delay_line_num = dsc_buf_size / cstate->dsc_slice_num /
	3420	+ be16_to_cpu(cstate->pps.chunk_size);
	3421	+
	3422	+ delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	3423	+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num;
	3424	+
	3425	+ /* The dsc mipi video mode dsc_hsync minimum size is 8 pixels */
	3426	+ if (dsc_hsync < 8)
	3427	+ dsc_hsync = 8;
	3428	+ }
2690	3429	vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_MODE_MASK,
2691	3430	DSC_INIT_DLY_MODE_SHIFT, 0, false);
2692	3431	vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_NUM_MASK,
2693	3432	DSC_INIT_DLY_NUM_SHIFT, dly_num, false);
2694	3433
2695		- dsc_hsync = hsync_len / 2;
2696	3434	/*
2697	3435	* htotal / dclk_core = dsc_htotal /cds_clk
2698	3436	*
..	..	@@ -2724,34 +3462,15 @@
2724	3462	vop2_mask_write(vop2, RK3588_DSC_8K_RST + ctrl_regs_offset, RST_DEASSERT_MASK,
2725	3463	RST_DEASSERT_SHIFT, 1, false);
2726	3464	udelay(10);
2727		- /* read current dsc core register and backup to regsbak */
2728		- backup_regs_offset = RK3588_DSC_8K_CTRL0;
2729		- vop2->regsbak[backup_regs_offset >> 2] = vop2_readl(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset);
2730	3465
2731		- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2732		- DSC_EN_SHIFT, 1, false);
	3466	+ val \|= DSC_CTRL0_DEF_CON \| (ilog2(cstate->dsc_slice_num) << DSC_NSLC_SHIFT) \|
	3467	+ ((dsc_sink_cap->version_minor == 2 ? 1 : 0) << DSC_IFEP_SHIFT);
	3468	+ vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val);
	3469	+
2733	3470	vop2_load_pps(state, vop2, dsc_id);
2734	3471
2735		- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2736		- DSC_RBIT_SHIFT, 1, false);
2737		- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2738		- DSC_RBYT_SHIFT, 0, false);
2739		- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2740		- DSC_FLAL_SHIFT, 1, false);
2741		- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2742		- DSC_MER_SHIFT, 1, false);
2743		- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2744		- DSC_EPB_SHIFT, 0, false);
2745		- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2746		- DSC_EPL_SHIFT, 1, false);
2747		- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2748		- DSC_NSLC_SHIFT, ilog2(cstate->dsc_slice_num), false);
2749		- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2750		- DSC_SBO_SHIFT, 1, false);
2751		- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2752		- DSC_IFEP_SHIFT, dsc_sink_cap->version_minor == 2 ? 1 : 0, false);
2753		- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2754		- DSC_PPS_UPD_SHIFT, 1, false);
	3472	+ val \|= (1 << DSC_PPS_UPD_SHIFT);
	3473	+ vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val);
2755	3474
2756	3475	printf("DSC%d: txp:%lld div:%d, pxl:%lld div:%d, dsc:%lld div:%d\n",
2757	3476	dsc_id,
..	..	@@ -2800,6 +3519,133 @@
2800	3519	return false;
2801	3520	}
2802	3521
	3522	+static void vop3_mcu_mode_setup(struct display_state *state)
	3523	+{
	3524	+ struct crtc_state *cstate = &state->crtc_state;
	3525	+ struct vop2 *vop2 = cstate->private;
	3526	+ u32 vp_offset = (cstate->crtc_id * 0x100);
	3527	+
	3528	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
	3529	+ MCU_TYPE_SHIFT, 1, false);
	3530	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
	3531	+ MCU_HOLD_MODE_SHIFT, 1, false);
	3532	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK,
	3533	+ MCU_PIX_TOTAL_SHIFT, cstate->mcu_timing.mcu_pix_total, false);
	3534	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK,
	3535	+ MCU_CS_PST_SHIFT, cstate->mcu_timing.mcu_cs_pst, false);
	3536	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK,
	3537	+ MCU_CS_PEND_SHIFT, cstate->mcu_timing.mcu_cs_pend, false);
	3538	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK,
	3539	+ MCU_RW_PST_SHIFT, cstate->mcu_timing.mcu_rw_pst, false);
	3540	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK,
	3541	+ MCU_RW_PEND_SHIFT, cstate->mcu_timing.mcu_rw_pend, false);
	3542	+}
	3543	+
	3544	+static void vop3_mcu_bypass_mode_setup(struct display_state *state)
	3545	+{
	3546	+ struct crtc_state *cstate = &state->crtc_state;
	3547	+ struct vop2 *vop2 = cstate->private;
	3548	+ u32 vp_offset = (cstate->crtc_id * 0x100);
	3549	+
	3550	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
	3551	+ MCU_TYPE_SHIFT, 1, false);
	3552	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
	3553	+ MCU_HOLD_MODE_SHIFT, 1, false);
	3554	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK,
	3555	+ MCU_PIX_TOTAL_SHIFT, 53, false);
	3556	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK,
	3557	+ MCU_CS_PST_SHIFT, 6, false);
	3558	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK,
	3559	+ MCU_CS_PEND_SHIFT, 48, false);
	3560	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK,
	3561	+ MCU_RW_PST_SHIFT, 12, false);
	3562	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK,
	3563	+ MCU_RW_PEND_SHIFT, 30, false);
	3564	+}
	3565	+
	3566	+static int rockchip_vop2_send_mcu_cmd(struct display_state *state, u32 type, u32 value)
	3567	+{
	3568	+ struct crtc_state *cstate = &state->crtc_state;
	3569	+ struct connector_state *conn_state = &state->conn_state;
	3570	+ struct drm_display_mode *mode = &conn_state->mode;
	3571	+ struct vop2 *vop2 = cstate->private;
	3572	+ u32 vp_offset = (cstate->crtc_id * 0x100);
	3573	+ u32 cfg_done = CFG_DONE_EN \| BIT(cstate->crtc_id) \| (BIT(cstate->crtc_id) << 16);
	3574	+
	3575	+ /*
	3576	+ * 1.disable port dclk auto gating.
	3577	+ * 2.set mcu bypass mode timing to adapt to the mode of sending cmds.
	3578	+ * 3.make setting of output mode take effect.
	3579	+ * 4.set dclk rate to 150M, in order to sync with hclk in sending cmds.
	3580	+ */
	3581	+ if (type == MCU_SETBYPASS && value) {
	3582	+ vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,
	3583	+ AUTO_GATING_EN_SHIFT, 0, false);
	3584	+ vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,
	3585	+ PORT_DCLK_AUTO_GATING_EN_SHIFT, 0, false);
	3586	+ vop3_mcu_bypass_mode_setup(state);
	3587	+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
	3588	+ STANDBY_EN_SHIFT, 0, false);
	3589	+ vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);
	3590	+ vop2_clk_set_rate(&cstate->dclk, 150000000);
	3591	+ }
	3592	+
	3593	+ switch (type) {
	3594	+ case MCU_WRCMD:
	3595	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
	3596	+ MCU_RS_SHIFT, 0, false);
	3597	+ vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset,
	3598	+ MCU_WRITE_DATA_BYPASS_MASK, MCU_WRITE_DATA_BYPASS_SHIFT,
	3599	+ value, false);
	3600	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
	3601	+ MCU_RS_SHIFT, 1, false);
	3602	+ break;
	3603	+ case MCU_WRDATA:
	3604	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
	3605	+ MCU_RS_SHIFT, 1, false);
	3606	+ vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset,
	3607	+ MCU_WRITE_DATA_BYPASS_MASK, MCU_WRITE_DATA_BYPASS_SHIFT,
	3608	+ value, false);
	3609	+ break;
	3610	+ case MCU_SETBYPASS:
	3611	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
	3612	+ MCU_BYPASS_SHIFT, value ? 1 : 0, false);
	3613	+ break;
	3614	+ default:
	3615	+ break;
	3616	+ }
	3617	+
	3618	+ /*
	3619	+ * 1.restore port dclk auto gating.
	3620	+ * 2.restore mcu data mode timing.
	3621	+ * 3.restore dclk rate to crtc_clock.
	3622	+ */
	3623	+ if (type == MCU_SETBYPASS && !value) {
	3624	+ vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,
	3625	+ AUTO_GATING_EN_SHIFT, 1, false);
	3626	+ vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,
	3627	+ PORT_DCLK_AUTO_GATING_EN_SHIFT, 1, false);
	3628	+ vop3_mcu_mode_setup(state);
	3629	+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
	3630	+ STANDBY_EN_SHIFT, 1, false);
	3631	+ vop2_clk_set_rate(&cstate->dclk, mode->crtc_clock * 1000);
	3632	+ }
	3633	+
	3634	+ return 0;
	3635	+}
	3636	+
	3637	+static int vop2_get_vrefresh(struct display_state *state)
	3638	+{
	3639	+ struct crtc_state *cstate = &state->crtc_state;
	3640	+ struct connector_state *conn_state = &state->conn_state;
	3641	+ struct drm_display_mode *mode = &conn_state->mode;
	3642	+
	3643	+ if (cstate->mcu_timing.mcu_pix_total)
	3644	+ return mode->vrefresh / cstate->mcu_timing.mcu_pix_total;
	3645	+ else
	3646	+ return mode->vrefresh;
	3647	+}
	3648	+
2803	3649	static int rockchip_vop2_init(struct display_state *state)
2804	3650	{
2805	3651	struct crtc_state *cstate = &state->crtc_state;
..	..	@@ -2822,22 +3668,24 @@
2822	3668	u32 line_flag_offset = (cstate->crtc_id * 4);
2823	3669	u32 val, act_end;
2824	3670	u8 dither_down_en = 0;
	3671	+ u8 dither_down_mode = 0;
2825	3672	u8 pre_dither_down_en = 0;
2826	3673	u8 dclk_div_factor = 0;
2827	3674	char output_type_name[30] = {0};
	3675	+#ifndef CONFIG_SPL_BUILD
2828	3676	char dclk_name[9];
2829		- struct clk dclk;
	3677	+#endif
2830	3678	struct clk hdmi0_phy_pll;
2831	3679	struct clk hdmi1_phy_pll;
2832	3680	struct clk hdmi_phy_pll;
2833	3681	struct udevice *disp_dev;
2834		- unsigned long dclk_rate;
	3682	+ unsigned long dclk_rate = 0;
2835	3683	int ret;
2836	3684
2837	3685	printf("VOP update mode to: %dx%d%s%d, type:%s for VP%d\n",
2838	3686	mode->crtc_hdisplay, mode->vdisplay,
2839	3687	mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
2840		- mode->vrefresh,
	3688	+ vop2_get_vrefresh(state),
2841	3689	get_output_if_name(conn_state->output_if, output_type_name),
2842	3690	cstate->crtc_id);
2843	3691
..	..	@@ -2854,11 +3702,20 @@
2854	3702	PORT_MERGE_EN_SHIFT, 1, false);
2855	3703	}
2856	3704
	3705	+ vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK,
	3706	+ RK3588_VP0_LINE_FLAG_OR_EN_SHIFT + cstate->crtc_id, 1, false);
	3707	+ vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK,
	3708	+ RK3588_VP0_ALMOST_FULL_OR_EN_SHIFT + cstate->crtc_id, 1, false);
	3709	+
2857	3710	vop2_initial(vop2, state);
2858	3711	if (vop2->version == VOP_VERSION_RK3588)
2859	3712	dclk_rate = rk3588_vop2_if_cfg(state);
2860		- else
	3713	+ else if (vop2->version == VOP_VERSION_RK3568)
2861	3714	dclk_rate = rk3568_vop2_if_cfg(state);
	3715	+ else if (vop2->version == VOP_VERSION_RK3528)
	3716	+ dclk_rate = rk3528_vop2_if_cfg(state);
	3717	+ else if (vop2->version == VOP_VERSION_RK3562)
	3718	+ dclk_rate = rk3562_vop2_if_cfg(state);
2862	3719
2863	3720	if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
2864	3721	!(cstate->feature & VOP_FEATURE_OUTPUT_10BIT))
..	..	@@ -2872,12 +3729,16 @@
2872	3729	switch (conn_state->bus_format) {
2873	3730	case MEDIA_BUS_FMT_RGB565_1X16:
2874	3731	dither_down_en = 1;
	3732	+ dither_down_mode = RGB888_TO_RGB565;
	3733	+ pre_dither_down_en = 1;
2875	3734	break;
2876	3735	case MEDIA_BUS_FMT_RGB666_1X18:
2877	3736	case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
2878	3737	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
2879	3738	case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA:
2880	3739	dither_down_en = 1;
	3740	+ dither_down_mode = RGB888_TO_RGB666;
	3741	+ pre_dither_down_en = 1;
2881	3742	break;
2882	3743	case MEDIA_BUS_FMT_YUV8_1X24:
2883	3744	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
..	..	@@ -2886,23 +3747,28 @@
2886	3747	break;
2887	3748	case MEDIA_BUS_FMT_YUV10_1X30:
2888	3749	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
2889		- case MEDIA_BUS_FMT_RGB888_1X24:
2890		- case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
2891		- case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
2892		- default:
2893	3750	dither_down_en = 0;
2894	3751	pre_dither_down_en = 0;
2895	3752	break;
	3753	+ case MEDIA_BUS_FMT_YUYV10_1X20:
	3754	+ case MEDIA_BUS_FMT_RGB888_1X24:
	3755	+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
	3756	+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
	3757	+ case MEDIA_BUS_FMT_RGB101010_1X30:
	3758	+ default:
	3759	+ dither_down_en = 0;
	3760	+ pre_dither_down_en = 1;
	3761	+ break;
2896	3762	}
2897	3763
2898		- if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA)
2899		- pre_dither_down_en = 0;
2900		- else
2901		- pre_dither_down_en = 1;
2902	3764	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
2903	3765	DITHER_DOWN_EN_SHIFT, dither_down_en, false);
2904	3766	vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
	3767	+ DITHER_DOWN_MODE_SHIFT, dither_down_mode, false);
	3768	+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
2905	3769	PRE_DITHER_DOWN_EN_SHIFT, pre_dither_down_en, false);
	3770	+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
	3771	+ DITHER_DOWN_MODE_SHIFT, dither_down_mode, false);
2906	3772
2907	3773	yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0;
2908	3774	vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id,
..	..	@@ -2946,15 +3812,13 @@
2946	3812	vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset,
2947	3813	(vtotal << 16) \| vsync_len);
2948	3814
2949		- if (vop2->version == VOP_VERSION_RK3568) {
2950		- if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\|
2951		- conn_state->output_if & VOP_OUTPUT_IF_BT656)
2952		- vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
2953		- CORE_DCLK_DIV_EN_SHIFT, 1, false);
2954		- else
2955		- vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
2956		- CORE_DCLK_DIV_EN_SHIFT, 0, false);
2957		- }
	3815	+ if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\|
	3816	+ conn_state->output_if & VOP_OUTPUT_IF_BT656)
	3817	+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
	3818	+ CORE_DCLK_DIV_EN_SHIFT, 1, false);
	3819	+ else
	3820	+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
	3821	+ CORE_DCLK_DIV_EN_SHIFT, 0, false);
2958	3822
2959	3823	if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420)
2960	3824	vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
..	..	@@ -2987,22 +3851,26 @@
2987	3851
2988	3852	vop2_tv_config_update(state, vop2);
2989	3853	vop2_post_config(state, vop2);
	3854	+ if (cstate->feature & (VOP_FEATURE_POST_ACM \| VOP_FEATURE_POST_CSC))
	3855	+ vop3_post_config(state, vop2);
2990	3856
2991	3857	if (cstate->dsc_enable) {
2992	3858	if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
2993		- vop2_dsc_enable(state, vop2, 0, dclk_rate);
2994		- vop2_dsc_enable(state, vop2, 1, dclk_rate);
	3859	+ vop2_dsc_enable(state, vop2, 0, dclk_rate * 1000LL);
	3860	+ vop2_dsc_enable(state, vop2, 1, dclk_rate * 1000LL);
2995	3861	} else {
2996		- vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate);
	3862	+ vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate * 1000LL);
2997	3863	}
2998	3864	}
2999	3865
	3866	+#ifndef CONFIG_SPL_BUILD
3000	3867	snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id);
3001		- ret = clk_get_by_name(cstate->dev, dclk_name, &dclk);
	3868	+ ret = clk_get_by_name(cstate->dev, dclk_name, &cstate->dclk);
3002	3869	if (ret) {
3003	3870	printf("%s: Failed to get dclk ret=%d\n", __func__, ret);
3004	3871	return ret;
3005	3872	}
	3873	+#endif
3006	3874
3007	3875	ret = uclass_get_device_by_name(UCLASS_VIDEO, "display-subsystem", &disp_dev);
3008	3876	if (!ret) {
..	..	@@ -3018,11 +3886,27 @@
3018	3886	debug("%s: Faile to find display-subsystem node\n", __func__);
3019	3887	}
3020	3888
	3889	+ if (vop2->version == VOP_VERSION_RK3528) {
	3890	+ struct ofnode_phandle_args args;
	3891	+
	3892	+ ret = dev_read_phandle_with_args(cstate->dev, "assigned-clock-parents",
	3893	+ "#clock-cells", 0, 0, &args);
	3894	+ if (!ret) {
	3895	+ ret = uclass_find_device_by_ofnode(UCLASS_CLK, args.node, &hdmi0_phy_pll.dev);
	3896	+ if (ret) {
	3897	+ debug("warn: can't get clk device\n");
	3898	+ return ret;
	3899	+ }
	3900	+ } else {
	3901	+ debug("assigned-clock-parents's node not define\n");
	3902	+ }
	3903	+ }
	3904	+
3021	3905	if (mode->crtc_clock < VOP2_MAX_DCLK_RATE) {
3022	3906	if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0)
3023		- vop2_clk_set_parent(&dclk, &hdmi0_phy_pll);
	3907	+ vop2_clk_set_parent(&cstate->dclk, &hdmi0_phy_pll);
3024	3908	else if (conn_state->output_if & VOP_OUTPUT_IF_HDMI1)
3025		- vop2_clk_set_parent(&dclk, &hdmi1_phy_pll);
	3909	+ vop2_clk_set_parent(&cstate->dclk, &hdmi1_phy_pll);
3026	3910
3027	3911	/*
3028	3912	* uboot clk driver won't set dclk parent's rate when use
..	..	@@ -3035,16 +3919,28 @@
3035	3919	} else if ((conn_state->output_if & VOP_OUTPUT_IF_HDMI1) && hdmi1_phy_pll.dev) {
3036	3920	ret = vop2_clk_set_rate(&hdmi1_phy_pll, dclk_rate * 1000);
3037	3921	} else {
3038		- if (is_extend_pll(state, &hdmi_phy_pll.dev))
	3922	+ if (is_extend_pll(state, &hdmi_phy_pll.dev)) {
3039	3923	ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000);
3040		- else
3041		- ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000);
	3924	+ } else {
	3925	+#ifndef CONFIG_SPL_BUILD
	3926	+ ret = vop2_clk_set_rate(&cstate->dclk, dclk_rate * 1000);
	3927	+#else
	3928	+ if (vop2->version == VOP_VERSION_RK3528) {
	3929	+ void cru_base = (void )RK3528_CRU_BASE;
	3930	+
	3931	+ /* dclk src switch to hdmiphy pll */
	3932	+ writel((BIT(0) << 16) \| BIT(0), cru_base + 0x450);
	3933	+ rockchip_phy_set_pll(conn_state->connector->phy, dclk_rate * 1000);
	3934	+ ret = dclk_rate * 1000;
	3935	+ }
	3936	+#endif
	3937	+ }
3042	3938	}
3043	3939	} else {
3044	3940	if (is_extend_pll(state, &hdmi_phy_pll.dev))
3045	3941	ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000);
3046	3942	else
3047		- ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000);
	3943	+ ret = vop2_clk_set_rate(&cstate->dclk, dclk_rate * 1000);
3048	3944	}
3049	3945
3050	3946	if (IS_ERR_VALUE(ret)) {
..	..	@@ -3053,7 +3949,11 @@
3053	3949	return ret;
3054	3950	} else {
3055	3951	dclk_div_factor = mode->clock / dclk_rate;
3056		- mode->crtc_clock = ret * dclk_div_factor / 1000;
	3952	+ if (vop2->version == VOP_VERSION_RK3528 &&
	3953	+ conn_state->output_if & VOP_OUTPUT_IF_BT656)
	3954	+ mode->crtc_clock = ret / 4 / 1000;
	3955	+ else
	3956	+ mode->crtc_clock = ret * dclk_div_factor / 1000;
3057	3957	printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock);
3058	3958	}
3059	3959
..	..	@@ -3061,6 +3961,9 @@
3061	3961	RK3568_DSP_LINE_FLAG_NUM0_SHIFT, act_end, false);
3062	3962	vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK,
3063	3963	RK3568_DSP_LINE_FLAG_NUM1_SHIFT, act_end, false);
	3964	+
	3965	+ if (cstate->mcu_timing.mcu_pix_total)
	3966	+ vop3_mcu_mode_setup(state);
3064	3967
3065	3968	return 0;
3066	3969	}
..	..	@@ -3071,71 +3974,129 @@
3071	3974	{
3072	3975	uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
3073	3976	uint16_t hscl_filter_mode, vscl_filter_mode;
3074		- uint8_t gt2 = 0, gt4 = 0;
	3977	+ uint8_t xgt2 = 0, xgt4 = 0;
	3978	+ uint8_t ygt2 = 0, ygt4 = 0;
3075	3979	uint32_t xfac = 0, yfac = 0;
3076		- uint16_t hsu_filter_mode = VOP2_SCALE_UP_BIC;
3077		- uint16_t hsd_filter_mode = VOP2_SCALE_DOWN_BIL;
3078		- uint16_t vsu_filter_mode = VOP2_SCALE_UP_BIL;
3079		- uint16_t vsd_filter_mode = VOP2_SCALE_DOWN_BIL;
3080	3980	u32 win_offset = win->reg_offset;
	3981	+ bool xgt_en = false;
	3982	+ bool xavg_en = false;
3081	3983
3082		- if (src_h >= (4 * dst_h))
3083		- gt4 = 1;
3084		- else if (src_h >= (2 * dst_h))
3085		- gt2 = 1;
	3984	+ if (is_vop3(vop2)) {
	3985	+ if (src_w >= (4 * dst_w)) {
	3986	+ xgt4 = 1;
	3987	+ src_w >>= 2;
	3988	+ } else if (src_w >= (2 * dst_w)) {
	3989	+ xgt2 = 1;
	3990	+ src_w >>= 1;
	3991	+ }
	3992	+ }
3086	3993
3087		- if (gt4)
	3994	+ if (src_h >= (4 * dst_h)) {
	3995	+ ygt4 = 1;
3088	3996	src_h >>= 2;
3089		- else if (gt2)
	3997	+ } else if (src_h >= (2 * dst_h)) {
	3998	+ ygt2 = 1;
3090	3999	src_h >>= 1;
	4000	+ }
3091	4001
3092	4002	yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
3093	4003	yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
3094	4004
3095	4005	if (yrgb_hor_scl_mode == SCALE_UP)
3096		- hscl_filter_mode = hsu_filter_mode;
	4006	+ hscl_filter_mode = win->hsu_filter_mode;
3097	4007	else
3098		- hscl_filter_mode = hsd_filter_mode;
	4008	+ hscl_filter_mode = win->hsd_filter_mode;
3099	4009
3100	4010	if (yrgb_ver_scl_mode == SCALE_UP)
3101		- vscl_filter_mode = vsu_filter_mode;
	4011	+ vscl_filter_mode = win->vsu_filter_mode;
3102	4012	else
3103		- vscl_filter_mode = vsd_filter_mode;
	4013	+ vscl_filter_mode = win->vsd_filter_mode;
3104	4014
3105	4015	/*
3106	4016	* RK3568 VOP Esmart/Smart dsp_w should be even pixel
3107	4017	* at scale down mode
3108	4018	*/
3109		- if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) {
	4019	+ if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1) && !is_vop3(vop2)) {
3110	4020	printf("win dst_w[%d] should align as 2 pixel\n", dst_w);
3111	4021	dst_w += 1;
3112	4022	}
3113	4023
3114		- xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w);
3115		- yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h);
	4024	+ if (is_vop3(vop2)) {
	4025	+ xfac = vop3_scale_factor(yrgb_hor_scl_mode, src_w, dst_w, true);
	4026	+ yfac = vop3_scale_factor(yrgb_ver_scl_mode, src_h, dst_h, false);
	4027	+
	4028	+ if (win->hsd_pre_filter_mode == VOP3_PRE_SCALE_DOWN_AVG)
	4029	+ xavg_en = xgt2 \|\| xgt4;
	4030	+ else
	4031	+ xgt_en = xgt2 \|\| xgt4;
	4032	+ } else {
	4033	+ xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w);
	4034	+ yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h);
	4035	+ }
3116	4036
3117	4037	if (win->type == CLUSTER_LAYER) {
3118	4038	vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset,
3119	4039	yfac << 16 \| xfac);
3120	4040
3121		- vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
3122		- YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, gt2, false);
3123		- vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
3124		- YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, gt4, false);
	4041	+ if (is_vop3(vop2)) {
	4042	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4043	+ EN_MASK, CLUSTER_XGT_EN_SHIFT, xgt_en, false);
	4044	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4045	+ EN_MASK, CLUSTER_XAVG_EN_SHIFT, xavg_en, false);
	4046	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4047	+ XGT_MODE_MASK, CLUSTER_XGT_MODE_SHIFT, xgt2 ? 0 : 1, false);
3125	4048
3126		- vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
3127		- YRGB_XSCL_MODE_MASK, CLUSTER_YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false);
3128		- vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
3129		- YRGB_YSCL_MODE_MASK, CLUSTER_YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false);
	4049	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4050	+ YRGB_XSCL_MODE_MASK, RK3528_CLUSTER_YRGB_XSCL_MODE_SHIFT,
	4051	+ yrgb_hor_scl_mode, false);
	4052	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4053	+ YRGB_YSCL_MODE_MASK, RK3528_CLUSTER_YRGB_YSCL_MODE_SHIFT,
	4054	+ yrgb_ver_scl_mode, false);
	4055	+ } else {
	4056	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4057	+ YRGB_XSCL_MODE_MASK, RK3568_CLUSTER_YRGB_XSCL_MODE_SHIFT,
	4058	+ yrgb_hor_scl_mode, false);
	4059	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4060	+ YRGB_YSCL_MODE_MASK, RK3568_CLUSTER_YRGB_YSCL_MODE_SHIFT,
	4061	+ yrgb_ver_scl_mode, false);
	4062	+ }
3130	4063
	4064	+ if (!is_vop3(vop2) \|\| win->vsd_pre_filter_mode == VOP3_PRE_SCALE_DOWN_GT) {
	4065	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4066	+ YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, ygt2, false);
	4067	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4068	+ YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, ygt4, false);
	4069	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4070	+ AVG2_MASK, CLUSTER_AVG2_SHIFT, 0, false);
	4071	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4072	+ AVG4_MASK, CLUSTER_AVG4_SHIFT, 0, false);
	4073	+ } else {
	4074	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4075	+ YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, 0, false);
	4076	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4077	+ YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, 0, false);
	4078	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4079	+ AVG2_MASK, CLUSTER_AVG2_SHIFT, ygt2, false);
	4080	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
	4081	+ AVG4_MASK, CLUSTER_AVG4_SHIFT, ygt4, false);
	4082	+ }
3131	4083	} else {
3132	4084	vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset,
3133	4085	yfac << 16 \| xfac);
3134	4086
	4087	+ if (is_vop3(vop2)) {
	4088	+ vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
	4089	+ EN_MASK, ESMART_XGT_EN_SHIFT, xgt_en, false);
	4090	+ vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
	4091	+ EN_MASK, ESMART_XAVG_EN_SHIFT, xavg_en, false);
	4092	+ vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
	4093	+ XGT_MODE_MASK, ESMART_XGT_MODE_SHIFT, xgt2 ? 0 : 1, false);
	4094	+ }
	4095	+
3135	4096	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
3136		- YRGB_GT2_MASK, YRGB_GT2_SHIFT, gt2, false);
	4097	+ YRGB_GT2_MASK, YRGB_GT2_SHIFT, ygt2, false);
3137	4098	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
3138		- YRGB_GT4_MASK, YRGB_GT4_SHIFT, gt4, false);
	4099	+ YRGB_GT4_MASK, YRGB_GT4_SHIFT, ygt4, false);
3139	4100
3140	4101	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset,
3141	4102	YRGB_XSCL_MODE_MASK, YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false);
..	..	@@ -3172,6 +4133,16 @@
3172	4133	}
3173	4134	}
3174	4135
	4136	+static bool vop2_win_dither_up(uint32_t format)
	4137	+{
	4138	+ switch (format) {
	4139	+ case ROCKCHIP_FMT_RGB565:
	4140	+ return true;
	4141	+ default:
	4142	+ return false;
	4143	+ }
	4144	+}
	4145	+
3175	4146	static void vop2_set_cluster_win(struct display_state state, struct vop2_win_data win)
3176	4147	{
3177	4148	struct crtc_state *cstate = &state->crtc_state;
..	..	@@ -3193,6 +4164,7 @@
3193	4164	u32 splice_yrgb_offset = 0;
3194	4165	u32 win_offset = win->reg_offset;
3195	4166	u32 cfg_done = CFG_DONE_EN \| BIT(cstate->crtc_id) \| (BIT(cstate->crtc_id) << 16);
	4167	+ bool dither_up;
3196	4168
3197	4169	if (win->splice_mode_right) {
3198	4170	src_w = cstate->right_src_rect.w;
..	..	@@ -3223,11 +4195,17 @@
3223	4195
3224	4196	vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h);
3225	4197
3226		- if (vop2->version == VOP_VERSION_RK3588)
	4198	+ if (vop2->version == VOP_VERSION_RK3588 \|\| vop2->version == VOP_VERSION_RK3528 \|\|
	4199	+ vop2->version == VOP_VERSION_RK3562)
3227	4200	vop2_axi_config(vop2, win);
3228	4201
3229	4202	if (y_mirror)
3230	4203	printf("WARN: y mirror is unsupported by cluster window\n");
	4204	+
	4205	+ /* rk3588 should set half_blocK_en to 1 in line and tile mode */
	4206	+ if (vop2->version == VOP_VERSION_RK3588)
	4207	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_AFBCD_CTRL + win_offset,
	4208	+ EN_MASK, CLUSTER_AFBCD_HALF_BLOCK_SHIFT, 1, false);
3231	4209
3232	4210	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset,
3233	4211	WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format,
..	..	@@ -3242,12 +4220,17 @@
3242	4220
3243	4221	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false);
3244	4222
3245		- csc_mode = vop2_convert_csc_mode(conn_state->color_space);
	4223	+ csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_10BIT_DEPTH);
3246	4224	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK,
3247	4225	CLUSTER_RGB2YUV_EN_SHIFT,
3248	4226	is_yuv_output(conn_state->bus_format), false);
3249	4227	vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, CSC_MODE_MASK,
3250	4228	CLUSTER_CSC_MODE_SHIFT, csc_mode, false);
	4229	+
	4230	+ dither_up = vop2_win_dither_up(cstate->format);
	4231	+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK,
	4232	+ CLUSTER_DITHER_UP_EN_SHIFT, dither_up, false);
	4233	+
3251	4234	vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false);
3252	4235
3253	4236	vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);
..	..	@@ -3274,6 +4257,7 @@
3274	4257	u32 splice_yrgb_offset = 0;
3275	4258	u32 win_offset = win->reg_offset;
3276	4259	u32 cfg_done = CFG_DONE_EN \| BIT(cstate->crtc_id) \| (BIT(cstate->crtc_id) << 16);
	4260	+ bool dither_up;
3277	4261
3278	4262	if (win->splice_mode_right) {
3279	4263	src_w = cstate->right_src_rect.w;
..	..	@@ -3311,9 +4295,14 @@
3311	4295	else
3312	4296	y_mirror = 0;
3313	4297
	4298	+ if (is_vop3(vop2))
	4299	+ vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, ESMART_LB_SELECT_MASK,
	4300	+ ESMART_LB_SELECT_SHIFT, win->scale_engine_num, false);
	4301	+
3314	4302	vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h);
3315	4303
3316		- if (vop2->version == VOP_VERSION_RK3588)
	4304	+ if (vop2->version == VOP_VERSION_RK3588 \|\| vop2->version == VOP_VERSION_RK3528 \|\|
	4305	+ vop2->version == VOP_VERSION_RK3562)
3317	4306	vop2_axi_config(vop2, win);
3318	4307
3319	4308	if (y_mirror)
..	..	@@ -3337,12 +4326,16 @@
3337	4326	vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK,
3338	4327	WIN_EN_SHIFT, 1, false);
3339	4328
3340		- csc_mode = vop2_convert_csc_mode(conn_state->color_space);
	4329	+ csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_10BIT_DEPTH);
3341	4330	vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK,
3342	4331	RGB2YUV_EN_SHIFT,
3343	4332	is_yuv_output(conn_state->bus_format), false);
3344	4333	vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK,
3345	4334	CSC_MODE_SHIFT, csc_mode, false);
	4335	+
	4336	+ dither_up = vop2_win_dither_up(cstate->format);
	4337	+ vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK,
	4338	+ REGION0_DITHER_UP_EN_SHIFT, dither_up, false);
3346	4339
3347	4340	vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);
3348	4341	}
..	..	@@ -3412,6 +4405,10 @@
3412	4405	printf("invalid win id %d\n", primary_plane_id);
3413	4406	return -ENODEV;
3414	4407	}
	4408	+
	4409	+ /* ignore some plane register according vop3 esmart lb mode */
	4410	+ if (vop3_ignore_plane(vop2, win_data))
	4411	+ return -EACCES;
3415	4412
3416	4413	if (vop2->version == VOP_VERSION_RK3588) {
3417	4414	if (vop2_power_domain_on(vop2, win_data->pd_id))
..	..	@@ -3494,6 +4491,10 @@
3494	4491	if (cstate->dsc_enable)
3495	4492	vop2_dsc_cfg_done(state);
3496	4493
	4494	+ if (cstate->mcu_timing.mcu_pix_total)
	4495	+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
	4496	+ MCU_HOLD_MODE_SHIFT, 0, false);
	4497	+
3497	4498	return 0;
3498	4499	}
3499	4500
..	..	@@ -3570,7 +4571,7 @@
3570	4571	int vp_id = 0;
3571	4572	int cursor_plane_id = -1;
3572	4573
3573		- if (vop_fix_dts)
	4574	+ if (vop_fix_dts \|\| vop2->version == VOP_VERSION_RK3528)
3574	4575	return 0;
3575	4576
3576	4577	ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) {
..	..	@@ -3638,6 +4639,53 @@
3638	4639	return 0;
3639	4640	}
3640	4641
	4642	+static int rockchip_vop2_mode_fixup(struct display_state *state)
	4643	+{
	4644	+ struct connector_state *conn_state = &state->conn_state;
	4645	+ struct drm_display_mode *mode = &conn_state->mode;
	4646	+ struct crtc_state *cstate = &state->crtc_state;
	4647	+ struct vop2 *vop2 = cstate->private;
	4648	+
	4649	+ drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V \| CRTC_STEREO_DOUBLE);
	4650	+
	4651	+ if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\| conn_state->output_if & VOP_OUTPUT_IF_BT656)
	4652	+ mode->crtc_clock *= 2;
	4653	+
	4654	+ /*
	4655	+ * For RK3528, the path of CVBS output is like:
	4656	+ * VOP BT656 ENCODER -> CVBS BT656 DECODER -> CVBS ENCODER -> CVBS VDAC
	4657	+ * The vop2 dclk should be four times crtc_clock for CVBS sampling
	4658	+ * clock needs.
	4659	+ */
	4660	+ if (vop2->version == VOP_VERSION_RK3528 && conn_state->output_if & VOP_OUTPUT_IF_BT656)
	4661	+ mode->crtc_clock *= 4;
	4662	+
	4663	+ if (cstate->mcu_timing.mcu_pix_total) {
	4664	+ if (conn_state->output_mode == ROCKCHIP_OUT_MODE_S888)
	4665	+ /*
	4666	+ * For serial output_mode rgb3x8, one pixel need 3 cycles.
	4667	+ * So dclk should be three times mode clock.
	4668	+ */
	4669	+ mode->crtc_clock *= 3;
	4670	+ else if (conn_state->output_mode == ROCKCHIP_OUT_MODE_S888_DUMMY)
	4671	+ /*
	4672	+ * For serial output_mode argb4x8, one pixel need 4 cycles.
	4673	+ * So dclk should be four times mode clock.
	4674	+ */
	4675	+ mode->crtc_clock *= 4;
	4676	+ }
	4677	+
	4678	+ if (conn_state->secondary) {
	4679	+ mode->crtc_clock *= 2;
	4680	+ mode->crtc_hdisplay *= 2;
	4681	+ mode->crtc_hsync_start *= 2;
	4682	+ mode->crtc_hsync_end *= 2;
	4683	+ mode->crtc_htotal *= 2;
	4684	+ }
	4685	+
	4686	+ return 0;
	4687	+}
	4688	+
3641	4689	#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
3642	4690
3643	4691	static int rockchip_vop2_plane_check(struct display_state *state)
..	..	@@ -3665,10 +4713,526 @@
3665	4713	if (hscale < 0 \|\| vscale < 0) {
3666	4714	printf("ERROR: VP%d %s: scale factor is out of range\n", cstate->crtc_id, win_data->name);
3667	4715	return -ERANGE;
	4716	+ }
	4717	+
	4718	+ return 0;
	4719	+}
	4720	+
	4721	+static int rockchip_vop2_apply_soft_te(struct display_state *state)
	4722	+{
	4723	+ __maybe_unused struct connector_state *conn_state = &state->conn_state;
	4724	+ struct crtc_state *cstate = &state->crtc_state;
	4725	+ struct vop2 *vop2 = cstate->private;
	4726	+ u32 vp_offset = (cstate->crtc_id * 0x100);
	4727	+ int val = 0;
	4728	+ int ret = 0;
	4729	+
	4730	+ ret = readl_poll_timeout(vop2->regs + RK3568_VP0_MIPI_CTRL + vp_offset, val,
	4731	+ (val >> EDPI_WMS_FS) & 0x1, 50 * 1000);
	4732	+ if (!ret) {
	4733	+#ifndef CONFIG_SPL_BUILD
	4734	+ ret = readx_poll_timeout(dm_gpio_get_value, conn_state->te_gpio, val,
	4735	+ !val, 50 * 1000);
	4736	+ if (!ret) {
	4737	+ ret = readx_poll_timeout(dm_gpio_get_value, conn_state->te_gpio, val,
	4738	+ val, 50 * 1000);
	4739	+ if (!ret) {
	4740	+ vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
	4741	+ EN_MASK, EDPI_WMS_FS, 1, false);
	4742	+ } else {
	4743	+ printf("ERROR: vp%d wait for active TE signal timeout\n",
	4744	+ cstate->crtc_id);
	4745	+ return ret;
	4746	+ }
	4747	+ } else {
	4748	+ printf("ERROR: vp%d TE signal maybe always high\n", cstate->crtc_id);
	4749	+ return ret;
	4750	+ }
	4751	+#endif
	4752	+ } else {
	4753	+ printf("ERROR: vp%d wait vop2 frame start timeout in hold mode\n", cstate->crtc_id);
	4754	+ return ret;
3668	4755	}
3669	4756
3670	4757	return 0;
3671	4758	}
	4759	+
	4760	+static int rockchip_vop2_regs_dump(struct display_state *state)
	4761	+{
	4762	+ struct crtc_state *cstate = &state->crtc_state;
	4763	+ struct vop2 *vop2 = cstate->private;
	4764	+ const struct vop2_data *vop2_data = vop2->data;
	4765	+ const struct vop2_dump_regs *regs = vop2_data->dump_regs;
	4766	+ u32 n, i, j;
	4767	+ u32 base;
	4768	+
	4769	+ if (!cstate->crtc->active)
	4770	+ return -EINVAL;
	4771	+
	4772	+ n = vop2_data->dump_regs_size;
	4773	+ for (i = 0; i < n; i++) {
	4774	+ base = regs[i].offset;
	4775	+ printf("\n%s:\n", regs[i].name);
	4776	+ for (j = 0; j < 68;) {
	4777	+ printf("%08lx: %08x %08x %08x %08x\n", (uintptr_t)vop2->regs + base + j * 4,
	4778	+ vop2_readl(vop2, base + (4 * j)),
	4779	+ vop2_readl(vop2, base + (4 * (j + 1))),
	4780	+ vop2_readl(vop2, base + (4 * (j + 2))),
	4781	+ vop2_readl(vop2, base + (4 * (j + 3))));
	4782	+ j += 4;
	4783	+ }
	4784	+ }
	4785	+
	4786	+ return 0;
	4787	+}
	4788	+
	4789	+static int rockchip_vop2_active_regs_dump(struct display_state *state)
	4790	+{
	4791	+ struct crtc_state *cstate = &state->crtc_state;
	4792	+ struct vop2 *vop2 = cstate->private;
	4793	+ const struct vop2_data *vop2_data = vop2->data;
	4794	+ const struct vop2_dump_regs *regs = vop2_data->dump_regs;
	4795	+ u32 n, i, j;
	4796	+ u32 base;
	4797	+ bool enable_state;
	4798	+
	4799	+ if (!cstate->crtc->active)
	4800	+ return -EINVAL;
	4801	+
	4802	+ n = vop2_data->dump_regs_size;
	4803	+ for (i = 0; i < n; i++) {
	4804	+ if (regs[i].state_mask) {
	4805	+ enable_state = (vop2_readl(vop2, regs[i].state_base) >> regs[i].state_shift) &
	4806	+ regs[i].state_mask;
	4807	+ if (enable_state != regs[i].enable_state)
	4808	+ continue;
	4809	+ }
	4810	+
	4811	+ base = regs[i].offset;
	4812	+ printf("\n%s:\n", regs[i].name);
	4813	+ for (j = 0; j < 68;) {
	4814	+ printf("%08lx: %08x %08x %08x %08x\n", (uintptr_t)vop2->regs + base + j * 4,
	4815	+ vop2_readl(vop2, base + (4 * j)),
	4816	+ vop2_readl(vop2, base + (4 * (j + 1))),
	4817	+ vop2_readl(vop2, base + (4 * (j + 2))),
	4818	+ vop2_readl(vop2, base + (4 * (j + 3))));
	4819	+ j += 4;
	4820	+ }
	4821	+ }
	4822	+
	4823	+ return 0;
	4824	+}
	4825	+
	4826	+static struct vop2_dump_regs rk3528_dump_regs[] = {
	4827	+ { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
	4828	+ { RK3528_OVL_SYS, "OVL_SYS", 0, 0, 0, 0 },
	4829	+ { RK3528_OVL_PORT0_CTRL, "OVL_VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
	4830	+ { RK3528_OVL_PORT1_CTRL, "OVL_VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
	4831	+ { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
	4832	+ { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
	4833	+ { RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0, 1 },
	4834	+ { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
	4835	+ { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
	4836	+ { RK3568_SMART0_CTRL0, "Esmart2", RK3568_SMART0_CTRL0, 0x1, 0, 1 },
	4837	+ { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_CTRL0, 0x1, 0, 1 },
	4838	+ { RK3528_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 },
	4839	+ { RK3528_ACM_CTRL, "ACM", RK3528_ACM_CTRL, 0x1, 0, 1},
	4840	+};
	4841	+
	4842	+static u8 rk3528_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = {
	4843	+ ROCKCHIP_VOP2_ESMART0,
	4844	+ ROCKCHIP_VOP2_ESMART1,
	4845	+ ROCKCHIP_VOP2_ESMART2,
	4846	+ ROCKCHIP_VOP2_ESMART3,
	4847	+};
	4848	+
	4849	+static struct vop2_plane_table rk3528_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = {
	4850	+ {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER},
	4851	+ {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER},
	4852	+ {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER},
	4853	+ {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER},
	4854	+ {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER},
	4855	+};
	4856	+
	4857	+static struct vop2_vp_plane_mask rk3528_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = {
	4858	+ { /* one display policy for hdmi */
	4859	+ {/* main display */
	4860	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
	4861	+ .attached_layers_nr = 4,
	4862	+ .attached_layers = {
	4863	+ ROCKCHIP_VOP2_CLUSTER0,
	4864	+ ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_ESMART2
	4865	+ },
	4866	+ },
	4867	+ {/* second display */},
	4868	+ {/* third display */},
	4869	+ {/* fourth display */},
	4870	+ },
	4871	+
	4872	+ { /* two display policy */
	4873	+ {/* main display */
	4874	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
	4875	+ .attached_layers_nr = 3,
	4876	+ .attached_layers = {
	4877	+ ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1
	4878	+ },
	4879	+ },
	4880	+
	4881	+ {/* second display */
	4882	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART3,
	4883	+ .attached_layers_nr = 2,
	4884	+ .attached_layers = {
	4885	+ ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3
	4886	+ },
	4887	+ },
	4888	+ {/* third display */},
	4889	+ {/* fourth display */},
	4890	+ },
	4891	+
	4892	+ { /* one display policy for cvbs */
	4893	+ {/* main display */
	4894	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART3,
	4895	+ .attached_layers_nr = 2,
	4896	+ .attached_layers = {
	4897	+ ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3
	4898	+ },
	4899	+ },
	4900	+ {/* second display */},
	4901	+ {/* third display */},
	4902	+ {/* fourth display */},
	4903	+ },
	4904	+
	4905	+ {/* reserved */},
	4906	+};
	4907	+
	4908	+static struct vop2_win_data rk3528_win_data[5] = {
	4909	+ {
	4910	+ .name = "Esmart0",
	4911	+ .phys_id = ROCKCHIP_VOP2_ESMART0,
	4912	+ .type = ESMART_LAYER,
	4913	+ .win_sel_port_offset = 8,
	4914	+ .layer_sel_win_id = { 1, 0xff, 0xff, 0xff },
	4915	+ .reg_offset = 0,
	4916	+ .axi_id = 0,
	4917	+ .axi_yrgb_id = 0x06,
	4918	+ .axi_uv_id = 0x07,
	4919	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	4920	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	4921	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	4922	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	4923	+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
	4924	+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */
	4925	+ .max_upscale_factor = 8,
	4926	+ .max_downscale_factor = 8,
	4927	+ },
	4928	+
	4929	+ {
	4930	+ .name = "Esmart1",
	4931	+ .phys_id = ROCKCHIP_VOP2_ESMART1,
	4932	+ .type = ESMART_LAYER,
	4933	+ .win_sel_port_offset = 10,
	4934	+ .layer_sel_win_id = { 2, 0xff, 0xff, 0xff },
	4935	+ .reg_offset = 0x200,
	4936	+ .axi_id = 0,
	4937	+ .axi_yrgb_id = 0x08,
	4938	+ .axi_uv_id = 0x09,
	4939	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	4940	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	4941	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	4942	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	4943	+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
	4944	+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */
	4945	+ .max_upscale_factor = 8,
	4946	+ .max_downscale_factor = 8,
	4947	+ },
	4948	+
	4949	+ {
	4950	+ .name = "Esmart2",
	4951	+ .phys_id = ROCKCHIP_VOP2_ESMART2,
	4952	+ .type = ESMART_LAYER,
	4953	+ .win_sel_port_offset = 12,
	4954	+ .layer_sel_win_id = { 3, 0, 0xff, 0xff },
	4955	+ .reg_offset = 0x400,
	4956	+ .axi_id = 0,
	4957	+ .axi_yrgb_id = 0x0a,
	4958	+ .axi_uv_id = 0x0b,
	4959	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	4960	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	4961	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	4962	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	4963	+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
	4964	+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */
	4965	+ .max_upscale_factor = 8,
	4966	+ .max_downscale_factor = 8,
	4967	+ },
	4968	+
	4969	+ {
	4970	+ .name = "Esmart3",
	4971	+ .phys_id = ROCKCHIP_VOP2_ESMART3,
	4972	+ .type = ESMART_LAYER,
	4973	+ .win_sel_port_offset = 14,
	4974	+ .layer_sel_win_id = { 0xff, 1, 0xff, 0xff },
	4975	+ .reg_offset = 0x600,
	4976	+ .axi_id = 0,
	4977	+ .axi_yrgb_id = 0x0c,
	4978	+ .axi_uv_id = 0x0d,
	4979	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	4980	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	4981	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	4982	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	4983	+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
	4984	+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */
	4985	+ .max_upscale_factor = 8,
	4986	+ .max_downscale_factor = 8,
	4987	+ },
	4988	+
	4989	+ {
	4990	+ .name = "Cluster0",
	4991	+ .phys_id = ROCKCHIP_VOP2_CLUSTER0,
	4992	+ .type = CLUSTER_LAYER,
	4993	+ .win_sel_port_offset = 0,
	4994	+ .layer_sel_win_id = { 0, 0xff, 0xff, 0xff },
	4995	+ .reg_offset = 0,
	4996	+ .axi_id = 0,
	4997	+ .axi_yrgb_id = 0x02,
	4998	+ .axi_uv_id = 0x03,
	4999	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5000	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5001	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5002	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5003	+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
	5004	+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
	5005	+ .max_upscale_factor = 8,
	5006	+ .max_downscale_factor = 8,
	5007	+ },
	5008	+};
	5009	+
	5010	+static struct vop2_vp_data rk3528_vp_data[2] = {
	5011	+ {
	5012	+ .feature = VOP_FEATURE_ALPHA_SCALE \| VOP_FEATURE_OVERSCAN \| VOP_FEATURE_POST_ACM \|
	5013	+ VOP_FEATURE_POST_CSC,
	5014	+ .max_output = {4096, 4096},
	5015	+ .layer_mix_dly = 6,
	5016	+ .hdr_mix_dly = 2,
	5017	+ .win_dly = 8,
	5018	+ },
	5019	+ {
	5020	+ .feature = VOP_FEATURE_ALPHA_SCALE \| VOP_FEATURE_OVERSCAN,
	5021	+ .max_output = {1920, 1080},
	5022	+ .layer_mix_dly = 2,
	5023	+ .hdr_mix_dly = 0,
	5024	+ .win_dly = 8,
	5025	+ },
	5026	+};
	5027	+
	5028	+const struct vop2_data rk3528_vop = {
	5029	+ .version = VOP_VERSION_RK3528,
	5030	+ .nr_vps = 2,
	5031	+ .vp_data = rk3528_vp_data,
	5032	+ .win_data = rk3528_win_data,
	5033	+ .plane_mask = rk3528_vp_plane_mask[0],
	5034	+ .plane_table = rk3528_plane_table,
	5035	+ .vp_primary_plane_order = rk3528_vp_primary_plane_order,
	5036	+ .nr_layers = 5,
	5037	+ .nr_mixers = 3,
	5038	+ .nr_gammas = 2,
	5039	+ .esmart_lb_mode = VOP3_ESMART_4K_2K_2K_MODE,
	5040	+ .dump_regs = rk3528_dump_regs,
	5041	+ .dump_regs_size = ARRAY_SIZE(rk3528_dump_regs),
	5042	+};
	5043	+
	5044	+static struct vop2_dump_regs rk3562_dump_regs[] = {
	5045	+ { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
	5046	+ { RK3528_OVL_SYS, "OVL_SYS", 0, 0, 0, 0 },
	5047	+ { RK3528_OVL_PORT0_CTRL, "OVL_VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
	5048	+ { RK3528_OVL_PORT1_CTRL, "OVL_VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
	5049	+ { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
	5050	+ { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
	5051	+ { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
	5052	+ { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
	5053	+ { RK3568_SMART0_CTRL0, "Esmart2", RK3568_SMART0_CTRL0, 0x1, 0, 1 },
	5054	+ { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_CTRL0, 0x1, 0, 1 },
	5055	+};
	5056	+
	5057	+static u8 rk3562_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = {
	5058	+ ROCKCHIP_VOP2_ESMART0,
	5059	+ ROCKCHIP_VOP2_ESMART1,
	5060	+ ROCKCHIP_VOP2_ESMART2,
	5061	+ ROCKCHIP_VOP2_ESMART3,
	5062	+};
	5063	+
	5064	+static struct vop2_plane_table rk3562_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = {
	5065	+ {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER},
	5066	+ {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER},
	5067	+ {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER},
	5068	+ {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER},
	5069	+};
	5070	+
	5071	+static struct vop2_vp_plane_mask rk3562_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = {
	5072	+ { /* one display policy for hdmi */
	5073	+ {/* main display */
	5074	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
	5075	+ .attached_layers_nr = 4,
	5076	+ .attached_layers = {
	5077	+ ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1,
	5078	+ ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3
	5079	+ },
	5080	+ },
	5081	+ {/* second display */},
	5082	+ {/* third display */},
	5083	+ {/* fourth display */},
	5084	+ },
	5085	+
	5086	+ { /* two display policy */
	5087	+ {/* main display */
	5088	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
	5089	+ .attached_layers_nr = 2,
	5090	+ .attached_layers = {
	5091	+ ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1
	5092	+ },
	5093	+ },
	5094	+
	5095	+ {/* second display */
	5096	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART2,
	5097	+ .attached_layers_nr = 2,
	5098	+ .attached_layers = {
	5099	+ ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3
	5100	+ },
	5101	+ },
	5102	+ {/* third display */},
	5103	+ {/* fourth display */},
	5104	+ },
	5105	+
	5106	+ {/* reserved */},
	5107	+};
	5108	+
	5109	+static struct vop2_win_data rk3562_win_data[4] = {
	5110	+ {
	5111	+ .name = "Esmart0",
	5112	+ .phys_id = ROCKCHIP_VOP2_ESMART0,
	5113	+ .type = ESMART_LAYER,
	5114	+ .win_sel_port_offset = 8,
	5115	+ .layer_sel_win_id = { 0, 0, 0xff, 0xff },
	5116	+ .reg_offset = 0,
	5117	+ .axi_id = 0,
	5118	+ .axi_yrgb_id = 0x02,
	5119	+ .axi_uv_id = 0x03,
	5120	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5121	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5122	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5123	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5124	+ .max_upscale_factor = 8,
	5125	+ .max_downscale_factor = 8,
	5126	+ },
	5127	+
	5128	+ {
	5129	+ .name = "Esmart1",
	5130	+ .phys_id = ROCKCHIP_VOP2_ESMART1,
	5131	+ .type = ESMART_LAYER,
	5132	+ .win_sel_port_offset = 10,
	5133	+ .layer_sel_win_id = { 1, 1, 0xff, 0xff },
	5134	+ .reg_offset = 0x200,
	5135	+ .axi_id = 0,
	5136	+ .axi_yrgb_id = 0x04,
	5137	+ .axi_uv_id = 0x05,
	5138	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5139	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5140	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5141	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5142	+ .max_upscale_factor = 8,
	5143	+ .max_downscale_factor = 8,
	5144	+ },
	5145	+
	5146	+ {
	5147	+ .name = "Esmart2",
	5148	+ .phys_id = ROCKCHIP_VOP2_ESMART2,
	5149	+ .type = ESMART_LAYER,
	5150	+ .win_sel_port_offset = 12,
	5151	+ .layer_sel_win_id = { 2, 2, 0xff, 0xff },
	5152	+ .reg_offset = 0x400,
	5153	+ .axi_id = 0,
	5154	+ .axi_yrgb_id = 0x06,
	5155	+ .axi_uv_id = 0x07,
	5156	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5157	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5158	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5159	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5160	+ .max_upscale_factor = 8,
	5161	+ .max_downscale_factor = 8,
	5162	+ },
	5163	+
	5164	+ {
	5165	+ .name = "Esmart3",
	5166	+ .phys_id = ROCKCHIP_VOP2_ESMART3,
	5167	+ .type = ESMART_LAYER,
	5168	+ .win_sel_port_offset = 14,
	5169	+ .layer_sel_win_id = { 3, 3, 0xff, 0xff },
	5170	+ .reg_offset = 0x600,
	5171	+ .axi_id = 0,
	5172	+ .axi_yrgb_id = 0x08,
	5173	+ .axi_uv_id = 0x0d,
	5174	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5175	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5176	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5177	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5178	+ .max_upscale_factor = 8,
	5179	+ .max_downscale_factor = 8,
	5180	+ },
	5181	+};
	5182	+
	5183	+static struct vop2_vp_data rk3562_vp_data[2] = {
	5184	+ {
	5185	+ .feature = VOP_FEATURE_ALPHA_SCALE \| VOP_FEATURE_OVERSCAN,
	5186	+ .max_output = {2048, 4096},
	5187	+ .win_dly = 8,
	5188	+ .layer_mix_dly = 8,
	5189	+ },
	5190	+ {
	5191	+ .feature = VOP_FEATURE_ALPHA_SCALE \| VOP_FEATURE_OVERSCAN,
	5192	+ .max_output = {2048, 1080},
	5193	+ .win_dly = 8,
	5194	+ .layer_mix_dly = 8,
	5195	+ },
	5196	+};
	5197	+
	5198	+const struct vop2_data rk3562_vop = {
	5199	+ .version = VOP_VERSION_RK3562,
	5200	+ .nr_vps = 2,
	5201	+ .vp_data = rk3562_vp_data,
	5202	+ .win_data = rk3562_win_data,
	5203	+ .plane_mask = rk3562_vp_plane_mask[0],
	5204	+ .plane_table = rk3562_plane_table,
	5205	+ .vp_primary_plane_order = rk3562_vp_primary_plane_order,
	5206	+ .nr_layers = 4,
	5207	+ .nr_mixers = 3,
	5208	+ .nr_gammas = 2,
	5209	+ .esmart_lb_mode = VOP3_ESMART_2K_2K_2K_2K_MODE,
	5210	+ .dump_regs = rk3562_dump_regs,
	5211	+ .dump_regs_size = ARRAY_SIZE(rk3562_dump_regs),
	5212	+};
	5213	+
	5214	+static struct vop2_dump_regs rk3568_dump_regs[] = {
	5215	+ { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
	5216	+ { RK3568_OVL_CTRL, "OVL", 0, 0, 0, 0 },
	5217	+ { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
	5218	+ { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
	5219	+ { RK3568_VP2_DSP_CTRL, "VP2", RK3568_VP2_DSP_CTRL, 0x1, 31, 0 },
	5220	+ { RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0, 1 },
	5221	+ { RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0, 1 },
	5222	+ { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
	5223	+ { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
	5224	+ { RK3568_SMART0_CTRL0, "Smart0", RK3568_SMART0_REGION0_CTRL, 0x1, 0, 1 },
	5225	+ { RK3568_SMART1_CTRL0, "Smart1", RK3568_SMART1_REGION0_CTRL, 0x1, 0, 1 },
	5226	+ { RK3568_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 },
	5227	+};
	5228	+
	5229	+static u8 rk3568_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = {
	5230	+ ROCKCHIP_VOP2_SMART0,
	5231	+ ROCKCHIP_VOP2_SMART1,
	5232	+ ROCKCHIP_VOP2_ESMART0,
	5233	+ ROCKCHIP_VOP2_ESMART1,
	5234	+};
	5235	+
3672	5236	static struct vop2_plane_table rk356x_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = {
3673	5237	{ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER},
3674	5238	{ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER},
..	..	@@ -3748,8 +5312,12 @@
3748	5312	.phys_id = ROCKCHIP_VOP2_CLUSTER0,
3749	5313	.type = CLUSTER_LAYER,
3750	5314	.win_sel_port_offset = 0,
3751		- .layer_sel_win_id = 0,
	5315	+ .layer_sel_win_id = { 0, 0, 0, 0xff },
3752	5316	.reg_offset = 0,
	5317	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5318	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5319	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5320	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3753	5321	.max_upscale_factor = 4,
3754	5322	.max_downscale_factor = 4,
3755	5323	},
..	..	@@ -3759,8 +5327,12 @@
3759	5327	.phys_id = ROCKCHIP_VOP2_CLUSTER1,
3760	5328	.type = CLUSTER_LAYER,
3761	5329	.win_sel_port_offset = 1,
3762		- .layer_sel_win_id = 1,
	5330	+ .layer_sel_win_id = { 1, 1, 1, 0xff },
3763	5331	.reg_offset = 0x200,
	5332	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5333	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5334	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5335	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3764	5336	.max_upscale_factor = 4,
3765	5337	.max_downscale_factor = 4,
3766	5338	},
..	..	@@ -3770,8 +5342,12 @@
3770	5342	.phys_id = ROCKCHIP_VOP2_ESMART0,
3771	5343	.type = ESMART_LAYER,
3772	5344	.win_sel_port_offset = 4,
3773		- .layer_sel_win_id = 2,
	5345	+ .layer_sel_win_id = { 2, 2, 2, 0xff },
3774	5346	.reg_offset = 0,
	5347	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5348	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5349	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5350	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3775	5351	.max_upscale_factor = 8,
3776	5352	.max_downscale_factor = 8,
3777	5353	},
..	..	@@ -3781,8 +5357,12 @@
3781	5357	.phys_id = ROCKCHIP_VOP2_ESMART1,
3782	5358	.type = ESMART_LAYER,
3783	5359	.win_sel_port_offset = 5,
3784		- .layer_sel_win_id = 6,
	5360	+ .layer_sel_win_id = { 6, 6, 6, 0xff },
3785	5361	.reg_offset = 0x200,
	5362	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5363	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5364	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5365	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3786	5366	.max_upscale_factor = 8,
3787	5367	.max_downscale_factor = 8,
3788	5368	},
..	..	@@ -3792,8 +5372,12 @@
3792	5372	.phys_id = ROCKCHIP_VOP2_SMART0,
3793	5373	.type = SMART_LAYER,
3794	5374	.win_sel_port_offset = 6,
3795		- .layer_sel_win_id = 3,
	5375	+ .layer_sel_win_id = { 3, 3, 3, 0xff },
3796	5376	.reg_offset = 0x400,
	5377	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5378	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5379	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5380	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3797	5381	.max_upscale_factor = 8,
3798	5382	.max_downscale_factor = 8,
3799	5383	},
..	..	@@ -3803,8 +5387,12 @@
3803	5387	.phys_id = ROCKCHIP_VOP2_SMART1,
3804	5388	.type = SMART_LAYER,
3805	5389	.win_sel_port_offset = 7,
3806		- .layer_sel_win_id = 7,
	5390	+ .layer_sel_win_id = { 7, 7, 7, 0xff },
3807	5391	.reg_offset = 0x600,
	5392	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5393	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5394	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5395	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3808	5396	.max_upscale_factor = 8,
3809	5397	.max_downscale_factor = 8,
3810	5398	},
..	..	@@ -3835,9 +5423,23 @@
3835	5423	.win_data = rk3568_win_data,
3836	5424	.plane_mask = rk356x_vp_plane_mask[0],
3837	5425	.plane_table = rk356x_plane_table,
	5426	+ .vp_primary_plane_order = rk3568_vp_primary_plane_order,
3838	5427	.nr_layers = 6,
3839	5428	.nr_mixers = 5,
3840	5429	.nr_gammas = 1,
	5430	+ .dump_regs = rk3568_dump_regs,
	5431	+ .dump_regs_size = ARRAY_SIZE(rk3568_dump_regs),
	5432	+};
	5433	+
	5434	+static u8 rk3588_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = {
	5435	+ ROCKCHIP_VOP2_ESMART0,
	5436	+ ROCKCHIP_VOP2_ESMART1,
	5437	+ ROCKCHIP_VOP2_ESMART2,
	5438	+ ROCKCHIP_VOP2_ESMART3,
	5439	+ ROCKCHIP_VOP2_CLUSTER0,
	5440	+ ROCKCHIP_VOP2_CLUSTER1,
	5441	+ ROCKCHIP_VOP2_CLUSTER2,
	5442	+ ROCKCHIP_VOP2_CLUSTER3,
3841	5443	};
3842	5444
3843	5445	static struct vop2_plane_table rk3588_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = {
..	..	@@ -3851,10 +5453,28 @@
3851	5453	{ROCKCHIP_VOP2_ESMART3, ESMART_LAYER},
3852	5454	};
3853	5455
	5456	+static struct vop2_dump_regs rk3588_dump_regs[] = {
	5457	+ { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
	5458	+ { RK3568_OVL_CTRL, "OVL", 0, 0, 0, 0 },
	5459	+ { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
	5460	+ { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
	5461	+ { RK3568_VP2_DSP_CTRL, "VP2", RK3568_VP2_DSP_CTRL, 0x1, 31, 0 },
	5462	+ { RK3588_VP3_DSP_CTRL, "VP3", RK3588_VP3_DSP_CTRL, 0x1, 31, 0 },
	5463	+ { RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0, 1 },
	5464	+ { RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0, 1 },
	5465	+ { RK3588_CLUSTER2_WIN0_CTRL0, "Cluster2", RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 0, 1 },
	5466	+ { RK3588_CLUSTER3_WIN0_CTRL0, "Cluster3", RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 0, 1 },
	5467	+ { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
	5468	+ { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
	5469	+ { RK3568_SMART0_CTRL0, "Esmart2", RK3568_SMART0_REGION0_CTRL, 0x1, 0, 1 },
	5470	+ { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_REGION0_CTRL, 0x1, 0, 1 },
	5471	+ { RK3568_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 },
	5472	+};
	5473	+
3854	5474	static struct vop2_vp_plane_mask rk3588_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = {
3855	5475	{ /* one display policy */
3856	5476	{/* main display */
3857		- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0,
	5477	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
3858	5478	.attached_layers_nr = 8,
3859	5479	.attached_layers = {
3860	5480	ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART2,
..	..	@@ -3869,7 +5489,7 @@
3869	5489
3870	5490	{ /* two display policy */
3871	5491	{/* main display */
3872		- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0,
	5492	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
3873	5493	.attached_layers_nr = 4,
3874	5494	.attached_layers = {
3875	5495	ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0,
..	..	@@ -3878,7 +5498,7 @@
3878	5498	},
3879	5499
3880	5500	{/* second display */
3881		- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2,
	5501	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART2,
3882	5502	.attached_layers_nr = 4,
3883	5503	.attached_layers = {
3884	5504	ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2,
..	..	@@ -3891,7 +5511,7 @@
3891	5511
3892	5512	{ /* three display policy */
3893	5513	{/* main display */
3894		- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0,
	5514	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
3895	5515	.attached_layers_nr = 3,
3896	5516	.attached_layers = {
3897	5517	ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART0
..	..	@@ -3899,7 +5519,7 @@
3899	5519	},
3900	5520
3901	5521	{/* second display */
3902		- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2,
	5522	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART1,
3903	5523	.attached_layers_nr = 3,
3904	5524	.attached_layers = {
3905	5525	ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART1
..	..	@@ -3917,25 +5537,25 @@
3917	5537
3918	5538	{ /* four display policy */
3919	5539	{/* main display */
3920		- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0,
	5540	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
3921	5541	.attached_layers_nr = 2,
3922	5542	.attached_layers = { ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0 },
3923	5543	},
3924	5544
3925	5545	{/* second display */
3926		- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER1,
	5546	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART1,
3927	5547	.attached_layers_nr = 2,
3928	5548	.attached_layers = { ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 },
3929	5549	},
3930	5550
3931	5551	{/* third display */
3932		- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2,
	5552	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART2,
3933	5553	.attached_layers_nr = 2,
3934	5554	.attached_layers = { ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2 },
3935	5555	},
3936	5556
3937	5557	{/* fourth display */
3938		- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER3,
	5558	+ .primary_plane_id = ROCKCHIP_VOP2_ESMART3,
3939	5559	.attached_layers_nr = 2,
3940	5560	.attached_layers = { ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 },
3941	5561	},
..	..	@@ -3950,12 +5570,16 @@
3950	5570	.splice_win_id = ROCKCHIP_VOP2_CLUSTER1,
3951	5571	.type = CLUSTER_LAYER,
3952	5572	.win_sel_port_offset = 0,
3953		- .layer_sel_win_id = 0,
	5573	+ .layer_sel_win_id = { 0, 0, 0, 0 },
3954	5574	.reg_offset = 0,
3955	5575	.axi_id = 0,
3956	5576	.axi_yrgb_id = 2,
3957	5577	.axi_uv_id = 3,
3958	5578	.pd_id = VOP2_PD_CLUSTER0,
	5579	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5580	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5581	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5582	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3959	5583	.max_upscale_factor = 4,
3960	5584	.max_downscale_factor = 4,
3961	5585	},
..	..	@@ -3965,12 +5589,16 @@
3965	5589	.phys_id = ROCKCHIP_VOP2_CLUSTER1,
3966	5590	.type = CLUSTER_LAYER,
3967	5591	.win_sel_port_offset = 1,
3968		- .layer_sel_win_id = 1,
	5592	+ .layer_sel_win_id = { 1, 1, 1, 1 },
3969	5593	.reg_offset = 0x200,
3970	5594	.axi_id = 0,
3971	5595	.axi_yrgb_id = 6,
3972	5596	.axi_uv_id = 7,
3973	5597	.pd_id = VOP2_PD_CLUSTER1,
	5598	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5599	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5600	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5601	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3974	5602	.max_upscale_factor = 4,
3975	5603	.max_downscale_factor = 4,
3976	5604	},
..	..	@@ -3981,12 +5609,16 @@
3981	5609	.splice_win_id = ROCKCHIP_VOP2_CLUSTER3,
3982	5610	.type = CLUSTER_LAYER,
3983	5611	.win_sel_port_offset = 2,
3984		- .layer_sel_win_id = 4,
	5612	+ .layer_sel_win_id = { 4, 4, 4, 4 },
3985	5613	.reg_offset = 0x400,
3986	5614	.axi_id = 1,
3987	5615	.axi_yrgb_id = 2,
3988	5616	.axi_uv_id = 3,
3989	5617	.pd_id = VOP2_PD_CLUSTER2,
	5618	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5619	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5620	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5621	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3990	5622	.max_upscale_factor = 4,
3991	5623	.max_downscale_factor = 4,
3992	5624	},
..	..	@@ -3996,12 +5628,16 @@
3996	5628	.phys_id = ROCKCHIP_VOP2_CLUSTER3,
3997	5629	.type = CLUSTER_LAYER,
3998	5630	.win_sel_port_offset = 3,
3999		- .layer_sel_win_id = 5,
	5631	+ .layer_sel_win_id = { 5, 5, 5, 5 },
4000	5632	.reg_offset = 0x600,
4001	5633	.axi_id = 1,
4002	5634	.axi_yrgb_id = 6,
4003	5635	.axi_uv_id = 7,
4004	5636	.pd_id = VOP2_PD_CLUSTER3,
	5637	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5638	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5639	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5640	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4005	5641	.max_upscale_factor = 4,
4006	5642	.max_downscale_factor = 4,
4007	5643	},
..	..	@@ -4012,11 +5648,15 @@
4012	5648	.splice_win_id = ROCKCHIP_VOP2_ESMART1,
4013	5649	.type = ESMART_LAYER,
4014	5650	.win_sel_port_offset = 4,
4015		- .layer_sel_win_id = 2,
	5651	+ .layer_sel_win_id = { 2, 2, 2, 2 },
4016	5652	.reg_offset = 0,
4017	5653	.axi_id = 0,
4018	5654	.axi_yrgb_id = 0x0a,
4019	5655	.axi_uv_id = 0x0b,
	5656	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5657	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5658	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5659	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4020	5660	.max_upscale_factor = 8,
4021	5661	.max_downscale_factor = 8,
4022	5662	},
..	..	@@ -4026,12 +5666,16 @@
4026	5666	.phys_id = ROCKCHIP_VOP2_ESMART1,
4027	5667	.type = ESMART_LAYER,
4028	5668	.win_sel_port_offset = 5,
4029		- .layer_sel_win_id = 3,
	5669	+ .layer_sel_win_id = { 3, 3, 3, 3 },
4030	5670	.reg_offset = 0x200,
4031	5671	.axi_id = 0,
4032	5672	.axi_yrgb_id = 0x0c,
4033	5673	.axi_uv_id = 0x0d,
4034	5674	.pd_id = VOP2_PD_ESMART,
	5675	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5676	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5677	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5678	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4035	5679	.max_upscale_factor = 8,
4036	5680	.max_downscale_factor = 8,
4037	5681	},
..	..	@@ -4042,12 +5686,16 @@
4042	5686	.splice_win_id = ROCKCHIP_VOP2_ESMART3,
4043	5687	.type = ESMART_LAYER,
4044	5688	.win_sel_port_offset = 6,
4045		- .layer_sel_win_id = 6,
	5689	+ .layer_sel_win_id = { 6, 6, 6, 6 },
4046	5690	.reg_offset = 0x400,
4047	5691	.axi_id = 1,
4048	5692	.axi_yrgb_id = 0x0a,
4049	5693	.axi_uv_id = 0x0b,
4050	5694	.pd_id = VOP2_PD_ESMART,
	5695	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5696	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5697	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5698	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4051	5699	.max_upscale_factor = 8,
4052	5700	.max_downscale_factor = 8,
4053	5701	},
..	..	@@ -4057,12 +5705,16 @@
4057	5705	.phys_id = ROCKCHIP_VOP2_ESMART3,
4058	5706	.type = ESMART_LAYER,
4059	5707	.win_sel_port_offset = 7,
4060		- .layer_sel_win_id = 7,
	5708	+ .layer_sel_win_id = { 7, 7, 7, 7 },
4061	5709	.reg_offset = 0x600,
4062	5710	.axi_id = 1,
4063	5711	.axi_yrgb_id = 0x0c,
4064	5712	.axi_uv_id = 0x0d,
4065	5713	.pd_id = VOP2_PD_ESMART,
	5714	+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
	5715	+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
	5716	+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
	5717	+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4066	5718	.max_upscale_factor = 8,
4067	5719	.max_downscale_factor = 8,
4068	5720	},
..	..	@@ -4218,6 +5870,7 @@
4218	5870	.dsc = rk3588_dsc_data,
4219	5871	.dsc_error_ecw = dsc_ecw,
4220	5872	.dsc_error_buffer_flow = dsc_buffer_flow,
	5873	+ .vp_primary_plane_order = rk3588_vp_primary_plane_order,
4221	5874	.nr_layers = 8,
4222	5875	.nr_mixers = 7,
4223	5876	.nr_gammas = 4,
..	..	@@ -4225,6 +5878,8 @@
4225	5878	.nr_dscs = 2,
4226	5879	.nr_dsc_ecw = ARRAY_SIZE(dsc_ecw),
4227	5880	.nr_dsc_buffer_flow = ARRAY_SIZE(dsc_buffer_flow),
	5881	+ .dump_regs = rk3588_dump_regs,
	5882	+ .dump_regs_size = ARRAY_SIZE(rk3588_dump_regs),
4228	5883	};
4229	5884
4230	5885	const struct rockchip_crtc_funcs rockchip_vop2_funcs = {
..	..	@@ -4235,7 +5890,12 @@
4235	5890	.enable = rockchip_vop2_enable,
4236	5891	.disable = rockchip_vop2_disable,
4237	5892	.fixup_dts = rockchip_vop2_fixup_dts,
	5893	+ .send_mcu_cmd = rockchip_vop2_send_mcu_cmd,
4238	5894	.check = rockchip_vop2_check,
4239	5895	.mode_valid = rockchip_vop2_mode_valid,
	5896	+ .mode_fixup = rockchip_vop2_mode_fixup,
4240	5897	.plane_check = rockchip_vop2_plane_check,
	5898	+ .regs_dump = rockchip_vop2_regs_dump,
	5899	+ .active_regs_dump = rockchip_vop2_active_regs_dump,
	5900	+ .apply_soft_te = rockchip_vop2_apply_soft_te,
4241	5901	};