forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 u-boot/drivers/thermal/rockchip_thermal.c
....@@ -78,6 +78,7 @@
7878 #define TSADCV2_AUTO_PERIOD_HT			0x6c
7979 #define TSADCV3_AUTO_PERIOD			0x154
8080 #define TSADCV3_AUTO_PERIOD_HT			0x158
81
+#define TSADCV3_Q_MAX				0x210
8182 
8283 #define TSADCV2_AUTO_EN				BIT(0)
8384 #define TSADCV2_AUTO_EN_MASK			BIT(16)
....@@ -88,6 +89,7 @@
8889 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK	BIT(24)
8990 
9091 #define TSADCV3_AUTO_Q_SEL_EN			BIT(1)
92
+#define TSADCV3_AUTO_Q_SEL_EN_MASK		BIT(17)
9193 
9294 #define TSADCV2_INT_SRC_EN(chn)			BIT(chn)
9395 #define TSADCV2_INT_SRC_EN_MASK(chn)		BIT(16 + (chn))
....@@ -101,6 +103,7 @@
101103 #define TSADCV2_DATA_MASK			0xfff
102104 #define TSADCV3_DATA_MASK			0x3ff
103105 #define TSADCV4_DATA_MASK			0x1ff
106
+#define TSADCV5_DATA_MASK			0x7ff
104107 
105108 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT	4
106109 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT	4
....@@ -112,6 +115,14 @@
112115 #define TSADCV5_AUTO_PERIOD_HT_TIME		1622 /* 2.5ms */
113116 #define TSADCV6_AUTO_PERIOD_TIME		5000 /* 2.5ms */
114117 #define TSADCV6_AUTO_PERIOD_HT_TIME		5000 /* 2.5ms */
118
+#define TSADCV7_AUTO_PERIOD_TIME		3000 /* 2.5ms */
119
+#define TSADCV7_AUTO_PERIOD_HT_TIME		3000 /* 2.5ms */
120
+#define TSADCV3_Q_MAX_VAL			0x7ff /* 11bit 2047 */
121
+#define TSADCV12_AUTO_PERIOD_TIME		3000 /* 2.5ms */
122
+#define TSADCV12_AUTO_PERIOD_HT_TIME		3000 /* 2.5ms */
123
+#define TSADCV12_Q_MAX_VAL			0xfff /* 12bit 4095 */
124
+#define TSADCV9_Q_MAX				0x210
125
+#define TSADCV9_Q_MAX_VAL			(0xffff0400 << 0)
115126 
116127 #define TSADCV2_USER_INTER_PD_SOC		0x340	/* 13 clocks */
117128 #define TSADCV5_USER_INTER_PD_SOC		0xfc0 /* 97us, at least 90us */
....@@ -123,7 +134,10 @@
123134 #define PX30_GRF_SOC_CON0			0x0400
124135 #define PX30_GRF_SOC_CON2			0x0408
125136 
137
+#define RK3562_GRF_TSADC_CON			0x0580
138
+
126139 #define RK3568_GRF_TSADC_CON			0x0600
140
+#define RK3528_GRF_TSADC_CON			0x40030
127141 #define RK3568_GRF_TSADC_ANA_REG0		(0x10001 << 0)
128142 #define RK3568_GRF_TSADC_ANA_REG1		(0x10001 << 1)
129143 #define RK3568_GRF_TSADC_ANA_REG2		(0x10001 << 2)
....@@ -137,9 +151,10 @@
137151 #define GRF_CON_TSADC_CH_INV			(0x10001 << 1)
138152 #define PX30S_TSADC_TDC_MODE                    (0x10001 << 4)
139153 
140
-#define MIN_TEMP				(-40000)
154
+/* -40 to 125 is reliable, outside the range existed unreliability */
155
+#define MIN_TEMP				(-60000)
141156 #define LOWEST_TEMP				(-273000)
142
-#define MAX_TEMP				(125000)
157
+#define MAX_TEMP				(180000)
143158 #define MAX_ENV_TEMP				(85000)
144159 
145160 #define BASE					(1024)
....@@ -208,7 +223,8 @@
208223 };
209224 
210225 static const struct tsadc_table rk1808_code_table[] = {
211
-	{0, -40000},
226
+	{0, MIN_TEMP},
227
+	{3423, MIN_TEMP},
212228 	{3455, -40000},
213229 	{3463, -35000},
214230 	{3471, -30000},
....@@ -243,11 +259,13 @@
243259 	{3709, 115000},
244260 	{3718, 120000},
245261 	{3726, 125000},
246
-	{TSADCV2_DATA_MASK, 125000},
262
+	{3820, MAX_TEMP},
263
+	{TSADCV2_DATA_MASK, MAX_TEMP},
247264 };
248265 
249266 static const struct tsadc_table rk3228_code_table[] = {
250
-	{0, -40000},
267
+	{0, MIN_TEMP},
268
+	{568, MIN_TEMP},
251269 	{588, -40000},
252270 	{593, -35000},
253271 	{598, -30000},
....@@ -282,11 +300,13 @@
282300 	{749, 115000},
283301 	{754, 120000},
284302 	{760, 125000},
285
-	{TSADCV2_DATA_MASK, 125000},
303
+	{821, MAX_TEMP},
304
+	{TSADCV2_DATA_MASK, MAX_TEMP},
286305 };
287306 
288307 static const struct tsadc_table rk3288_code_table[] = {
289
-	{TSADCV2_DATA_MASK, -40000},
308
+	{TSADCV2_DATA_MASK, MIN_TEMP},
309
+	{3833, MIN_TEMP},
290310 	{3800, -40000},
291311 	{3792, -35000},
292312 	{3783, -30000},
....@@ -321,10 +341,15 @@
321341 	{3452, 115000},
322342 	{3437, 120000},
323343 	{3421, 125000},
344
+	{3350, 145000},
345
+	{3270, 165000},
346
+	{3195, MAX_TEMP},
347
+	{0, MAX_TEMP},
324348 };
325349 
326350 static const struct tsadc_table rk3328_code_table[] = {
327
-	{0, -40000},
351
+	{0, MIN_TEMP},
352
+	{261, MIN_TEMP},
328353 	{296, -40000},
329354 	{304, -35000},
330355 	{313, -30000},
....@@ -358,11 +383,15 @@
358383 	{644, 115000},
359384 	{659, 120000},
360385 	{675, 125000},
361
-	{TSADCV2_DATA_MASK, 125000},
386
+	{745, 145000},
387
+	{825, 165000},
388
+	{900, MAX_TEMP},
389
+	{TSADCV2_DATA_MASK, MAX_TEMP},
362390 };
363391 
364392 static const struct tsadc_table rk3368_code_table[] = {
365
-	{0, -40000},
393
+	{0, MIN_TEMP},
394
+	{98, MIN_TEMP},
366395 	{106, -40000},
367396 	{108, -35000},
368397 	{110, -30000},
....@@ -397,11 +426,13 @@
397426 	{167, 115000},
398427 	{169, 120000},
399428 	{171, 125000},
400
-	{TSADCV3_DATA_MASK, 125000},
429
+	{193, MAX_TEMP},
430
+	{TSADCV3_DATA_MASK, MAX_TEMP},
401431 };
402432 
403433 static const struct tsadc_table rk3399_code_table[] = {
404
-	{0, -40000},
434
+	{0, MIN_TEMP},
435
+	{368, MIN_TEMP},
405436 	{402, -40000},
406437 	{410, -35000},
407438 	{419, -30000},
....@@ -436,11 +467,95 @@
436467 	{668, 115000},
437468 	{677, 120000},
438469 	{685, 125000},
439
-	{TSADCV3_DATA_MASK, 125000},
470
+	{782, MAX_TEMP},
471
+	{TSADCV3_DATA_MASK, MAX_TEMP},
472
+};
473
+
474
+static const struct tsadc_table rk3528_code_table[] = {
475
+	{0, MIN_TEMP},
476
+	{1386, MIN_TEMP},
477
+	{1419, -40000},
478
+	{1427, -35000},
479
+	{1435, -30000},
480
+	{1443, -25000},
481
+	{1452, -20000},
482
+	{1460, -15000},
483
+	{1468, -10000},
484
+	{1477, -5000},
485
+	{1486, 0},
486
+	{1494, 5000},
487
+	{1502, 10000},
488
+	{1510, 15000},
489
+	{1519, 20000},
490
+	{1527, 25000},
491
+	{1535, 30000},
492
+	{1544, 35000},
493
+	{1552, 40000},
494
+	{1561, 45000},
495
+	{1569, 50000},
496
+	{1578, 55000},
497
+	{1586, 60000},
498
+	{1594, 65000},
499
+	{1603, 70000},
500
+	{1612, 75000},
501
+	{1620, 80000},
502
+	{1628, 85000},
503
+	{1637, 90000},
504
+	{1646, 95000},
505
+	{1654, 100000},
506
+	{1662, 105000},
507
+	{1671, 110000},
508
+	{1679, 115000},
509
+	{1688, 120000},
510
+	{1696, 125000},
511
+	{1790, MAX_TEMP},
512
+	{TSADCV5_DATA_MASK, MAX_TEMP},
513
+};
514
+
515
+static const struct tsadc_table rk3562_code_table[] = {
516
+	{0, MIN_TEMP},
517
+	{1385, MIN_TEMP},
518
+	{1419, -40000},
519
+	{1428, -35000},
520
+	{1436, -30000},
521
+	{1445, -25000},
522
+	{1453, -20000},
523
+	{1462, -15000},
524
+	{1470, -10000},
525
+	{1479, -5000},
526
+	{1487, 0},
527
+	{1496, 5000},
528
+	{1504, 10000},
529
+	{1512, 15000},
530
+	{1521, 20000},
531
+	{1529, 25000},
532
+	{1538, 30000},
533
+	{1546, 35000},
534
+	{1555, 40000},
535
+	{1563, 45000},
536
+	{1572, 50000},
537
+	{1580, 55000},
538
+	{1589, 60000},
539
+	{1598, 65000},
540
+	{1606, 70000},
541
+	{1615, 75000},
542
+	{1623, 80000},
543
+	{1632, 85000},
544
+	{1640, 90000},
545
+	{1648, 95000},
546
+	{1657, 100000},
547
+	{1666, 105000},
548
+	{1674, 110000},
549
+	{1682, 115000},
550
+	{1691, 120000},
551
+	{1699, 125000},
552
+	{1793, MAX_TEMP},
553
+	{TSADCV2_DATA_MASK, MAX_TEMP},
440554 };
441555 
442556 static const struct tsadc_table rk3568_code_table[] = {
443
-	{0, -40000},
557
+	{0, MIN_TEMP},
558
+	{1448, MIN_TEMP},
444559 	{1584, -40000},
445560 	{1620, -35000},
446561 	{1652, -30000},
....@@ -475,16 +590,19 @@
475590 	{2636, 115000},
476591 	{2672, 120000},
477592 	{2704, 125000},
478
-	{TSADCV2_DATA_MASK, 125000},
593
+	{3076, MAX_TEMP},
594
+	{TSADCV2_DATA_MASK, MAX_TEMP},
479595 };
480596 
481597 static const struct tsadc_table rk3588_code_table[] = {
482
-	{0, -40000},
598
+	{0, MIN_TEMP},
599
+	{194, MIN_TEMP},
483600 	{215, -40000},
484601 	{285, 25000},
485602 	{350, 85000},
486603 	{395, 125000},
487
-	{TSADCV4_DATA_MASK, 125000},
604
+	{455, MAX_TEMP},
605
+	{TSADCV4_DATA_MASK, MAX_TEMP},
488606 };
489607 
490608 /*
....@@ -806,6 +924,81 @@
806924 	tsadc_init_v2(dev);
807925 	if (!IS_ERR(priv->grf))
808926 		writel(PX30S_TSADC_TDC_MODE, priv->grf + PX30_GRF_SOC_CON0);
927
+}
928
+
929
+static void tsadc_init_v11(struct udevice *dev)
930
+{
931
+	struct rockchip_thermal_priv *priv = dev_get_priv(dev);
932
+
933
+	writel(TSADCV7_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD);
934
+	writel(TSADCV7_AUTO_PERIOD_HT_TIME,
935
+	       priv->base + TSADCV3_AUTO_PERIOD_HT);
936
+	writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
937
+	       priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
938
+	writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
939
+	       priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
940
+	writel(TSADCV3_Q_MAX_VAL, priv->base + TSADCV3_Q_MAX);
941
+	writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
942
+	       priv->base + TSADCV2_AUTO_CON);
943
+
944
+	if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
945
+		writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
946
+		       TSADCV2_AUTO_TSHUT_POLARITY_MASK,
947
+		       priv->base + TSADCV2_AUTO_CON);
948
+	else
949
+		writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
950
+		       priv->base + TSADCV2_AUTO_CON);
951
+
952
+	if (!IS_ERR(priv->grf)) {
953
+		writel(RK3568_GRF_TSADC_TSEN,
954
+		       priv->grf + RK3528_GRF_TSADC_CON);
955
+		udelay(15);
956
+		writel(RK3568_GRF_TSADC_ANA_REG0,
957
+		       priv->grf + RK3528_GRF_TSADC_CON);
958
+		writel(RK3568_GRF_TSADC_ANA_REG1,
959
+		       priv->grf + RK3528_GRF_TSADC_CON);
960
+		writel(RK3568_GRF_TSADC_ANA_REG2,
961
+		       priv->grf + RK3528_GRF_TSADC_CON);
962
+		udelay(200);
963
+	}
964
+}
965
+
966
+static void tsadc_init_v12(struct udevice *dev)
967
+{
968
+	struct rockchip_thermal_priv *priv = dev_get_priv(dev);
969
+
970
+	writel(TSADCV12_AUTO_PERIOD_TIME,
971
+	       priv->base + TSADCV3_AUTO_PERIOD);
972
+	writel(TSADCV12_AUTO_PERIOD_HT_TIME,
973
+	       priv->base + TSADCV3_AUTO_PERIOD_HT);
974
+	writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
975
+	       priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
976
+	writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
977
+	       priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
978
+	writel(TSADCV12_Q_MAX_VAL,
979
+	       priv->base + TSADCV9_Q_MAX);
980
+	writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
981
+	       priv->base + TSADCV2_AUTO_CON);
982
+	if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
983
+		writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
984
+		       TSADCV2_AUTO_TSHUT_POLARITY_MASK,
985
+		       priv->base + TSADCV2_AUTO_CON);
986
+	else
987
+		writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
988
+		       priv->base + TSADCV2_AUTO_CON);
989
+
990
+	if (!IS_ERR(priv->grf)) {
991
+		writel(RK3568_GRF_TSADC_TSEN,
992
+		       priv->grf + RK3562_GRF_TSADC_CON);
993
+		udelay(15);
994
+		writel(RK3568_GRF_TSADC_ANA_REG0,
995
+		       priv->grf + RK3562_GRF_TSADC_CON);
996
+		writel(RK3568_GRF_TSADC_ANA_REG1,
997
+		       priv->grf + RK3562_GRF_TSADC_CON);
998
+		writel(RK3568_GRF_TSADC_ANA_REG2,
999
+		       priv->grf + RK3562_GRF_TSADC_CON);
1000
+		udelay(200);
1001
+	}
8091002 }
8101003 
8111004 static int tsadc_get_temp_v2(struct udevice *dev,
....@@ -1381,6 +1574,54 @@
13811574 	},
13821575 };
13831576 
1577
+static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
1578
+	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1579
+	.chn_num = 1, /* one channels for tsadc */
1580
+
1581
+	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via GPIO give PMIC */
1582
+	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1583
+	.tshut_temp = 95000,
1584
+
1585
+	.tsadc_init = tsadc_init_v11,
1586
+	.tsadc_control = tsadc_control_v4,
1587
+	.tsadc_get_temp = tsadc_get_temp_v4,
1588
+	.irq_ack = tsadc_irq_ack_v4,
1589
+	.set_alarm_temp = tsadc_alarm_temp_v3,
1590
+	.set_tshut_temp = tsadc_tshut_temp_v3,
1591
+	.set_tshut_mode = tsadc_tshut_mode_v4,
1592
+
1593
+	.table = {
1594
+		.id = rk3528_code_table,
1595
+		.length = ARRAY_SIZE(rk3528_code_table),
1596
+		.data_mask = TSADCV2_DATA_MASK,
1597
+		.mode = ADC_INCREMENT,
1598
+	},
1599
+};
1600
+
1601
+static const struct rockchip_tsadc_chip rk3562_tsadc_data = {
1602
+	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1603
+	.chn_num = 1, /* one channels for tsadc */
1604
+
1605
+	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1606
+	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1607
+	.tshut_temp = 95000,
1608
+
1609
+	.tsadc_init = tsadc_init_v12,
1610
+	.tsadc_control = tsadc_control_v4,
1611
+	.tsadc_get_temp = tsadc_get_temp_v4,
1612
+	.irq_ack = tsadc_irq_ack_v4,
1613
+	.set_alarm_temp = tsadc_alarm_temp_v3,
1614
+	.set_tshut_temp = tsadc_tshut_temp_v3,
1615
+	.set_tshut_mode = tsadc_tshut_mode_v4,
1616
+
1617
+	.table = {
1618
+		.id = rk3562_code_table,
1619
+		.length = ARRAY_SIZE(rk3562_code_table),
1620
+		.data_mask = TSADCV2_DATA_MASK,
1621
+		.mode = ADC_INCREMENT,
1622
+	},
1623
+};
1624
+
13841625 static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
13851626 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
13861627 	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
....@@ -1477,6 +1718,14 @@
14771718 		.data = (ulong)&rk3399_tsadc_data,
14781719 	},
14791720 	{
1721
+		.compatible = "rockchip,rk3528-tsadc",
1722
+		.data = (ulong)&rk3528_tsadc_data,
1723
+	},
1724
+	{
1725
+		.compatible = "rockchip,rk3562-tsadc",
1726
+		.data = (ulong)&rk3562_tsadc_data,
1727
+	},
1728
+	{
14801729 		.compatible = "rockchip,rk3568-tsadc",
14811730 		.data = (ulong)&rk3568_tsadc_data,
14821731 	},