~hc/RK356X_SDK_RELEASE.git

..	..	@@ -18,6 +18,9 @@
18	18	#include <asm/arch/clock.h>
19	19	#include <asm/arch/hardware.h>
20	20	#ifdef CONFIG_DWC_ETH_QOS
	21	+#include <asm/arch/grf_rk3528.h>
	22	+#include <asm/arch/grf_rk3562.h>
	23	+#include <asm/arch/ioc_rk3562.h>
21	24	#include <asm/arch/grf_rk3568.h>
22	25	#include <asm/arch/grf_rk3588.h>
23	26	#include <asm/arch/grf_rv1106.h>
..	..	@@ -516,6 +519,147 @@
516	519	return 0;
517	520	}
518	521	#else
	522	+static int rk3528_set_rgmii_speed(struct gmac_rockchip_platdata *pdata,
	523	+ struct rockchip_eth_dev *dev)
	524	+{
	525	+ struct eqos_priv *priv = &dev->eqos;
	526	+ struct rk3528_grf *grf;
	527	+ unsigned int div;
	528	+
	529	+ enum {
	530	+ RK3528_GMAC0_CLK_RMII_DIV_SHIFT = 3,
	531	+ RK3528_GMAC0_CLK_RMII_DIV_MASK = GENMASK(4, 3),
	532	+ RK3528_GMAC0_CLK_RMII_DIV2 = BIT(3),
	533	+ RK3528_GMAC0_CLK_RMII_DIV20 = 0,
	534	+ };
	535	+
	536	+ enum {
	537	+ RK3528_GMAC1_CLK_RGMII_DIV_SHIFT = 10,
	538	+ RK3528_GMAC1_CLK_RGMII_DIV_MASK = GENMASK(11, 10),
	539	+ RK3528_GMAC1_CLK_RGMII_DIV1 = 0,
	540	+ RK3528_GMAC1_CLK_RGMII_DIV5 = GENMASK(11, 10),
	541	+ RK3528_GMAC1_CLK_RGMII_DIV50 = BIT(11),
	542	+ RK3528_GMAC1_CLK_RMII_DIV2 = BIT(11),
	543	+ RK3528_GMAC1_CLK_RMII_DIV20 = 0,
	544	+ };
	545	+
	546	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	547	+
	548	+ switch (priv->phy->speed) {
	549	+ case 10:
	550	+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
	551	+ div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV20 :
	552	+ RK3528_GMAC0_CLK_RMII_DIV20;
	553	+ else
	554	+ div = RK3528_GMAC1_CLK_RGMII_DIV50;
	555	+ break;
	556	+ case 100:
	557	+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
	558	+ div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV2 :
	559	+ RK3528_GMAC0_CLK_RMII_DIV2;
	560	+ else
	561	+ div = RK3528_GMAC1_CLK_RGMII_DIV5;
	562	+ break;
	563	+ case 1000:
	564	+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
	565	+ div = RK3528_GMAC1_CLK_RGMII_DIV1;
	566	+ else
	567	+ return -EINVAL;
	568	+ break;
	569	+ default:
	570	+ debug("Unknown phy speed: %d\n", priv->phy->speed);
	571	+ return -EINVAL;
	572	+ }
	573	+
	574	+ if (pdata->bus_id)
	575	+ rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_RGMII_DIV_MASK, div);
	576	+ else
	577	+ rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_DIV_MASK, div);
	578	+
	579	+ return 0;
	580	+}
	581	+
	582	+static int rk3562_set_gmac_speed(struct gmac_rockchip_platdata *pdata,
	583	+ struct rockchip_eth_dev *dev)
	584	+{
	585	+ struct eqos_priv *priv = &dev->eqos;
	586	+ struct rk3562_grf *grf;
	587	+ unsigned int div;
	588	+
	589	+ enum {
	590	+ RK3562_GMAC0_CLK_RGMII_DIV_SHIFT = 7,
	591	+ RK3562_GMAC0_CLK_RGMII_DIV_MASK = GENMASK(8, 7),
	592	+ RK3562_GMAC0_CLK_RGMII_DIV1 = 0,
	593	+ RK3562_GMAC0_CLK_RGMII_DIV5 = GENMASK(8, 7),
	594	+ RK3562_GMAC0_CLK_RGMII_DIV50 = BIT(8),
	595	+ RK3562_GMAC0_CLK_RMII_DIV2 = BIT(7),
	596	+ RK3562_GMAC0_CLK_RMII_DIV20 = 0,
	597	+ };
	598	+
	599	+ enum {
	600	+ RK3562_GMAC1_SPEED_SHIFT = 0x0,
	601	+ RK3562_GMAC1_SPEED_MASK = BIT(0),
	602	+ RK3562_GMAC1_SPEED_10M = 0,
	603	+ RK3562_GMAC1_SPEED_100M = BIT(0),
	604	+ };
	605	+
	606	+ enum {
	607	+ RK3562_GMAC1_CLK_RMII_DIV_SHIFT = 13,
	608	+ RK3562_GMAC1_CLK_RMII_DIV_MASK = BIT(13),
	609	+ RK3562_GMAC1_CLK_RMII_DIV2 = BIT(13),
	610	+ RK3562_GMAC1_CLK_RMII_DIV20 = 0,
	611	+ };
	612	+
	613	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	614	+
	615	+ switch (priv->phy->speed) {
	616	+ case 10:
	617	+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) {
	618	+ if (pdata->bus_id > 0) {
	619	+ div = RK3562_GMAC1_CLK_RMII_DIV20;
	620	+ rk_clrsetreg(&grf->soc_con[0],
	621	+ RK3562_GMAC1_SPEED_MASK,
	622	+ RK3562_GMAC1_SPEED_10M);
	623	+ } else {
	624	+ div = RK3562_GMAC0_CLK_RMII_DIV20;
	625	+ }
	626	+ } else {
	627	+ div = RK3562_GMAC0_CLK_RGMII_DIV50;
	628	+ }
	629	+ break;
	630	+ case 100:
	631	+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) {
	632	+ if (pdata->bus_id > 0) {
	633	+ div = RK3562_GMAC1_CLK_RMII_DIV2;
	634	+ rk_clrsetreg(&grf->soc_con[0],
	635	+ RK3562_GMAC1_SPEED_MASK,
	636	+ RK3562_GMAC1_SPEED_100M);
	637	+ } else {
	638	+ div = RK3562_GMAC0_CLK_RMII_DIV2;
	639	+ }
	640	+ } else {
	641	+ div = RK3562_GMAC0_CLK_RGMII_DIV5;
	642	+ }
	643	+ break;
	644	+ case 1000:
	645	+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
	646	+ div = RK3562_GMAC0_CLK_RGMII_DIV1;
	647	+ else
	648	+ return -EINVAL;
	649	+ break;
	650	+ default:
	651	+ debug("Unknown phy speed: %d\n", priv->phy->speed);
	652	+ return -EINVAL;
	653	+ }
	654	+
	655	+ if (pdata->bus_id)
	656	+ rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_RMII_DIV_MASK, div);
	657	+ else
	658	+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_RGMII_DIV_MASK, div);
	659	+
	660	+ return 0;
	661	+}
	662	+
519	663	static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata,
520	664	struct rockchip_eth_dev *dev)
521	665	{
..	..	@@ -1064,6 +1208,251 @@
1064	1208	}
1065	1209
1066	1210	#else
	1211	+static void rk3528_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
	1212	+{
	1213	+ struct rk3528_grf *grf;
	1214	+ unsigned char bgs[1] = {0};
	1215	+
	1216	+ enum {
	1217	+ RK3528_MACPHY_ENABLE_MASK = BIT(1),
	1218	+ RK3528_MACPHY_DISENABLE = BIT(1),
	1219	+ RK3528_MACPHY_ENABLE = 0,
	1220	+ RK3528_MACPHY_XMII_SEL_MASK = GENMASK(6, 5),
	1221	+ RK3528_MACPHY_XMII_SEL = BIT(6),
	1222	+ RK3528_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7),
	1223	+ RK3528_MACPHY_24M_CLK_SEL_24M = (BIT(8) \| BIT(9)),
	1224	+ RK3528_MACPHY_PHY_ID_MASK = GENMASK(14, 10),
	1225	+ RK3528_MACPHY_PHY_ID = BIT(11),
	1226	+ };
	1227	+
	1228	+ enum {
	1229	+ RK3528_MACPHY_BGS_MASK = GENMASK(3, 0),
	1230	+ };
	1231	+
	1232	+#if defined(CONFIG_ROCKCHIP_EFUSE) \|\| defined(CONFIG_ROCKCHIP_OTP)
	1233	+ struct udevice *dev;
	1234	+ u32 regs[2] = {0};
	1235	+ ofnode node;
	1236	+ int ret = 0;
	1237	+
	1238	+ /* retrieve the device */
	1239	+ if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE))
	1240	+ ret = uclass_get_device_by_driver(UCLASS_MISC,
	1241	+ DM_GET_DRIVER(rockchip_efuse),
	1242	+ &dev);
	1243	+ else
	1244	+ ret = uclass_get_device_by_driver(UCLASS_MISC,
	1245	+ DM_GET_DRIVER(rockchip_otp),
	1246	+ &dev);
	1247	+ if (!ret) {
	1248	+ node = dev_read_subnode(dev, "macphy-bgs");
	1249	+ if (ofnode_valid(node)) {
	1250	+ if (!ofnode_read_u32_array(node, "reg", regs, 2)) {
	1251	+ /* read the bgs from the efuses */
	1252	+ ret = misc_read(dev, regs[0], &bgs, 1);
	1253	+ if (ret) {
	1254	+ printf("read bgs from efuse/otp failed, ret=%d\n",
	1255	+ ret);
	1256	+ bgs[0] = 0;
	1257	+ }
	1258	+ }
	1259	+ }
	1260	+ }
	1261	+#endif
	1262	+
	1263	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	1264	+
	1265	+ reset_assert(&pdata->phy_reset);
	1266	+ udelay(20);
	1267	+ rk_clrsetreg(&grf->macphy_con0,
	1268	+ RK3528_MACPHY_ENABLE_MASK \|
	1269	+ RK3528_MACPHY_XMII_SEL_MASK \|
	1270	+ RK3528_MACPHY_24M_CLK_SEL_MASK \|
	1271	+ RK3528_MACPHY_PHY_ID_MASK,
	1272	+ RK3528_MACPHY_ENABLE \|
	1273	+ RK3528_MACPHY_XMII_SEL \|
	1274	+ RK3528_MACPHY_24M_CLK_SEL_24M \|
	1275	+ RK3528_MACPHY_PHY_ID);
	1276	+
	1277	+ rk_clrsetreg(&grf->macphy_con1,
	1278	+ RK3528_MACPHY_BGS_MASK,
	1279	+ bgs[0]);
	1280	+ udelay(20);
	1281	+ reset_deassert(&pdata->phy_reset);
	1282	+ udelay(30 * 1000);
	1283	+}
	1284	+
	1285	+static void rk3528_set_to_rmii(struct gmac_rockchip_platdata *pdata)
	1286	+{
	1287	+ unsigned int clk_mode;
	1288	+ struct rk3528_grf *grf;
	1289	+
	1290	+ enum {
	1291	+ RK3528_GMAC0_CLK_RMII_MODE_SHIFT = 0x1,
	1292	+ RK3528_GMAC0_CLK_RMII_MODE_MASK = BIT(1),
	1293	+ RK3528_GMAC0_CLK_RMII_MODE = 0x1,
	1294	+ };
	1295	+
	1296	+ enum {
	1297	+ RK3528_GMAC1_CLK_RMII_MODE_SHIFT = 0x8,
	1298	+ RK3528_GMAC1_CLK_RMII_MODE_MASK = BIT(8),
	1299	+ RK3528_GMAC1_CLK_RMII_MODE = 0x1,
	1300	+ };
	1301	+
	1302	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	1303	+
	1304	+ if (pdata->bus_id == 1) {
	1305	+ clk_mode = RK3528_GMAC1_CLK_RMII_MODE << RK3528_GMAC1_CLK_RMII_MODE_SHIFT;
	1306	+ rk_clrsetreg(&grf->gmac1_con1, RK3528_GMAC1_CLK_RMII_MODE_MASK, clk_mode);
	1307	+ } else {
	1308	+ clk_mode = RK3528_GMAC0_CLK_RMII_MODE << RK3528_GMAC0_CLK_RMII_MODE_SHIFT;
	1309	+ rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_MODE_MASK, clk_mode);
	1310	+ }
	1311	+}
	1312	+
	1313	+static void rk3528_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
	1314	+{
	1315	+ unsigned int rx_enable;
	1316	+ unsigned int rx_delay;
	1317	+ struct rk3528_grf *grf;
	1318	+
	1319	+ enum {
	1320	+ RK3528_GMAC1_RGMII_MODE_SHIFT = 0x8,
	1321	+ RK3528_GMAC1_RGMII_MODE_MASK = BIT(8),
	1322	+ RK3528_GMAC1_RGMII_MODE = 0x0,
	1323	+
	1324	+ RK3528_GMAC1_TXCLK_DLY_ENA_MASK = BIT(14),
	1325	+ RK3528_GMAC1_TXCLK_DLY_ENA_DISABLE = 0,
	1326	+ RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE = BIT(14),
	1327	+
	1328	+ RK3528_GMAC1_RXCLK_DLY_ENA_MASK = BIT(15),
	1329	+ RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE = 0,
	1330	+ RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE = BIT(15),
	1331	+ };
	1332	+
	1333	+ enum {
	1334	+ RK3528_GMAC1_RX_DL_CFG_SHIFT = 0x8,
	1335	+ RK3528_GMAC1_RX_DL_CFG_MASK = GENMASK(15, 8),
	1336	+
	1337	+ RK3528_GMAC1_TX_DL_CFG_SHIFT = 0x0,
	1338	+ RK3528_GMAC1_TX_DL_CFG_MASK = GENMASK(7, 0),
	1339	+ };
	1340	+
	1341	+ if (!pdata->bus_id)
	1342	+ return;
	1343	+
	1344	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	1345	+
	1346	+ if (pdata->rx_delay < 0) {
	1347	+ rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE;
	1348	+ rx_delay = 0;
	1349	+ } else {
	1350	+ rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE;
	1351	+ rx_delay = pdata->rx_delay << RK3528_GMAC1_RX_DL_CFG_SHIFT;
	1352	+ }
	1353	+
	1354	+ rk_clrsetreg(&grf->gmac1_con0,
	1355	+ RK3528_GMAC1_TXCLK_DLY_ENA_MASK \|
	1356	+ RK3528_GMAC1_RXCLK_DLY_ENA_MASK \|
	1357	+ RK3528_GMAC1_RGMII_MODE_MASK,
	1358	+ rx_enable \| RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE \|
	1359	+ (RK3528_GMAC1_RGMII_MODE << RK3528_GMAC1_RGMII_MODE_SHIFT));
	1360	+
	1361	+ rk_clrsetreg(&grf->gmac1_con1,
	1362	+ RK3528_GMAC1_RX_DL_CFG_MASK \|
	1363	+ RK3528_GMAC1_TX_DL_CFG_MASK,
	1364	+ (pdata->tx_delay << RK3528_GMAC1_TX_DL_CFG_SHIFT) \|
	1365	+ rx_delay);
	1366	+}
	1367	+
	1368	+static void rk3562_set_to_rmii(struct gmac_rockchip_platdata *pdata)
	1369	+{
	1370	+ struct rk3562_grf *grf;
	1371	+ unsigned int mode;
	1372	+
	1373	+ enum {
	1374	+ RK3562_GMAC0_RMII_MODE_SHIFT = 0x5,
	1375	+ RK3562_GMAC0_RMII_MODE_MASK = BIT(5),
	1376	+ RK3562_GMAC0_RMII_MODE = 0x1,
	1377	+ };
	1378	+
	1379	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	1380	+
	1381	+ if (!pdata->bus_id) {
	1382	+ mode = RK3562_GMAC0_RMII_MODE << RK3562_GMAC0_RMII_MODE_SHIFT;
	1383	+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RMII_MODE_MASK, mode);
	1384	+ }
	1385	+}
	1386	+
	1387	+static void rk3562_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
	1388	+{
	1389	+ struct rk3562_grf *grf;
	1390	+ struct rk3562_ioc *ioc;
	1391	+ unsigned int rx_enable;
	1392	+ unsigned int rx_delay;
	1393	+
	1394	+ enum {
	1395	+ RK3562_GMAC0_RGMII_MODE_SHIFT = 0x5,
	1396	+ RK3562_GMAC0_RGMII_MODE_MASK = BIT(5),
	1397	+ RK3562_GMAC0_RGMII_MODE = 0x0,
	1398	+
	1399	+ RK3562_GMAC0_TXCLK_DLY_ENA_MASK = BIT(0),
	1400	+ RK3562_GMAC0_TXCLK_DLY_ENA_DISABLE = 0,
	1401	+ RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE = BIT(0),
	1402	+
	1403	+ RK3562_GMAC0_RXCLK_DLY_ENA_MASK = BIT(1),
	1404	+ RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE = 0,
	1405	+ RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE = BIT(1),
	1406	+ };
	1407	+
	1408	+ enum {
	1409	+ RK3562_GMAC0_RX_DL_CFG_SHIFT = 0x8,
	1410	+ RK3562_GMAC0_RX_DL_CFG_MASK = GENMASK(15, 8),
	1411	+
	1412	+ RK3562_GMAC0_TX_DL_CFG_SHIFT = 0x0,
	1413	+ RK3562_GMAC0_TX_DL_CFG_MASK = GENMASK(7, 0),
	1414	+ };
	1415	+
	1416	+ if (pdata->bus_id)
	1417	+ return;
	1418	+
	1419	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	1420	+ ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC);
	1421	+
	1422	+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RGMII_MODE_MASK,
	1423	+ RK3562_GMAC0_RGMII_MODE << RK3562_GMAC0_RGMII_MODE_SHIFT);
	1424	+
	1425	+ if (pdata->rx_delay < 0) {
	1426	+ rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE;
	1427	+ rx_delay = 0;
	1428	+ } else {
	1429	+ rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE;
	1430	+ rx_delay = pdata->rx_delay << RK3562_GMAC0_RX_DL_CFG_SHIFT;
	1431	+ }
	1432	+
	1433	+ rk_clrsetreg(&ioc->mac0_io_con1,
	1434	+ RK3562_GMAC0_TXCLK_DLY_ENA_MASK \|
	1435	+ RK3562_GMAC0_RXCLK_DLY_ENA_MASK,
	1436	+ rx_enable \| RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE);
	1437	+
	1438	+ rk_clrsetreg(&ioc->mac0_io_con0,
	1439	+ RK3562_GMAC0_RX_DL_CFG_MASK \|
	1440	+ RK3562_GMAC0_TX_DL_CFG_MASK,
	1441	+ (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) \|
	1442	+ rx_delay);
	1443	+
	1444	+ rk_clrsetreg(&ioc->mac1_io_con1,
	1445	+ RK3562_GMAC0_TXCLK_DLY_ENA_MASK \|
	1446	+ RK3562_GMAC0_RXCLK_DLY_ENA_MASK,
	1447	+ rx_enable \| RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE);
	1448	+
	1449	+ rk_clrsetreg(&ioc->mac1_io_con0,
	1450	+ RK3562_GMAC0_RX_DL_CFG_MASK \|
	1451	+ RK3562_GMAC0_TX_DL_CFG_MASK,
	1452	+ (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) \|
	1453	+ rx_delay);
	1454	+}
	1455	+
1067	1456	static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata)
1068	1457	{
1069	1458	struct rk3568_grf *grf;
..	..	@@ -1438,6 +1827,86 @@
1438	1827	#endif
1439	1828
1440	1829	#ifdef CONFIG_DWC_ETH_QOS
	1830	+static void rk3528_set_clock_selection(struct gmac_rockchip_platdata *pdata)
	1831	+{
	1832	+ struct rk3528_grf *grf;
	1833	+ unsigned int val;
	1834	+
	1835	+ enum {
	1836	+ RK3528_GMAC1_CLK_SELET_SHIFT = 0x12,
	1837	+ RK3528_GMAC1_CLK_SELET_MASK = BIT(12),
	1838	+ RK3528_GMAC1_CLK_SELET_CRU = 0,
	1839	+ RK3528_GMAC1_CLK_SELET_IO = BIT(12),
	1840	+ };
	1841	+
	1842	+ if (!pdata->bus_id)
	1843	+ return;
	1844	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	1845	+
	1846	+ val = pdata->clock_input ? RK3528_GMAC1_CLK_SELET_IO :
	1847	+ RK3528_GMAC1_CLK_SELET_CRU;
	1848	+ rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_SELET_MASK, val);
	1849	+}
	1850	+
	1851	+static void rk3562_set_clock_selection(struct gmac_rockchip_platdata *pdata)
	1852	+{
	1853	+ struct rk3562_grf *grf;
	1854	+ struct rk3562_ioc *ioc;
	1855	+ unsigned int val;
	1856	+
	1857	+ enum {
	1858	+ RK3562_GMAC0_CLK_SELET_SHIFT = 0x9,
	1859	+ RK3562_GMAC0_CLK_SELET_MASK = BIT(9),
	1860	+ RK3562_GMAC0_CLK_SELET_CRU = 0,
	1861	+ RK3562_GMAC0_CLK_SELET_IO = BIT(9),
	1862	+ };
	1863	+
	1864	+ enum {
	1865	+ RK3562_GMAC1_CLK_SELET_SHIFT = 15,
	1866	+ RK3562_GMAC1_CLK_SELET_MASK = BIT(15),
	1867	+ RK3562_GMAC1_CLK_SELET_CRU = 0,
	1868	+ RK3562_GMAC1_CLK_SELET_IO = BIT(15),
	1869	+ };
	1870	+
	1871	+ enum {
	1872	+ RK3562_GMAC0_IO_EXTCLK_SELET_SHIFT = 0x2,
	1873	+ RK3562_GMAC0_IO_EXTCLK_SELET_MASK = BIT(2),
	1874	+ RK3562_GMAC0_IO_EXTCLK_SELET_CRU = 0,
	1875	+ RK3562_GMAC0_IO_EXTCLK_SELET_IO = BIT(2),
	1876	+ };
	1877	+
	1878	+ enum {
	1879	+ RK3562_GMAC1_IO_EXTCLK_SELET_SHIFT = 0x3,
	1880	+ RK3562_GMAC1_IO_EXTCLK_SELET_MASK = BIT(3),
	1881	+ RK3562_GMAC1_IO_EXTCLK_SELET_CRU = 0,
	1882	+ RK3562_GMAC1_IO_EXTCLK_SELET_IO = BIT(3),
	1883	+ };
	1884	+
	1885	+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
	1886	+ ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC);
	1887	+
	1888	+ if (!pdata->bus_id) {
	1889	+ val = pdata->clock_input ? RK3562_GMAC0_CLK_SELET_IO :
	1890	+ RK3562_GMAC0_CLK_SELET_CRU;
	1891	+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_SELET_MASK, val);
	1892	+ val = pdata->clock_input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO :
	1893	+ RK3562_GMAC0_IO_EXTCLK_SELET_CRU;
	1894	+ rk_clrsetreg(&ioc->mac1_io_con1,
	1895	+ RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val);
	1896	+ rk_clrsetreg(&ioc->mac0_io_con1,
	1897	+ RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val);
	1898	+
	1899	+ } else {
	1900	+ val = pdata->clock_input ? RK3562_GMAC1_CLK_SELET_IO :
	1901	+ RK3562_GMAC1_CLK_SELET_CRU;
	1902	+ rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_SELET_MASK, val);
	1903	+ val = pdata->clock_input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO :
	1904	+ RK3562_GMAC1_IO_EXTCLK_SELET_CRU;
	1905	+ rk_clrsetreg(&ioc->mac1_io_con1,
	1906	+ RK3562_GMAC1_IO_EXTCLK_SELET_MASK, val);
	1907	+ }
	1908	+}
	1909	+
1441	1910	static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata)
1442	1911	{
1443	1912	struct rk3588_php_grf *php_grf;
..	..	@@ -1701,6 +2170,21 @@
1701	2170	.set_to_rmii = rv1108_gmac_set_to_rmii,
1702	2171	};
1703	2172	#else
	2173	+const struct rk_gmac_ops rk3528_gmac_ops = {
	2174	+ .fix_mac_speed = rk3528_set_rgmii_speed,
	2175	+ .set_to_rgmii = rk3528_set_to_rgmii,
	2176	+ .set_to_rmii = rk3528_set_to_rmii,
	2177	+ .set_clock_selection = rk3528_set_clock_selection,
	2178	+ .integrated_phy_powerup = rk3528_gmac_integrated_phy_powerup,
	2179	+};
	2180	+
	2181	+const struct rk_gmac_ops rk3562_gmac_ops = {
	2182	+ .fix_mac_speed = rk3562_set_gmac_speed,
	2183	+ .set_to_rgmii = rk3562_set_to_rgmii,
	2184	+ .set_to_rmii = rk3562_set_to_rmii,
	2185	+ .set_clock_selection = rk3562_set_clock_selection,
	2186	+};
	2187	+
1704	2188	const struct rk_gmac_ops rk3568_gmac_ops = {
1705	2189	.fix_mac_speed = rv1126_set_rgmii_speed,
1706	2190	.set_to_rgmii = rk3568_set_to_rgmii,
..	..	@@ -1774,6 +2258,16 @@
1774	2258	.data = (ulong)&rv1108_gmac_ops },
1775	2259	#endif
1776	2260	#else
	2261	+#ifdef CONFIG_ROCKCHIP_RK3528
	2262	+ { .compatible = "rockchip,rk3528-gmac",
	2263	+ .data = (ulong)&rk3528_gmac_ops },
	2264	+#endif
	2265	+
	2266	+#ifdef CONFIG_ROCKCHIP_RK3562
	2267	+ { .compatible = "rockchip,rk3562-gmac",
	2268	+ .data = (ulong)&rk3562_gmac_ops },
	2269	+#endif
	2270	+
1777	2271	#ifdef CONFIG_ROCKCHIP_RK3568
1778	2272	{ .compatible = "rockchip,rk3568-gmac",
1779	2273	.data = (ulong)&rk3568_gmac_ops },