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97 | 97 | #define SAI_DMACR_RDE(x) ((x) << 24) |
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98 | 98 | #define SAI_DMACR_RDL_MASK GENMASK(20, 16) |
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99 | 99 | #define SAI_DMACR_RDL(x) ((x - 1) << 16) |
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| 100 | +#define SAI_DMACR_RDL_V(v) ((((v) & SAI_DMACR_RDL_MASK) >> 16) + 1) |
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100 | 101 | #define SAI_DMACR_TDE_MASK BIT(8) |
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101 | 102 | #define SAI_DMACR_TDE(x) ((x) << 8) |
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102 | 103 | #define SAI_DMACR_TDL_MASK GENMASK(4, 0) |
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103 | 104 | #define SAI_DMACR_TDL(x) ((x) << 0) |
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| 105 | +#define SAI_DMACR_TDL_V(v) (((v) & SAI_DMACR_TDL_MASK) >> 0) |
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104 | 106 | |
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105 | 107 | /* INTCR Interrupt Ctrl Register */ |
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106 | 108 | #define SAI_INTCR_RXOIC BIT(18) |
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.. | .. |
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120 | 122 | #define SAI_XSHIFT_SEL_MASK GENMASK(23, 0) |
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121 | 123 | #define SAI_XSHIFT_SEL(x) (x) |
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122 | 124 | |
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| 125 | +/* XFIFOLR: Transfer / Receive FIFO Level Register */ |
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| 126 | +#define SAI_FIFOLR_XFL3_SHIFT 18 |
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| 127 | +#define SAI_FIFOLR_XFL3_MASK GENMASK(23, 18) |
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| 128 | +#define SAI_FIFOLR_XFL2_SHIFT 12 |
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| 129 | +#define SAI_FIFOLR_XFL2_MASK GENMASK(17, 12) |
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| 130 | +#define SAI_FIFOLR_XFL1_SHIFT 6 |
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| 131 | +#define SAI_FIFOLR_XFL1_MASK GENMASK(11, 6) |
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| 132 | +#define SAI_FIFOLR_XFL0_SHIFT 0 |
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| 133 | +#define SAI_FIFOLR_XFL0_MASK GENMASK(5, 0) |
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| 134 | + |
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123 | 135 | /* SAI Registers */ |
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124 | 136 | #define SAI_TXCR (0x0000) |
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125 | 137 | #define SAI_FSCR (0x0004) |
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