add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/sound/soc/codecs/rt5682.c
..
..
@@ -1,26 +1,22 @@
1
-/*
2
- * rt5682.c  --  RT5682 ALSA SoC audio component driver
3
- *
4
- * Copyright 2018 Realtek Semiconductor Corp.
5
- * Author: Bard Liao <bardliao@realtek.com>
6
- *
7
- * This program is free software; you can redistribute it and/or modify
8
- * it under the terms of the GNU General Public License version 2 as
9
- * published by the Free Software Foundation.
10
- */
1
+// SPDX-License-Identifier: GPL-2.0-only
2
+//
3
+// rt5682.c  --  RT5682 ALSA SoC audio component driver
4
+//
5
+// Copyright 2018 Realtek Semiconductor Corp.
6
+// Author: Bard Liao <bardliao@realtek.com>
7
+//
11
8
 
12
9
 #include <linux/module.h>
13
10
 #include <linux/moduleparam.h>
14
11
 #include <linux/init.h>
15
12
 #include <linux/delay.h>
16
13
 #include <linux/pm.h>
17
-#include <linux/i2c.h>
14
+#include <linux/pm_runtime.h>
18
15
 #include <linux/platform_device.h>
19
16
 #include <linux/spi/spi.h>
20
17
 #include <linux/acpi.h>
21
18
 #include <linux/gpio.h>
22
19
 #include <linux/of_gpio.h>
23
-#include <linux/regulator/consumer.h>
24
20
 #include <linux/mutex.h>
25
21
 #include <sound/core.h>
26
22
 #include <sound/pcm.h>
..
..
@@ -35,43 +31,34 @@
35
31
 #include "rl6231.h"
36
32
 #include "rt5682.h"
37
33
 
38
-#define RT5682_NUM_SUPPLIES 3
39
-
40
-static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
34
+const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
41
35
 	"AVDD",
42
36
 	"MICVDD",
43
37
 	"VBAT",
44
38
 };
45
-
46
-struct rt5682_priv {
47
-	struct snd_soc_component *component;
48
-	struct rt5682_platform_data pdata;
49
-	struct regmap *regmap;
50
-	struct snd_soc_jack *hs_jack;
51
-	struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES];
52
-	struct delayed_work jack_detect_work;
53
-	struct delayed_work jd_check_work;
54
-	struct mutex calibrate_mutex;
55
-
56
-	int sysclk;
57
-	int sysclk_src;
58
-	int lrck[RT5682_AIFS];
59
-	int bclk[RT5682_AIFS];
60
-	int master[RT5682_AIFS];
61
-
62
-	int pll_src;
63
-	int pll_in;
64
-	int pll_out;
65
-
66
-	int jack_type;
67
-};
39
+EXPORT_SYMBOL_GPL(rt5682_supply_names);
68
40
 
69
41
 static const struct reg_sequence patch_list[] = {
70
-	{0x01c1, 0x1000},
42
+	{RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
71
43
 	{RT5682_DAC_ADC_DIG_VOL1, 0xa020},
44
+	{RT5682_I2C_CTRL, 0x000f},
45
+	{RT5682_PLL2_INTERNAL, 0x8266},
46
+	{RT5682_SAR_IL_CMD_3, 0x8365},
47
+	{RT5682_SAR_IL_CMD_6, 0x0180},
72
48
 };
73
49
 
74
-static const struct reg_default rt5682_reg[] = {
50
+void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
51
+{
52
+	int ret;
53
+
54
+	ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
55
+				     ARRAY_SIZE(patch_list));
56
+	if (ret)
57
+		dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
58
+}
59
+EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
60
+
61
+const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
75
62
 	{0x0002, 0x8080},
76
63
 	{0x0003, 0x8000},
77
64
 	{0x0005, 0x0000},
..
..
@@ -216,7 +203,7 @@
216
203
 	{0x0148, 0x0000},
217
204
 	{0x0149, 0x0000},
218
205
 	{0x0150, 0x79a1},
219
-	{0x0151, 0x0000},
206
+	{0x0156, 0xaaaa},
220
207
 	{0x0160, 0x4ec0},
221
208
 	{0x0161, 0x0080},
222
209
 	{0x0162, 0x0200},
..
..
@@ -391,8 +378,9 @@
391
378
 	{0x03f2, 0x0800},
392
379
 	{0x03f3, 0x0800},
393
380
 };
381
+EXPORT_SYMBOL_GPL(rt5682_reg);
394
382
 
395
-static bool rt5682_volatile_register(struct device *dev, unsigned int reg)
383
+bool rt5682_volatile_register(struct device *dev, unsigned int reg)
396
384
 {
397
385
 	switch (reg) {
398
386
 	case RT5682_RESET:
..
..
@@ -419,8 +407,9 @@
419
407
 		return false;
420
408
 	}
421
409
 }
410
+EXPORT_SYMBOL_GPL(rt5682_volatile_register);
422
411
 
423
-static bool rt5682_readable_register(struct device *dev, unsigned int reg)
412
+bool rt5682_readable_register(struct device *dev, unsigned int reg)
424
413
 {
425
414
 	switch (reg) {
426
415
 	case RT5682_RESET:
..
..
@@ -749,8 +738,8 @@
749
738
 		return false;
750
739
 	}
751
740
 }
741
+EXPORT_SYMBOL_GPL(rt5682_readable_register);
752
742
 
753
-static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
754
743
 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
755
744
 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
756
745
 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
..
..
@@ -801,11 +790,30 @@
801
790
 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
802
791
 	SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
803
792
 
804
-static void rt5682_reset(struct regmap *regmap)
793
+static const char * const rt5682_dac_select[] = {
794
+	"IF1", "SOUND"
795
+};
796
+
797
+static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
798
+	RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
799
+
800
+static const struct snd_kcontrol_new rt5682_dac_l_mux =
801
+	SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
802
+
803
+static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
804
+	RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
805
+
806
+static const struct snd_kcontrol_new rt5682_dac_r_mux =
807
+	SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
808
+
809
+void rt5682_reset(struct rt5682_priv *rt5682)
805
810
 {
806
-	regmap_write(regmap, RT5682_RESET, 0);
807
-	regmap_write(regmap, RT5682_I2C_MODE, 1);
811
+	regmap_write(rt5682->regmap, RT5682_RESET, 0);
812
+	if (!rt5682->is_sdw)
813
+		regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
808
814
 }
815
+EXPORT_SYMBOL_GPL(rt5682_reset);
816
+
809
817
 /**
810
818
  * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
811
819
  * @component: SoC audio component device.
..
..
@@ -823,7 +831,6 @@
823
831
 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
824
832
 		unsigned int filter_mask, unsigned int clk_src)
825
833
 {
826
-
827
834
 	switch (clk_src) {
828
835
 	case RT5682_CLK_SEL_SYS:
829
836
 	case RT5682_CLK_SEL_I2S1_ASRC:
..
..
@@ -854,10 +861,10 @@
854
861
 {
855
862
 	int btn_type, val;
856
863
 
857
-	val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1);
864
+	val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
858
865
 	btn_type = val & 0xfff0;
859
866
 	snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
860
-	pr_debug("%s btn_type=%x\n", __func__, btn_type);
867
+	dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
861
868
 	snd_soc_component_update_bits(component,
862
869
 		RT5682_SAR_IL_CMD_2, 0x10, 0x10);
863
870
 
..
..
@@ -867,6 +874,8 @@
867
874
 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
868
875
 		bool enable)
869
876
 {
877
+	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
878
+
870
879
 	if (enable) {
871
880
 		snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
872
881
 			RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
..
..
@@ -876,8 +885,15 @@
876
885
 		snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
877
886
 			RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
878
887
 			RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
879
-		snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
880
-			RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN);
888
+		if (rt5682->is_sdw)
889
+			snd_soc_component_update_bits(component,
890
+				RT5682_IRQ_CTRL_3,
891
+				RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
892
+				RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
893
+		else
894
+			snd_soc_component_update_bits(component,
895
+				RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
896
+				RT5682_IL_IRQ_EN);
881
897
 	} else {
882
898
 		snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
883
899
 			RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
..
..
@@ -901,26 +917,37 @@
901
917
  *
902
918
  * Returns detect status.
903
919
  */
904
-static int rt5682_headset_detect(struct snd_soc_component *component,
905
-		int jack_insert)
920
+int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
906
921
 {
907
922
 	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
908
-	struct snd_soc_dapm_context *dapm =
909
-		snd_soc_component_get_dapm(component);
923
+	struct snd_soc_dapm_context *dapm = &component->dapm;
910
924
 	unsigned int val, count;
911
925
 
912
926
 	if (jack_insert) {
913
-		snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
914
-		snd_soc_dapm_sync(dapm);
927
+		snd_soc_dapm_mutex_lock(dapm);
928
+
929
+		snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
930
+			RT5682_PWR_VREF2 | RT5682_PWR_MB,
931
+			RT5682_PWR_VREF2 | RT5682_PWR_MB);
932
+		snd_soc_component_update_bits(component,
933
+			RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
934
+		usleep_range(15000, 20000);
935
+		snd_soc_component_update_bits(component,
936
+			RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
937
+		snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
938
+			RT5682_PWR_CBJ, RT5682_PWR_CBJ);
939
+		snd_soc_component_update_bits(component,
940
+			RT5682_HP_CHARGE_PUMP_1,
941
+			RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
915
942
 		snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
916
943
 			RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
917
944
 
918
945
 		count = 0;
919
-		val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2)
946
+		val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
920
947
 			& RT5682_JACK_TYPE_MASK;
921
948
 		while (val == 0 && count < 50) {
922
949
 			usleep_range(10000, 15000);
923
-			val = snd_soc_component_read32(component,
950
+			val = snd_soc_component_read(component,
924
951
 				RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
925
952
 			count++;
926
953
 		}
..
..
@@ -933,14 +960,37 @@
933
960
 			break;
934
961
 		default:
935
962
 			rt5682->jack_type = SND_JACK_HEADPHONE;
963
+			break;
936
964
 		}
937
965
 
966
+		snd_soc_component_update_bits(component,
967
+			RT5682_HP_CHARGE_PUMP_1,
968
+			RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
969
+			RT5682_OSW_L_EN | RT5682_OSW_R_EN);
970
+		snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
971
+			RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
972
+			RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
973
+
974
+		snd_soc_dapm_mutex_unlock(dapm);
938
975
 	} else {
939
976
 		rt5682_enable_push_button_irq(component, false);
940
977
 		snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
941
978
 			RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
942
-		snd_soc_dapm_disable_pin(dapm, "CBJ Power");
943
-		snd_soc_dapm_sync(dapm);
979
+		if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
980
+			!snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
981
+			!snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
982
+			snd_soc_component_update_bits(component,
983
+				RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
984
+		if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
985
+			!snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
986
+			!snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
987
+			snd_soc_component_update_bits(component,
988
+				RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
989
+		snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
990
+			RT5682_PWR_CBJ, 0);
991
+		snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
992
+			RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
993
+			RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
944
994
 
945
995
 		rt5682->jack_type = 0;
946
996
 	}
..
..
@@ -948,38 +998,10 @@
948
998
 	dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
949
999
 	return rt5682->jack_type;
950
1000
 }
951
-
952
-static irqreturn_t rt5682_irq(int irq, void *data)
953
-{
954
-	struct rt5682_priv *rt5682 = data;
955
-
956
-	mod_delayed_work(system_power_efficient_wq,
957
-			&rt5682->jack_detect_work, msecs_to_jiffies(250));
958
-
959
-	return IRQ_HANDLED;
960
-}
961
-
962
-static void rt5682_jd_check_handler(struct work_struct *work)
963
-{
964
-	struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv,
965
-		jd_check_work.work);
966
-
967
-	if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
968
-		& RT5682_JDH_RS_MASK) {
969
-		/* jack out */
970
-		rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
971
-
972
-		snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
973
-				SND_JACK_HEADSET |
974
-				SND_JACK_BTN_0 | SND_JACK_BTN_1 |
975
-				SND_JACK_BTN_2 | SND_JACK_BTN_3);
976
-	} else {
977
-		schedule_delayed_work(&rt5682->jd_check_work, 500);
978
-	}
979
-}
1001
+EXPORT_SYMBOL_GPL(rt5682_headset_detect);
980
1002
 
981
1003
 static int rt5682_set_jack_detect(struct snd_soc_component *component,
982
-	struct snd_soc_jack *hs_jack, void *data)
1004
+		struct snd_soc_jack *hs_jack, void *data)
983
1005
 {
984
1006
 	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
985
1007
 
..
..
@@ -987,67 +1009,89 @@
987
1009
 
988
1010
 	if (!hs_jack) {
989
1011
 		regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
990
-				   RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1012
+			RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
991
1013
 		regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
992
-				   RT5682_POW_JDH | RT5682_POW_JDL, 0);
1014
+			RT5682_POW_JDH | RT5682_POW_JDL, 0);
1015
+		cancel_delayed_work_sync(&rt5682->jack_detect_work);
1016
+
993
1017
 		return 0;
994
1018
 	}
995
1019
 
996
-	switch (rt5682->pdata.jd_src) {
997
-	case RT5682_JD1:
998
-		snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2,
999
-			RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
1000
-		snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042);
1001
-		snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3,
1002
-			RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
1003
-		snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
1004
-			RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
1005
-		regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1006
-			RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1007
-		regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1020
+	if (!rt5682->is_sdw) {
1021
+		switch (rt5682->pdata.jd_src) {
1022
+		case RT5682_JD1:
1023
+			snd_soc_component_update_bits(component,
1024
+				RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1025
+				RT5682_EXT_JD_SRC_MANUAL);
1026
+			snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1027
+				0xd042);
1028
+			snd_soc_component_update_bits(component,
1029
+				RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1030
+				RT5682_CBJ_IN_BUF_EN);
1031
+			snd_soc_component_update_bits(component,
1032
+				RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1033
+				RT5682_SAR_POW_EN);
1034
+			regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1035
+				RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1036
+			regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1008
1037
 				RT5682_POW_IRQ | RT5682_POW_JDH |
1009
1038
 				RT5682_POW_ANA, RT5682_POW_IRQ |
1010
1039
 				RT5682_POW_JDH | RT5682_POW_ANA);
1011
-		regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1012
-			RT5682_PWR_JDH | RT5682_PWR_JDL,
1013
-			RT5682_PWR_JDH | RT5682_PWR_JDL);
1014
-		regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1015
-			RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1016
-			RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1017
-		mod_delayed_work(system_power_efficient_wq,
1018
-			   &rt5682->jack_detect_work, msecs_to_jiffies(250));
1019
-		break;
1040
+			regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1041
+				RT5682_PWR_JDH, RT5682_PWR_JDH);
1042
+			regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1043
+				RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1044
+				RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1045
+			regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1046
+				0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1047
+				rt5682->pdata.btndet_delay));
1048
+			regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1049
+				0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1050
+				rt5682->pdata.btndet_delay));
1051
+			regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1052
+				0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1053
+				rt5682->pdata.btndet_delay));
1054
+			regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1055
+				0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1056
+				rt5682->pdata.btndet_delay));
1057
+			mod_delayed_work(system_power_efficient_wq,
1058
+				&rt5682->jack_detect_work,
1059
+				msecs_to_jiffies(250));
1060
+			break;
1020
1061
 
1021
-	case RT5682_JD_NULL:
1022
-		regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1023
-			RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1024
-		regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1062
+		case RT5682_JD_NULL:
1063
+			regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1064
+				RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1065
+			regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1025
1066
 				RT5682_POW_JDH | RT5682_POW_JDL, 0);
1026
-		break;
1067
+			break;
1027
1068
 
1028
-	default:
1029
-		dev_warn(component->dev, "Wrong JD source\n");
1030
-		break;
1069
+		default:
1070
+			dev_warn(component->dev, "Wrong JD source\n");
1071
+			break;
1072
+		}
1031
1073
 	}
1032
1074
 
1033
1075
 	return 0;
1034
1076
 }
1035
1077
 
1036
-static void rt5682_jack_detect_handler(struct work_struct *work)
1078
+void rt5682_jack_detect_handler(struct work_struct *work)
1037
1079
 {
1038
1080
 	struct rt5682_priv *rt5682 =
1039
1081
 		container_of(work, struct rt5682_priv, jack_detect_work.work);
1040
1082
 	int val, btn_type;
1041
1083
 
1042
-	while (!rt5682->component)
1043
-		usleep_range(10000, 15000);
1044
-
1045
-	while (!rt5682->component->card->instantiated)
1046
-		usleep_range(10000, 15000);
1084
+	if (!rt5682->component || !rt5682->component->card ||
1085
+	    !rt5682->component->card->instantiated) {
1086
+		/* card not yet ready, try later */
1087
+		mod_delayed_work(system_power_efficient_wq,
1088
+				 &rt5682->jack_detect_work, msecs_to_jiffies(15));
1089
+		return;
1090
+	}
1047
1091
 
1048
1092
 	mutex_lock(&rt5682->calibrate_mutex);
1049
1093
 
1050
-	val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
1094
+	val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
1051
1095
 		& RT5682_JDH_RS_MASK;
1052
1096
 	if (!val) {
1053
1097
 		/* jack in */
..
..
@@ -1055,7 +1099,8 @@
1055
1099
 			/* jack was out, report jack type */
1056
1100
 			rt5682->jack_type =
1057
1101
 				rt5682_headset_detect(rt5682->component, 1);
1058
-		} else {
1102
+		} else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1103
+			SND_JACK_HEADSET) {
1059
1104
 			/* jack is already in, report button event */
1060
1105
 			rt5682->jack_type = SND_JACK_HEADSET;
1061
1106
 			btn_type = rt5682_button_detect(rt5682->component);
..
..
@@ -1090,7 +1135,6 @@
1090
1135
 			case 0x0000: /* unpressed */
1091
1136
 				break;
1092
1137
 			default:
1093
-				btn_type = 0;
1094
1138
 				dev_err(rt5682->component->dev,
1095
1139
 					"Unexpected button code 0x%04x\n",
1096
1140
 					btn_type);
..
..
@@ -1103,27 +1147,26 @@
1103
1147
 	}
1104
1148
 
1105
1149
 	snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1106
-			SND_JACK_HEADSET |
1107
-			    SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1108
-			    SND_JACK_BTN_2 | SND_JACK_BTN_3);
1150
+		SND_JACK_HEADSET |
1151
+		SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1152
+		SND_JACK_BTN_2 | SND_JACK_BTN_3);
1109
1153
 
1110
-	if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1111
-		SND_JACK_BTN_2 | SND_JACK_BTN_3))
1112
-		schedule_delayed_work(&rt5682->jd_check_work, 0);
1113
-	else
1114
-		cancel_delayed_work_sync(&rt5682->jd_check_work);
1154
+	if (!rt5682->is_sdw) {
1155
+		if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1156
+			SND_JACK_BTN_2 | SND_JACK_BTN_3))
1157
+			schedule_delayed_work(&rt5682->jd_check_work, 0);
1158
+		else
1159
+			cancel_delayed_work_sync(&rt5682->jd_check_work);
1160
+	}
1115
1161
 
1116
1162
 	mutex_unlock(&rt5682->calibrate_mutex);
1117
1163
 }
1164
+EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1118
1165
 
1119
1166
 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1120
-	/* Headphone Output Volume */
1121
-	SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5682_HPL_GAIN,
1122
-		RT5682_HPR_GAIN, RT5682_G_HP_SFT, 15, 1, hp_vol_tlv),
1123
-
1124
1167
 	/* DAC Digital Volume */
1125
1168
 	SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1126
-		RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 86, 0, dac_vol_tlv),
1169
+		RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1127
1170
 
1128
1171
 	/* IN Boost Volume */
1129
1172
 	SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
..
..
@@ -1141,35 +1184,34 @@
1141
1184
 		3, 0, adc_bst_tlv),
1142
1185
 };
1143
1186
 
1144
-
1145
1187
 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1146
-			  int target, const int div[], int size)
1188
+		int target, const int div[], int size)
1147
1189
 {
1148
1190
 	int i;
1149
1191
 
1150
1192
 	if (rt5682->sysclk < target) {
1151
-		pr_err("sysclk rate %d is too low\n",
1152
-			rt5682->sysclk);
1193
+		dev_err(rt5682->component->dev,
1194
+			"sysclk rate %d is too low\n", rt5682->sysclk);
1153
1195
 		return 0;
1154
1196
 	}
1155
1197
 
1156
1198
 	for (i = 0; i < size - 1; i++) {
1157
-		pr_info("div[%d]=%d\n", i, div[i]);
1199
+		dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1158
1200
 		if (target * div[i] == rt5682->sysclk)
1159
1201
 			return i;
1160
1202
 		if (target * div[i + 1] > rt5682->sysclk) {
1161
-			pr_err("can't find div for sysclk %d\n",
1203
+			dev_dbg(rt5682->component->dev,
1204
+				"can't find div for sysclk %d\n",
1162
1205
 				rt5682->sysclk);
1163
1206
 			return i;
1164
1207
 		}
1165
1208
 	}
1166
1209
 
1167
1210
 	if (target * div[i] < rt5682->sysclk)
1168
-		pr_err("sysclk rate %d is too high\n",
1169
-			rt5682->sysclk);
1211
+		dev_err(rt5682->component->dev,
1212
+			"sysclk rate %d is too high\n", rt5682->sysclk);
1170
1213
 
1171
1214
 	return size - 1;
1172
-
1173
1215
 }
1174
1216
 
1175
1217
 /**
..
..
@@ -1183,15 +1225,18 @@
1183
1225
  * It is better for clock to approximate 3MHz.
1184
1226
  */
1185
1227
 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1186
-	struct snd_kcontrol *kcontrol, int event)
1228
+		struct snd_kcontrol *kcontrol, int event)
1187
1229
 {
1188
1230
 	struct snd_soc_component *component =
1189
1231
 		snd_soc_dapm_to_component(w->dapm);
1190
1232
 	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1191
-	int idx = -EINVAL;
1233
+	int idx = -EINVAL, dmic_clk_rate = 3072000;
1192
1234
 	static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1193
1235
 
1194
-	idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div));
1236
+	if (rt5682->pdata.dmic_clk_rate)
1237
+		dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1238
+
1239
+	idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1195
1240
 
1196
1241
 	snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1197
1242
 		RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
..
..
@@ -1200,7 +1245,7 @@
1200
1245
 }
1201
1246
 
1202
1247
 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1203
-	struct snd_kcontrol *kcontrol, int event)
1248
+		struct snd_kcontrol *kcontrol, int event)
1204
1249
 {
1205
1250
 	struct snd_soc_component *component =
1206
1251
 		snd_soc_dapm_to_component(w->dapm);
..
..
@@ -1209,7 +1254,10 @@
1209
1254
 	static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1210
1255
 	static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1211
1256
 
1212
-	val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) &
1257
+	if (rt5682->is_sdw)
1258
+		return 0;
1259
+
1260
+	val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1213
1261
 		RT5682_GP4_PIN_MASK;
1214
1262
 	if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1215
1263
 		val == RT5682_GP4_PIN_ADCDAT2)
..
..
@@ -1241,13 +1289,13 @@
1241
1289
 }
1242
1290
 
1243
1291
 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1244
-			 struct snd_soc_dapm_widget *sink)
1292
+		struct snd_soc_dapm_widget *sink)
1245
1293
 {
1246
1294
 	unsigned int val;
1247
1295
 	struct snd_soc_component *component =
1248
1296
 		snd_soc_dapm_to_component(w->dapm);
1249
1297
 
1250
-	val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1298
+	val = snd_soc_component_read(component, RT5682_GLB_CLK);
1251
1299
 	val &= RT5682_SCLK_SRC_MASK;
1252
1300
 	if (val == RT5682_SCLK_SRC_PLL1)
1253
1301
 		return 1;
..
..
@@ -1255,8 +1303,23 @@
1255
1303
 		return 0;
1256
1304
 }
1257
1305
 
1306
+static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1307
+		struct snd_soc_dapm_widget *sink)
1308
+{
1309
+	unsigned int val;
1310
+	struct snd_soc_component *component =
1311
+		snd_soc_dapm_to_component(w->dapm);
1312
+
1313
+	val = snd_soc_component_read(component, RT5682_GLB_CLK);
1314
+	val &= RT5682_SCLK_SRC_MASK;
1315
+	if (val == RT5682_SCLK_SRC_PLL2)
1316
+		return 1;
1317
+	else
1318
+		return 0;
1319
+}
1320
+
1258
1321
 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1259
-			 struct snd_soc_dapm_widget *sink)
1322
+		struct snd_soc_dapm_widget *sink)
1260
1323
 {
1261
1324
 	unsigned int reg, shift, val;
1262
1325
 	struct snd_soc_component *component =
..
..
@@ -1275,7 +1338,7 @@
1275
1338
 		return 0;
1276
1339
 	}
1277
1340
 
1278
-	val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1341
+	val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1279
1342
 	switch (val) {
1280
1343
 	case RT5682_CLK_SEL_I2S1_ASRC:
1281
1344
 	case RT5682_CLK_SEL_I2S2_ASRC:
..
..
@@ -1283,7 +1346,6 @@
1283
1346
 	default:
1284
1347
 		return 0;
1285
1348
 	}
1286
-
1287
1349
 }
1288
1350
 
1289
1351
 /* Digital Mixer */
..
..
@@ -1437,13 +1499,13 @@
1437
1499
 /* Out Switch */
1438
1500
 static const struct snd_kcontrol_new hpol_switch =
1439
1501
 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1440
-					RT5682_L_MUTE_SFT, 1, 1);
1502
+		RT5682_L_MUTE_SFT, 1, 1);
1441
1503
 static const struct snd_kcontrol_new hpor_switch =
1442
1504
 	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1443
-					RT5682_R_MUTE_SFT, 1, 1);
1505
+		RT5682_R_MUTE_SFT, 1, 1);
1444
1506
 
1445
1507
 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1446
-	struct snd_kcontrol *kcontrol, int event)
1508
+		struct snd_kcontrol *kcontrol, int event)
1447
1509
 {
1448
1510
 	struct snd_soc_component *component =
1449
1511
 		snd_soc_dapm_to_component(w->dapm);
..
..
@@ -1454,8 +1516,6 @@
1454
1516
 			RT5682_HP_LOGIC_CTRL_2, 0x0012);
1455
1517
 		snd_soc_component_write(component,
1456
1518
 			RT5682_HP_CTRL_2, 0x6000);
1457
-		snd_soc_component_update_bits(component, RT5682_STO_NG2_CTRL_1,
1458
-			RT5682_NG2_EN_MASK, RT5682_NG2_EN);
1459
1519
 		snd_soc_component_update_bits(component,
1460
1520
 			RT5682_DEPOP_1, 0x60, 0x60);
1461
1521
 		snd_soc_component_update_bits(component,
..
..
@@ -1470,33 +1530,53 @@
1470
1530
 		snd_soc_component_update_bits(component,
1471
1531
 			RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1472
1532
 		break;
1473
-
1474
-	default:
1475
-		return 0;
1476
1533
 	}
1477
1534
 
1478
1535
 	return 0;
1479
-
1480
1536
 }
1481
1537
 
1482
1538
 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1483
-	struct snd_kcontrol *kcontrol, int event)
1539
+		struct snd_kcontrol *kcontrol, int event)
1484
1540
 {
1541
+	struct snd_soc_component *component =
1542
+		snd_soc_dapm_to_component(w->dapm);
1543
+	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1544
+	unsigned int delay = 50, val;
1545
+
1546
+	if (rt5682->pdata.dmic_delay)
1547
+		delay = rt5682->pdata.dmic_delay;
1548
+
1485
1549
 	switch (event) {
1486
1550
 	case SND_SOC_DAPM_POST_PMU:
1551
+		val = snd_soc_component_read(component, RT5682_GLB_CLK);
1552
+		val &= RT5682_SCLK_SRC_MASK;
1553
+		if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1554
+			snd_soc_component_update_bits(component,
1555
+				RT5682_PWR_ANLG_1,
1556
+				RT5682_PWR_VREF2 | RT5682_PWR_MB,
1557
+				RT5682_PWR_VREF2 | RT5682_PWR_MB);
1558
+
1487
1559
 		/*Add delay to avoid pop noise*/
1488
-		msleep(150);
1560
+		msleep(delay);
1489
1561
 		break;
1490
1562
 
1491
-	default:
1492
-		return 0;
1563
+	case SND_SOC_DAPM_POST_PMD:
1564
+		if (!rt5682->jack_type) {
1565
+			if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1566
+				snd_soc_component_update_bits(component,
1567
+					RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
1568
+			if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1569
+				snd_soc_component_update_bits(component,
1570
+					RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
1571
+		}
1572
+		break;
1493
1573
 	}
1494
1574
 
1495
1575
 	return 0;
1496
1576
 }
1497
1577
 
1498
-static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1499
-	struct snd_kcontrol *kcontrol, int event)
1578
+static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1579
+		struct snd_kcontrol *kcontrol, int event)
1500
1580
 {
1501
1581
 	struct snd_soc_component *component =
1502
1582
 		snd_soc_dapm_to_component(w->dapm);
..
..
@@ -1512,9 +1592,6 @@
1512
1592
 		case RT5682_PWR_VREF2_BIT:
1513
1593
 			snd_soc_component_update_bits(component,
1514
1594
 				RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1515
-			break;
1516
-
1517
-		default:
1518
1595
 			break;
1519
1596
 		}
1520
1597
 		break;
..
..
@@ -1533,14 +1610,8 @@
1533
1610
 				RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1534
1611
 				RT5682_PWR_FV2);
1535
1612
 			break;
1536
-
1537
-		default:
1538
-			break;
1539
1613
 		}
1540
1614
 		break;
1541
-
1542
-	default:
1543
-		return 0;
1544
1615
 	}
1545
1616
 
1546
1617
 	return 0;
..
..
@@ -1571,11 +1642,11 @@
1571
1642
 	SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1572
1643
 		0, NULL, 0),
1573
1644
 	SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1574
-		0, NULL, 0),
1645
+		0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1575
1646
 	SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1576
-		rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1577
-	SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0,
1578
-		rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1647
+		rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1648
+	SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1649
+	SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1579
1650
 
1580
1651
 	/* ASRC */
1581
1652
 	SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
..
..
@@ -1604,14 +1675,12 @@
1604
1675
 	SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1605
1676
 		set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1606
1677
 	SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1607
-		RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1678
+		RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1679
+		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1608
1680
 
1609
1681
 	/* Boost */
1610
1682
 	SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1611
1683
 		0, 0, NULL, 0),
1612
-
1613
-	SND_SOC_DAPM_SUPPLY("CBJ Power", RT5682_PWR_ANLG_3,
1614
-		RT5682_PWR_CBJ_BIT, 0, NULL, 0),
1615
1684
 
1616
1685
 	/* REC Mixer */
1617
1686
 	SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
..
..
@@ -1670,21 +1739,28 @@
1670
1739
 	SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1671
1740
 	SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1672
1741
 	SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1742
+	SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1743
+	SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1673
1744
 
1674
1745
 	/* Digital Interface Select */
1675
1746
 	SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1676
-			&rt5682_if1_01_adc_swap_mux),
1747
+		&rt5682_if1_01_adc_swap_mux),
1677
1748
 	SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1678
-			&rt5682_if1_23_adc_swap_mux),
1749
+		&rt5682_if1_23_adc_swap_mux),
1679
1750
 	SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1680
-			&rt5682_if1_45_adc_swap_mux),
1751
+		&rt5682_if1_45_adc_swap_mux),
1681
1752
 	SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1682
-			&rt5682_if1_67_adc_swap_mux),
1753
+		&rt5682_if1_67_adc_swap_mux),
1683
1754
 	SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1684
-			&rt5682_if2_adc_swap_mux),
1755
+		&rt5682_if2_adc_swap_mux),
1685
1756
 
1686
1757
 	SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1687
-			&rt5682_adcdat_pin_ctrl),
1758
+		&rt5682_adcdat_pin_ctrl),
1759
+
1760
+	SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1761
+		&rt5682_dac_l_mux),
1762
+	SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1763
+		&rt5682_dac_r_mux),
1688
1764
 
1689
1765
 	/* Audio Interface */
1690
1766
 	SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
..
..
@@ -1692,6 +1768,8 @@
1692
1768
 	SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1693
1769
 		RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1694
1770
 	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1771
+	SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1772
+	SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1695
1773
 
1696
1774
 	/* Output Side */
1697
1775
 	/* DAC mixer before sound effect  */
..
..
@@ -1754,13 +1832,16 @@
1754
1832
 	/* Output Lines */
1755
1833
 	SND_SOC_DAPM_OUTPUT("HPOL"),
1756
1834
 	SND_SOC_DAPM_OUTPUT("HPOR"),
1757
-
1758
1835
 };
1759
1836
 
1760
1837
 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1761
1838
 	/*PLL*/
1762
1839
 	{"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1840
+	{"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1841
+	{"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1763
1842
 	{"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1843
+	{"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1844
+	{"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1764
1845
 
1765
1846
 	/*ASRC*/
1766
1847
 	{"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
..
..
@@ -1774,17 +1855,13 @@
1774
1855
 
1775
1856
 	/*Vref*/
1776
1857
 	{"MICBIAS1", NULL, "Vref1"},
1777
-	{"MICBIAS1", NULL, "Vref2"},
1778
1858
 	{"MICBIAS2", NULL, "Vref1"},
1779
-	{"MICBIAS2", NULL, "Vref2"},
1780
1859
 
1781
1860
 	{"CLKDET SYS", NULL, "CLKDET"},
1782
1861
 
1783
1862
 	{"IN1P", NULL, "LDO2"},
1784
1863
 
1785
1864
 	{"BST1 CBJ", NULL, "IN1P"},
1786
-	{"BST1 CBJ", NULL, "CBJ Power"},
1787
-	{"CBJ Power", NULL, "Vref2"},
1788
1865
 
1789
1866
 	{"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1790
1867
 	{"RECMIX1L", NULL, "RECMIX1L Power"},
..
..
@@ -1848,8 +1925,8 @@
1848
1925
 	{"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1849
1926
 	{"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1850
1927
 	{"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1851
-	{"IF1_ADC Mux", NULL, "I2S1"},
1852
1928
 	{"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1929
+	{"AIF1TX", NULL, "I2S1"},
1853
1930
 	{"AIF1TX", NULL, "ADCDAT Mux"},
1854
1931
 	{"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1855
1932
 	{"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
..
..
@@ -1858,6 +1935,10 @@
1858
1935
 	{"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1859
1936
 	{"AIF2TX", NULL, "ADCDAT Mux"},
1860
1937
 
1938
+	{"SDWTX", NULL, "PLL2B"},
1939
+	{"SDWTX", NULL, "PLL2F"},
1940
+	{"SDWTX", NULL, "ADCDAT Mux"},
1941
+
1861
1942
 	{"IF1 DAC1 L", NULL, "AIF1RX"},
1862
1943
 	{"IF1 DAC1 L", NULL, "I2S1"},
1863
1944
 	{"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
..
..
@@ -1865,10 +1946,24 @@
1865
1946
 	{"IF1 DAC1 R", NULL, "I2S1"},
1866
1947
 	{"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1867
1948
 
1949
+	{"SOUND DAC L", NULL, "SDWRX"},
1950
+	{"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
1951
+	{"SOUND DAC L", NULL, "PLL2B"},
1952
+	{"SOUND DAC L", NULL, "PLL2F"},
1953
+	{"SOUND DAC R", NULL, "SDWRX"},
1954
+	{"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
1955
+	{"SOUND DAC R", NULL, "PLL2B"},
1956
+	{"SOUND DAC R", NULL, "PLL2F"},
1957
+
1958
+	{"DAC L Mux", "IF1", "IF1 DAC1 L"},
1959
+	{"DAC L Mux", "SOUND", "SOUND DAC L"},
1960
+	{"DAC R Mux", "IF1", "IF1 DAC1 R"},
1961
+	{"DAC R Mux", "SOUND", "SOUND DAC R"},
1962
+
1868
1963
 	{"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1869
-	{"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1964
+	{"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
1870
1965
 	{"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1871
-	{"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1966
+	{"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
1872
1967
 
1873
1968
 	{"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1874
1969
 	{"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
..
..
@@ -1894,8 +1989,7 @@
1894
1989
 	{"HP Amp", NULL, "Capless"},
1895
1990
 	{"HP Amp", NULL, "Charge Pump"},
1896
1991
 	{"HP Amp", NULL, "CLKDET SYS"},
1897
-	{"HP Amp", NULL, "CBJ Power"},
1898
-	{"HP Amp", NULL, "Vref2"},
1992
+	{"HP Amp", NULL, "Vref1"},
1899
1993
 	{"HPOL Playback", "Switch", "HP Amp"},
1900
1994
 	{"HPOR Playback", "Switch", "HP Amp"},
1901
1995
 	{"HPOL", NULL, "HPOL Playback"},
..
..
@@ -1903,7 +1997,7 @@
1903
1997
 };
1904
1998
 
1905
1999
 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1906
-			unsigned int rx_mask, int slots, int slot_width)
2000
+		unsigned int rx_mask, int slots, int slot_width)
1907
2001
 {
1908
2002
 	struct snd_soc_component *component = dai->component;
1909
2003
 	unsigned int cl, val = 0;
..
..
@@ -1971,9 +2065,8 @@
1971
2065
 	return 0;
1972
2066
 }
1973
2067
 
1974
-
1975
2068
 static int rt5682_hw_params(struct snd_pcm_substream *substream,
1976
-	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2069
+		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1977
2070
 {
1978
2071
 	struct snd_soc_component *component = dai->component;
1979
2072
 	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
..
..
@@ -1991,7 +2084,7 @@
1991
2084
 	}
1992
2085
 
1993
2086
 	dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
1994
-				rt5682->lrck[dai->id], pre_div, dai->id);
2087
+		rt5682->lrck[dai->id], pre_div, dai->id);
1995
2088
 
1996
2089
 	switch (params_width(params)) {
1997
2090
 	case 16:
..
..
@@ -2022,8 +2115,10 @@
2022
2115
 			RT5682_I2S1_DL_MASK, len_1);
2023
2116
 		if (rt5682->master[RT5682_AIF1]) {
2024
2117
 			snd_soc_component_update_bits(component,
2025
-				RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK,
2026
-				pre_div << RT5682_I2S_M_DIV_SFT);
2118
+				RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2119
+				RT5682_I2S_CLK_SRC_MASK,
2120
+				pre_div << RT5682_I2S_M_DIV_SFT |
2121
+				(rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2027
2122
 		}
2028
2123
 		if (params_channels(params) == 1) /* mono mode */
2029
2124
 			snd_soc_component_update_bits(component,
..
..
@@ -2196,61 +2291,164 @@
2196
2291
 		unsigned int freq_out)
2197
2292
 {
2198
2293
 	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2199
-	struct rl6231_pll_code pll_code;
2294
+	struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2295
+	unsigned int pll2_fout1, pll2_ps_val;
2200
2296
 	int ret;
2201
2297
 
2202
-	if (source == rt5682->pll_src && freq_in == rt5682->pll_in &&
2203
-	    freq_out == rt5682->pll_out)
2298
+	if (source == rt5682->pll_src[pll_id] &&
2299
+	    freq_in == rt5682->pll_in[pll_id] &&
2300
+	    freq_out == rt5682->pll_out[pll_id])
2204
2301
 		return 0;
2205
2302
 
2206
2303
 	if (!freq_in || !freq_out) {
2207
2304
 		dev_dbg(component->dev, "PLL disabled\n");
2208
2305
 
2209
-		rt5682->pll_in = 0;
2210
-		rt5682->pll_out = 0;
2306
+		rt5682->pll_in[pll_id] = 0;
2307
+		rt5682->pll_out[pll_id] = 0;
2211
2308
 		snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2212
2309
 			RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2213
2310
 		return 0;
2214
2311
 	}
2215
2312
 
2216
-	switch (source) {
2217
-	case RT5682_PLL1_S_MCLK:
2218
-		snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2219
-			RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK);
2220
-		break;
2221
-	case RT5682_PLL1_S_BCLK1:
2222
-		snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2223
-				RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1);
2224
-		break;
2225
-	default:
2226
-		dev_err(component->dev, "Unknown PLL Source %d\n", source);
2227
-		return -EINVAL;
2313
+	if (pll_id == RT5682_PLL2) {
2314
+		switch (source) {
2315
+		case RT5682_PLL2_S_MCLK:
2316
+			snd_soc_component_update_bits(component,
2317
+				RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2318
+				RT5682_PLL2_SRC_MCLK);
2319
+			break;
2320
+		default:
2321
+			dev_err(component->dev, "Unknown PLL2 Source %d\n",
2322
+				source);
2323
+			return -EINVAL;
2324
+		}
2325
+
2326
+		/**
2327
+		 * PLL2 concatenates 2 PLL units.
2328
+		 * We suggest the Fout of the front PLL is 3.84MHz.
2329
+		 */
2330
+		pll2_fout1 = 3840000;
2331
+		ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2332
+		if (ret < 0) {
2333
+			dev_err(component->dev, "Unsupport input clock %d\n",
2334
+				freq_in);
2335
+			return ret;
2336
+		}
2337
+		dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2338
+			freq_in, pll2_fout1,
2339
+			pll2f_code.m_bp,
2340
+			(pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2341
+			pll2f_code.n_code, pll2f_code.k_code);
2342
+
2343
+		ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2344
+		if (ret < 0) {
2345
+			dev_err(component->dev, "Unsupport input clock %d\n",
2346
+				pll2_fout1);
2347
+			return ret;
2348
+		}
2349
+		dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2350
+			pll2_fout1, freq_out,
2351
+			pll2b_code.m_bp,
2352
+			(pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2353
+			pll2b_code.n_code, pll2b_code.k_code);
2354
+
2355
+		snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2356
+			pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2357
+			pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2358
+			pll2b_code.m_code);
2359
+		snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2360
+			pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2361
+			pll2b_code.n_code);
2362
+		snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2363
+			pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2364
+
2365
+		if (freq_out == 22579200)
2366
+			pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2367
+		else
2368
+			pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2369
+		snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2370
+			RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2371
+			RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2372
+			pll2_ps_val |
2373
+			(pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2374
+			(pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2375
+			0xf);
2376
+	} else {
2377
+		switch (source) {
2378
+		case RT5682_PLL1_S_MCLK:
2379
+			snd_soc_component_update_bits(component,
2380
+				RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2381
+				RT5682_PLL1_SRC_MCLK);
2382
+			break;
2383
+		case RT5682_PLL1_S_BCLK1:
2384
+			snd_soc_component_update_bits(component,
2385
+				RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2386
+				RT5682_PLL1_SRC_BCLK1);
2387
+			break;
2388
+		default:
2389
+			dev_err(component->dev, "Unknown PLL1 Source %d\n",
2390
+				source);
2391
+			return -EINVAL;
2392
+		}
2393
+
2394
+		ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2395
+		if (ret < 0) {
2396
+			dev_err(component->dev, "Unsupport input clock %d\n",
2397
+				freq_in);
2398
+			return ret;
2399
+		}
2400
+
2401
+		dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2402
+			pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2403
+			pll_code.n_code, pll_code.k_code);
2404
+
2405
+		snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2406
+			pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2407
+		snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2408
+		    (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2409
+		    pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2228
2410
 	}
2229
2411
 
2230
-	ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2231
-	if (ret < 0) {
2232
-		dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2233
-		return ret;
2234
-	}
2235
-
2236
-	dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2237
-		pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2238
-		pll_code.n_code, pll_code.k_code);
2239
-
2240
-	snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2241
-		pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2242
-	snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2243
-		(pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2244
-		pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2245
-
2246
-	rt5682->pll_in = freq_in;
2247
-	rt5682->pll_out = freq_out;
2248
-	rt5682->pll_src = source;
2412
+	rt5682->pll_in[pll_id] = freq_in;
2413
+	rt5682->pll_out[pll_id] = freq_out;
2414
+	rt5682->pll_src[pll_id] = source;
2249
2415
 
2250
2416
 	return 0;
2251
2417
 }
2252
2418
 
2253
-static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2419
+static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2420
+{
2421
+	struct snd_soc_component *component = dai->component;
2422
+	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2423
+
2424
+	rt5682->bclk[dai->id] = ratio;
2425
+
2426
+	switch (ratio) {
2427
+	case 256:
2428
+		snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2429
+			RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2430
+		break;
2431
+	case 128:
2432
+		snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2433
+			RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2434
+		break;
2435
+	case 64:
2436
+		snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2437
+			RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2438
+		break;
2439
+	case 32:
2440
+		snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2441
+			RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2442
+		break;
2443
+	default:
2444
+		dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2445
+		return -EINVAL;
2446
+	}
2447
+
2448
+	return 0;
2449
+}
2450
+
2451
+static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2254
2452
 {
2255
2453
 	struct snd_soc_component *component = dai->component;
2256
2454
 	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
..
..
@@ -2269,7 +2467,7 @@
2269
2467
 			RT5682_I2S2_BCLK_MS2_32);
2270
2468
 		break;
2271
2469
 	default:
2272
-		dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2470
+		dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2273
2471
 		return -EINVAL;
2274
2472
 	}
2275
2473
 
..
..
@@ -2277,23 +2475,20 @@
2277
2475
 }
2278
2476
 
2279
2477
 static int rt5682_set_bias_level(struct snd_soc_component *component,
2280
-			enum snd_soc_bias_level level)
2478
+		enum snd_soc_bias_level level)
2281
2479
 {
2282
2480
 	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2283
2481
 
2284
2482
 	switch (level) {
2285
2483
 	case SND_SOC_BIAS_PREPARE:
2286
2484
 		regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2287
-			RT5682_PWR_MB | RT5682_PWR_BG,
2288
-			RT5682_PWR_MB | RT5682_PWR_BG);
2485
+			RT5682_PWR_BG, RT5682_PWR_BG);
2289
2486
 		regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2290
2487
 			RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2291
2488
 			RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2292
2489
 		break;
2293
2490
 
2294
2491
 	case SND_SOC_BIAS_STANDBY:
2295
-		regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2296
-			RT5682_PWR_MB, RT5682_PWR_MB);
2297
2492
 		regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2298
2493
 			RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2299
2494
 		break;
..
..
@@ -2301,22 +2496,414 @@
2301
2496
 		regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2302
2497
 			RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2303
2498
 		regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2304
-			RT5682_PWR_MB | RT5682_PWR_BG, 0);
2499
+			RT5682_PWR_BG, 0);
2305
2500
 		break;
2306
-
2307
-	default:
2501
+	case SND_SOC_BIAS_ON:
2308
2502
 		break;
2309
2503
 	}
2310
2504
 
2311
2505
 	return 0;
2312
2506
 }
2313
2507
 
2508
+#ifdef CONFIG_COMMON_CLK
2509
+#define CLK_PLL2_FIN 48000000
2510
+#define CLK_48 48000
2511
+#define CLK_44 44100
2512
+
2513
+static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2514
+{
2515
+	if (!rt5682->master[RT5682_AIF1]) {
2516
+		dev_dbg(rt5682->component->dev, "sysclk/dai not set correctly\n");
2517
+		return false;
2518
+	}
2519
+	return true;
2520
+}
2521
+
2522
+static int rt5682_wclk_prepare(struct clk_hw *hw)
2523
+{
2524
+	struct rt5682_priv *rt5682 =
2525
+		container_of(hw, struct rt5682_priv,
2526
+			     dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2527
+	struct snd_soc_component *component = rt5682->component;
2528
+	struct snd_soc_dapm_context *dapm =
2529
+			snd_soc_component_get_dapm(component);
2530
+
2531
+	if (!rt5682_clk_check(rt5682))
2532
+		return -EINVAL;
2533
+
2534
+	snd_soc_dapm_mutex_lock(dapm);
2535
+
2536
+	snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2537
+	snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2538
+				RT5682_PWR_MB, RT5682_PWR_MB);
2539
+
2540
+	snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2541
+	snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2542
+			RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2543
+			RT5682_PWR_VREF2);
2544
+	usleep_range(55000, 60000);
2545
+	snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2546
+			RT5682_PWR_FV2, RT5682_PWR_FV2);
2547
+
2548
+	snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2549
+	snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2550
+	snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2551
+	snd_soc_dapm_sync_unlocked(dapm);
2552
+
2553
+	snd_soc_dapm_mutex_unlock(dapm);
2554
+
2555
+	return 0;
2556
+}
2557
+
2558
+static void rt5682_wclk_unprepare(struct clk_hw *hw)
2559
+{
2560
+	struct rt5682_priv *rt5682 =
2561
+		container_of(hw, struct rt5682_priv,
2562
+			     dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2563
+	struct snd_soc_component *component = rt5682->component;
2564
+	struct snd_soc_dapm_context *dapm =
2565
+			snd_soc_component_get_dapm(component);
2566
+
2567
+	if (!rt5682_clk_check(rt5682))
2568
+		return;
2569
+
2570
+	snd_soc_dapm_mutex_lock(dapm);
2571
+
2572
+	snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2573
+	snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2574
+	if (!rt5682->jack_type)
2575
+		snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2576
+				RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2577
+				RT5682_PWR_MB, 0);
2578
+
2579
+	snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2580
+	snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2581
+	snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2582
+	snd_soc_dapm_sync_unlocked(dapm);
2583
+
2584
+	snd_soc_dapm_mutex_unlock(dapm);
2585
+}
2586
+
2587
+static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2588
+					     unsigned long parent_rate)
2589
+{
2590
+	struct rt5682_priv *rt5682 =
2591
+		container_of(hw, struct rt5682_priv,
2592
+			     dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2593
+	struct snd_soc_component *component = rt5682->component;
2594
+	const char * const clk_name = clk_hw_get_name(hw);
2595
+
2596
+	if (!rt5682_clk_check(rt5682))
2597
+		return 0;
2598
+	/*
2599
+	 * Only accept to set wclk rate to 44.1k or 48kHz.
2600
+	 */
2601
+	if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2602
+	    rt5682->lrck[RT5682_AIF1] != CLK_44) {
2603
+		dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2604
+			__func__, clk_name, CLK_44, CLK_48);
2605
+		return 0;
2606
+	}
2607
+
2608
+	return rt5682->lrck[RT5682_AIF1];
2609
+}
2610
+
2611
+static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2612
+				   unsigned long *parent_rate)
2613
+{
2614
+	struct rt5682_priv *rt5682 =
2615
+		container_of(hw, struct rt5682_priv,
2616
+			     dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2617
+	struct snd_soc_component *component = rt5682->component;
2618
+	const char * const clk_name = clk_hw_get_name(hw);
2619
+
2620
+	if (!rt5682_clk_check(rt5682))
2621
+		return -EINVAL;
2622
+	/*
2623
+	 * Only accept to set wclk rate to 44.1k or 48kHz.
2624
+	 * It will force to 48kHz if not both.
2625
+	 */
2626
+	if (rate != CLK_48 && rate != CLK_44) {
2627
+		dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2628
+			__func__, clk_name, CLK_44, CLK_48);
2629
+		rate = CLK_48;
2630
+	}
2631
+
2632
+	return rate;
2633
+}
2634
+
2635
+static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2636
+				unsigned long parent_rate)
2637
+{
2638
+	struct rt5682_priv *rt5682 =
2639
+		container_of(hw, struct rt5682_priv,
2640
+			     dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2641
+	struct snd_soc_component *component = rt5682->component;
2642
+	struct clk *parent_clk;
2643
+	const char * const clk_name = clk_hw_get_name(hw);
2644
+	int pre_div;
2645
+	unsigned int clk_pll2_out;
2646
+
2647
+	if (!rt5682_clk_check(rt5682))
2648
+		return -EINVAL;
2649
+
2650
+	/*
2651
+	 * Whether the wclk's parent clk (mclk) exists or not, please ensure
2652
+	 * it is fixed or set to 48MHz before setting wclk rate. It's a
2653
+	 * temporary limitation. Only accept 48MHz clk as the clk provider.
2654
+	 *
2655
+	 * It will set the codec anyway by assuming mclk is 48MHz.
2656
+	 */
2657
+	parent_clk = clk_get_parent(hw->clk);
2658
+	if (!parent_clk)
2659
+		dev_warn(component->dev,
2660
+			"Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2661
+			CLK_PLL2_FIN);
2662
+
2663
+	if (parent_rate != CLK_PLL2_FIN)
2664
+		dev_warn(component->dev, "clk %s only support %d Hz input\n",
2665
+			clk_name, CLK_PLL2_FIN);
2666
+
2667
+	/*
2668
+	 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2669
+	 * PLL2 is needed.
2670
+	 */
2671
+	clk_pll2_out = rate * 512;
2672
+	rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2673
+		CLK_PLL2_FIN, clk_pll2_out);
2674
+
2675
+	rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2676
+		clk_pll2_out, SND_SOC_CLOCK_IN);
2677
+
2678
+	rt5682->lrck[RT5682_AIF1] = rate;
2679
+
2680
+	pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2681
+
2682
+	snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2683
+		RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2684
+		pre_div << RT5682_I2S_M_DIV_SFT |
2685
+		(rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2686
+
2687
+	return 0;
2688
+}
2689
+
2690
+static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2691
+					     unsigned long parent_rate)
2692
+{
2693
+	struct rt5682_priv *rt5682 =
2694
+		container_of(hw, struct rt5682_priv,
2695
+			     dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2696
+	struct snd_soc_component *component = rt5682->component;
2697
+	unsigned int bclks_per_wclk;
2698
+
2699
+	bclks_per_wclk = snd_soc_component_read(component, RT5682_TDM_TCON_CTRL);
2700
+
2701
+	switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2702
+	case RT5682_TDM_BCLK_MS1_256:
2703
+		return parent_rate * 256;
2704
+	case RT5682_TDM_BCLK_MS1_128:
2705
+		return parent_rate * 128;
2706
+	case RT5682_TDM_BCLK_MS1_64:
2707
+		return parent_rate * 64;
2708
+	case RT5682_TDM_BCLK_MS1_32:
2709
+		return parent_rate * 32;
2710
+	default:
2711
+		return 0;
2712
+	}
2713
+}
2714
+
2715
+static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2716
+					    unsigned long parent_rate)
2717
+{
2718
+	unsigned long factor;
2719
+
2720
+	factor = rate / parent_rate;
2721
+	if (factor < 64)
2722
+		return 32;
2723
+	else if (factor < 128)
2724
+		return 64;
2725
+	else if (factor < 256)
2726
+		return 128;
2727
+	else
2728
+		return 256;
2729
+}
2730
+
2731
+static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2732
+				   unsigned long *parent_rate)
2733
+{
2734
+	struct rt5682_priv *rt5682 =
2735
+		container_of(hw, struct rt5682_priv,
2736
+			     dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2737
+	unsigned long factor;
2738
+
2739
+	if (!*parent_rate || !rt5682_clk_check(rt5682))
2740
+		return -EINVAL;
2741
+
2742
+	/*
2743
+	 * BCLK rates are set as a multiplier of WCLK in HW.
2744
+	 * We don't allow changing the parent WCLK. We just do
2745
+	 * some rounding down based on the parent WCLK rate
2746
+	 * and find the appropriate multiplier of BCLK to
2747
+	 * get the rounded down BCLK value.
2748
+	 */
2749
+	factor = rt5682_bclk_get_factor(rate, *parent_rate);
2750
+
2751
+	return *parent_rate * factor;
2752
+}
2753
+
2754
+static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2755
+				unsigned long parent_rate)
2756
+{
2757
+	struct rt5682_priv *rt5682 =
2758
+		container_of(hw, struct rt5682_priv,
2759
+			     dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2760
+	struct snd_soc_component *component = rt5682->component;
2761
+	struct snd_soc_dai *dai = NULL;
2762
+	unsigned long factor;
2763
+
2764
+	if (!rt5682_clk_check(rt5682))
2765
+		return -EINVAL;
2766
+
2767
+	factor = rt5682_bclk_get_factor(rate, parent_rate);
2768
+
2769
+	for_each_component_dais(component, dai)
2770
+		if (dai->id == RT5682_AIF1)
2771
+			break;
2772
+	if (!dai) {
2773
+		dev_err(component->dev, "dai %d not found in component\n",
2774
+			RT5682_AIF1);
2775
+		return -ENODEV;
2776
+	}
2777
+
2778
+	return rt5682_set_bclk1_ratio(dai, factor);
2779
+}
2780
+
2781
+static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2782
+	[RT5682_DAI_WCLK_IDX] = {
2783
+		.prepare = rt5682_wclk_prepare,
2784
+		.unprepare = rt5682_wclk_unprepare,
2785
+		.recalc_rate = rt5682_wclk_recalc_rate,
2786
+		.round_rate = rt5682_wclk_round_rate,
2787
+		.set_rate = rt5682_wclk_set_rate,
2788
+	},
2789
+	[RT5682_DAI_BCLK_IDX] = {
2790
+		.recalc_rate = rt5682_bclk_recalc_rate,
2791
+		.round_rate = rt5682_bclk_round_rate,
2792
+		.set_rate = rt5682_bclk_set_rate,
2793
+	},
2794
+};
2795
+
2796
+static int rt5682_register_dai_clks(struct snd_soc_component *component)
2797
+{
2798
+	struct device *dev = component->dev;
2799
+	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2800
+	struct rt5682_platform_data *pdata = &rt5682->pdata;
2801
+	struct clk_hw *dai_clk_hw;
2802
+	int i, ret;
2803
+
2804
+	for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2805
+		struct clk_init_data init = { };
2806
+		struct clk_parent_data parent_data;
2807
+		const struct clk_hw *parent;
2808
+
2809
+		dai_clk_hw = &rt5682->dai_clks_hw[i];
2810
+
2811
+		switch (i) {
2812
+		case RT5682_DAI_WCLK_IDX:
2813
+			/* Make MCLK the parent of WCLK */
2814
+			if (rt5682->mclk) {
2815
+				parent_data = (struct clk_parent_data){
2816
+					.fw_name = "mclk",
2817
+				};
2818
+				init.parent_data = &parent_data;
2819
+				init.num_parents = 1;
2820
+			}
2821
+			break;
2822
+		case RT5682_DAI_BCLK_IDX:
2823
+			/* Make WCLK the parent of BCLK */
2824
+			parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX];
2825
+			init.parent_hws = &parent;
2826
+			init.num_parents = 1;
2827
+			break;
2828
+		default:
2829
+			dev_err(dev, "Invalid clock index\n");
2830
+			return -EINVAL;
2831
+		}
2832
+
2833
+		init.name = pdata->dai_clk_names[i];
2834
+		init.ops = &rt5682_dai_clk_ops[i];
2835
+		init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2836
+		dai_clk_hw->init = &init;
2837
+
2838
+		ret = devm_clk_hw_register(dev, dai_clk_hw);
2839
+		if (ret) {
2840
+			dev_warn(dev, "Failed to register %s: %d\n",
2841
+				 init.name, ret);
2842
+			return ret;
2843
+		}
2844
+
2845
+		if (dev->of_node) {
2846
+			devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2847
+						    dai_clk_hw);
2848
+		} else {
2849
+			ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2850
+							  init.name,
2851
+							  dev_name(dev));
2852
+			if (ret)
2853
+				return ret;
2854
+		}
2855
+	}
2856
+
2857
+	return 0;
2858
+}
2859
+#endif /* CONFIG_COMMON_CLK */
2860
+
2314
2861
 static int rt5682_probe(struct snd_soc_component *component)
2315
2862
 {
2316
2863
 	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2864
+	struct sdw_slave *slave;
2865
+	unsigned long time;
2866
+	struct snd_soc_dapm_context *dapm = &component->dapm;
2317
2867
 
2868
+#ifdef CONFIG_COMMON_CLK
2869
+	int ret;
2870
+#endif
2318
2871
 	rt5682->component = component;
2319
2872
 
2873
+	if (rt5682->is_sdw) {
2874
+		slave = rt5682->slave;
2875
+		time = wait_for_completion_timeout(
2876
+			&slave->initialization_complete,
2877
+			msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2878
+		if (!time) {
2879
+			dev_err(&slave->dev, "Initialization not complete, timed out\n");
2880
+			return -ETIMEDOUT;
2881
+		}
2882
+	} else {
2883
+#ifdef CONFIG_COMMON_CLK
2884
+		/* Check if MCLK provided */
2885
+		rt5682->mclk = devm_clk_get(component->dev, "mclk");
2886
+		if (IS_ERR(rt5682->mclk)) {
2887
+			if (PTR_ERR(rt5682->mclk) != -ENOENT) {
2888
+				ret = PTR_ERR(rt5682->mclk);
2889
+				return ret;
2890
+			}
2891
+			rt5682->mclk = NULL;
2892
+		}
2893
+
2894
+		/* Register CCF DAI clock control */
2895
+		ret = rt5682_register_dai_clks(component);
2896
+		if (ret)
2897
+			return ret;
2898
+
2899
+		/* Initial setup for CCF */
2900
+		rt5682->lrck[RT5682_AIF1] = CLK_48;
2901
+#endif
2902
+	}
2903
+
2904
+	snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2905
+	snd_soc_dapm_disable_pin(dapm, "Vref2");
2906
+	snd_soc_dapm_sync(dapm);
2320
2907
 	return 0;
2321
2908
 }
2322
2909
 
..
..
@@ -2324,7 +2911,7 @@
2324
2911
 {
2325
2912
 	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2326
2913
 
2327
-	rt5682_reset(rt5682->regmap);
2914
+	rt5682_reset(rt5682);
2328
2915
 }
2329
2916
 
2330
2917
 #ifdef CONFIG_PM
..
..
@@ -2344,6 +2931,9 @@
2344
2931
 	regcache_cache_only(rt5682->regmap, false);
2345
2932
 	regcache_sync(rt5682->regmap);
2346
2933
 
2934
+	mod_delayed_work(system_power_efficient_wq,
2935
+		&rt5682->jack_detect_work, msecs_to_jiffies(250));
2936
+
2347
2937
 	return 0;
2348
2938
 }
2349
2939
 #else
..
..
@@ -2351,57 +2941,22 @@
2351
2941
 #define rt5682_resume NULL
2352
2942
 #endif
2353
2943
 
2354
-#define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2355
-#define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2356
-		SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2357
-
2358
-static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2944
+const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2359
2945
 	.hw_params = rt5682_hw_params,
2360
2946
 	.set_fmt = rt5682_set_dai_fmt,
2361
2947
 	.set_tdm_slot = rt5682_set_tdm_slot,
2948
+	.set_bclk_ratio = rt5682_set_bclk1_ratio,
2362
2949
 };
2950
+EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
2363
2951
 
2364
-static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2952
+const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2365
2953
 	.hw_params = rt5682_hw_params,
2366
2954
 	.set_fmt = rt5682_set_dai_fmt,
2367
-	.set_bclk_ratio = rt5682_set_bclk_ratio,
2955
+	.set_bclk_ratio = rt5682_set_bclk2_ratio,
2368
2956
 };
2957
+EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
2369
2958
 
2370
-static struct snd_soc_dai_driver rt5682_dai[] = {
2371
-	{
2372
-		.name = "rt5682-aif1",
2373
-		.id = RT5682_AIF1,
2374
-		.playback = {
2375
-			.stream_name = "AIF1 Playback",
2376
-			.channels_min = 1,
2377
-			.channels_max = 2,
2378
-			.rates = RT5682_STEREO_RATES,
2379
-			.formats = RT5682_FORMATS,
2380
-		},
2381
-		.capture = {
2382
-			.stream_name = "AIF1 Capture",
2383
-			.channels_min = 1,
2384
-			.channels_max = 2,
2385
-			.rates = RT5682_STEREO_RATES,
2386
-			.formats = RT5682_FORMATS,
2387
-		},
2388
-		.ops = &rt5682_aif1_dai_ops,
2389
-	},
2390
-	{
2391
-		.name = "rt5682-aif2",
2392
-		.id = RT5682_AIF2,
2393
-		.capture = {
2394
-			.stream_name = "AIF2 Capture",
2395
-			.channels_min = 1,
2396
-			.channels_max = 2,
2397
-			.rates = RT5682_STEREO_RATES,
2398
-			.formats = RT5682_FORMATS,
2399
-		},
2400
-		.ops = &rt5682_aif2_dai_ops,
2401
-	},
2402
-};
2403
-
2404
-static const struct snd_soc_component_driver soc_component_dev_rt5682 = {
2959
+const struct snd_soc_component_driver rt5682_soc_component_dev = {
2405
2960
 	.probe = rt5682_probe,
2406
2961
 	.remove = rt5682_remove,
2407
2962
 	.suspend = rt5682_suspend,
..
..
@@ -2420,26 +2975,9 @@
2420
2975
 	.endianness		= 1,
2421
2976
 	.non_legacy_dai_naming	= 1,
2422
2977
 };
2978
+EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
2423
2979
 
2424
-static const struct regmap_config rt5682_regmap = {
2425
-	.reg_bits = 16,
2426
-	.val_bits = 16,
2427
-	.max_register = RT5682_I2C_MODE,
2428
-	.volatile_reg = rt5682_volatile_register,
2429
-	.readable_reg = rt5682_readable_register,
2430
-	.cache_type = REGCACHE_RBTREE,
2431
-	.reg_defaults = rt5682_reg,
2432
-	.num_reg_defaults = ARRAY_SIZE(rt5682_reg),
2433
-	.use_single_rw = true,
2434
-};
2435
-
2436
-static const struct i2c_device_id rt5682_i2c_id[] = {
2437
-	{"rt5682", 0},
2438
-	{}
2439
-};
2440
-MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id);
2441
-
2442
-static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2980
+int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2443
2981
 {
2444
2982
 
2445
2983
 	device_property_read_u32(dev, "realtek,dmic1-data-pin",
..
..
@@ -2448,44 +2986,52 @@
2448
2986
 		&rt5682->pdata.dmic1_clk_pin);
2449
2987
 	device_property_read_u32(dev, "realtek,jd-src",
2450
2988
 		&rt5682->pdata.jd_src);
2989
+	device_property_read_u32(dev, "realtek,btndet-delay",
2990
+		&rt5682->pdata.btndet_delay);
2991
+	device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2992
+		&rt5682->pdata.dmic_clk_rate);
2993
+	device_property_read_u32(dev, "realtek,dmic-delay-ms",
2994
+		&rt5682->pdata.dmic_delay);
2451
2995
 
2452
2996
 	rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2453
2997
 		"realtek,ldo1-en-gpios", 0);
2454
2998
 
2999
+	if (device_property_read_string_array(dev, "clock-output-names",
3000
+					      rt5682->pdata.dai_clk_names,
3001
+					      RT5682_DAI_NUM_CLKS) < 0)
3002
+		dev_warn(dev, "Using default DAI clk names: %s, %s\n",
3003
+			 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
3004
+			 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
3005
+
2455
3006
 	return 0;
2456
3007
 }
3008
+EXPORT_SYMBOL_GPL(rt5682_parse_dt);
2457
3009
 
2458
-static void rt5682_calibrate(struct rt5682_priv *rt5682)
3010
+void rt5682_calibrate(struct rt5682_priv *rt5682)
2459
3011
 {
2460
3012
 	int value, count;
2461
3013
 
2462
3014
 	mutex_lock(&rt5682->calibrate_mutex);
2463
3015
 
2464
-	rt5682_reset(rt5682->regmap);
2465
-	regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2bf);
3016
+	rt5682_reset(rt5682);
3017
+	regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3018
+	regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
2466
3019
 	usleep_range(15000, 20000);
2467
-	regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2bf);
2468
-	regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2469
-	regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x8001);
2470
-	regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2471
-	regmap_write(rt5682->regmap, RT5682_STO1_DAC_MIXER, 0x2080);
2472
-	regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x4040);
2473
-	regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0069);
3020
+	regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3021
+	regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3022
+	regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3023
+	regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3024
+	regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
2474
3025
 	regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
2475
-	regmap_write(rt5682->regmap, RT5682_HP_CTRL_2, 0x6000);
2476
-	regmap_write(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1, 0x0f26);
2477
-	regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7f05);
3026
+	regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
2478
3027
 	regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
2479
3028
 	regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
2480
-	regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_9, 0x000f);
2481
-	regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x8d01);
2482
3029
 	regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
2483
3030
 	regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
2484
3031
 	regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2485
3032
 	regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
2486
3033
 	regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
2487
-	regmap_write(rt5682->regmap, RT5682_RESET_HPF_CTRL, 0x0000);
2488
-	regmap_write(rt5682->regmap, RT5682_ADC_STO1_HP_CTRL_1, 0x3320);
3034
+	regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2489
3035
 
2490
3036
 	regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
2491
3037
 
..
..
@@ -2498,194 +3044,21 @@
2498
3044
 	}
2499
3045
 
2500
3046
 	if (count >= 60)
2501
-		pr_err("HP Calibration Failure\n");
3047
+		dev_err(rt5682->component->dev, "HP Calibration Failure\n");
2502
3048
 
2503
3049
 	/* restore settings */
2504
-	regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3050
+	regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
3051
+	regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3052
+	regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
2505
3053
 	regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3054
+	regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3055
+	regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3056
+	regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3057
+	regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
2506
3058
 
2507
3059
 	mutex_unlock(&rt5682->calibrate_mutex);
2508
-
2509
3060
 }
2510
-
2511
-static int rt5682_i2c_probe(struct i2c_client *i2c,
2512
-		    const struct i2c_device_id *id)
2513
-{
2514
-	struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev);
2515
-	struct rt5682_priv *rt5682;
2516
-	int i, ret;
2517
-	unsigned int val;
2518
-
2519
-	rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv),
2520
-		GFP_KERNEL);
2521
-
2522
-	if (rt5682 == NULL)
2523
-		return -ENOMEM;
2524
-
2525
-	i2c_set_clientdata(i2c, rt5682);
2526
-
2527
-	if (pdata)
2528
-		rt5682->pdata = *pdata;
2529
-	else
2530
-		rt5682_parse_dt(rt5682, &i2c->dev);
2531
-
2532
-	rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap);
2533
-	if (IS_ERR(rt5682->regmap)) {
2534
-		ret = PTR_ERR(rt5682->regmap);
2535
-		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2536
-			ret);
2537
-		return ret;
2538
-	}
2539
-
2540
-	for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++)
2541
-		rt5682->supplies[i].supply = rt5682_supply_names[i];
2542
-
2543
-	ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies),
2544
-				      rt5682->supplies);
2545
-	if (ret != 0) {
2546
-		dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2547
-		return ret;
2548
-	}
2549
-
2550
-	ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
2551
-				    rt5682->supplies);
2552
-	if (ret != 0) {
2553
-		dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2554
-		return ret;
2555
-	}
2556
-
2557
-	if (gpio_is_valid(rt5682->pdata.ldo1_en)) {
2558
-		if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en,
2559
-					  GPIOF_OUT_INIT_HIGH, "rt5682"))
2560
-			dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
2561
-	}
2562
-
2563
-	/* Sleep for 300 ms miniumum */
2564
-	usleep_range(300000, 350000);
2565
-
2566
-	regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1);
2567
-	usleep_range(10000, 15000);
2568
-
2569
-	regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
2570
-	if (val != DEVICE_ID) {
2571
-		pr_err("Device with ID register %x is not rt5682\n", val);
2572
-		return -ENODEV;
2573
-	}
2574
-
2575
-	rt5682_reset(rt5682->regmap);
2576
-
2577
-	rt5682_calibrate(rt5682);
2578
-
2579
-	ret = regmap_register_patch(rt5682->regmap, patch_list,
2580
-				    ARRAY_SIZE(patch_list));
2581
-	if (ret != 0)
2582
-		dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2583
-
2584
-	regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
2585
-
2586
-	/* DMIC pin*/
2587
-	if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) {
2588
-		switch (rt5682->pdata.dmic1_data_pin) {
2589
-		case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */
2590
-			regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2591
-				RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2);
2592
-			regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2593
-				RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA);
2594
-			break;
2595
-
2596
-		case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
2597
-			regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2598
-				RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5);
2599
-			regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2600
-				RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA);
2601
-			break;
2602
-
2603
-		default:
2604
-			dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
2605
-			break;
2606
-		}
2607
-
2608
-		switch (rt5682->pdata.dmic1_clk_pin) {
2609
-		case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */
2610
-			regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2611
-				RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK);
2612
-			break;
2613
-
2614
-		case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */
2615
-			regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2616
-				RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK);
2617
-			break;
2618
-
2619
-		default:
2620
-			dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
2621
-			break;
2622
-		}
2623
-	}
2624
-
2625
-	regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2626
-			RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
2627
-			RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
2628
-	regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2629
-	regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2630
-			RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK,
2631
-			RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1);
2632
-	regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2633
-
2634
-	INIT_DELAYED_WORK(&rt5682->jack_detect_work,
2635
-				rt5682_jack_detect_handler);
2636
-	INIT_DELAYED_WORK(&rt5682->jd_check_work,
2637
-				rt5682_jd_check_handler);
2638
-
2639
-	mutex_init(&rt5682->calibrate_mutex);
2640
-
2641
-	if (i2c->irq) {
2642
-		ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2643
-			rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2644
-			| IRQF_ONESHOT, "rt5682", rt5682);
2645
-		if (ret)
2646
-			dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2647
-
2648
-	}
2649
-
2650
-	return devm_snd_soc_register_component(&i2c->dev,
2651
-			&soc_component_dev_rt5682,
2652
-			rt5682_dai, ARRAY_SIZE(rt5682_dai));
2653
-}
2654
-
2655
-static void rt5682_i2c_shutdown(struct i2c_client *client)
2656
-{
2657
-	struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
2658
-
2659
-	rt5682_reset(rt5682->regmap);
2660
-}
2661
-
2662
-#ifdef CONFIG_OF
2663
-static const struct of_device_id rt5682_of_match[] = {
2664
-	{.compatible = "realtek,rt5682i"},
2665
-	{},
2666
-};
2667
-MODULE_DEVICE_TABLE(of, rt5682_of_match);
2668
-#endif
2669
-
2670
-#ifdef CONFIG_ACPI
2671
-static const struct acpi_device_id rt5682_acpi_match[] = {
2672
-	{"10EC5682", 0,},
2673
-	{},
2674
-};
2675
-MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match);
2676
-#endif
2677
-
2678
-static struct i2c_driver rt5682_i2c_driver = {
2679
-	.driver = {
2680
-		.name = "rt5682",
2681
-		.of_match_table = of_match_ptr(rt5682_of_match),
2682
-		.acpi_match_table = ACPI_PTR(rt5682_acpi_match),
2683
-	},
2684
-	.probe = rt5682_i2c_probe,
2685
-	.shutdown = rt5682_i2c_shutdown,
2686
-	.id_table = rt5682_i2c_id,
2687
-};
2688
-module_i2c_driver(rt5682_i2c_driver);
3061
+EXPORT_SYMBOL_GPL(rt5682_calibrate);
2689
3062
 
2690
3063
 MODULE_DESCRIPTION("ASoC RT5682 driver");
2691
3064
 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");