.. | .. |
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56 | 56 | BIT_MASK_DESCR(IRQCHIP_ONESHOT_SAFE), |
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57 | 57 | BIT_MASK_DESCR(IRQCHIP_EOI_THREADED), |
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58 | 58 | BIT_MASK_DESCR(IRQCHIP_SUPPORTS_LEVEL_MSI), |
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| 59 | + BIT_MASK_DESCR(IRQCHIP_SUPPORTS_NMI), |
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| 60 | + BIT_MASK_DESCR(IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND), |
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59 | 61 | }; |
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60 | 62 | |
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61 | 63 | static void |
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.. | .. |
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111 | 113 | BIT_MASK_DESCR(IRQD_AFFINITY_SET), |
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112 | 114 | BIT_MASK_DESCR(IRQD_SETAFFINITY_PENDING), |
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113 | 115 | BIT_MASK_DESCR(IRQD_AFFINITY_MANAGED), |
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| 116 | + BIT_MASK_DESCR(IRQD_AFFINITY_ON_ACTIVATE), |
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114 | 117 | BIT_MASK_DESCR(IRQD_MANAGED_SHUTDOWN), |
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115 | 118 | BIT_MASK_DESCR(IRQD_CAN_RESERVE), |
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116 | 119 | BIT_MASK_DESCR(IRQD_MSI_NOMASK_QUIRK), |
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.. | .. |
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119 | 122 | |
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120 | 123 | BIT_MASK_DESCR(IRQD_WAKEUP_STATE), |
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121 | 124 | BIT_MASK_DESCR(IRQD_WAKEUP_ARMED), |
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| 125 | + |
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| 126 | + BIT_MASK_DESCR(IRQD_DEFAULT_TRIGGER_SET), |
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| 127 | + |
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| 128 | + BIT_MASK_DESCR(IRQD_HANDLE_ENFORCE_IRQCTX), |
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| 129 | + |
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| 130 | + BIT_MASK_DESCR(IRQD_IRQ_ENABLED_ON_SUSPEND), |
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122 | 131 | }; |
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123 | 132 | |
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124 | 133 | static const struct irq_bit_descr irqdesc_states[] = { |
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.. | .. |
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130 | 139 | BIT_MASK_DESCR(_IRQ_PER_CPU_DEVID), |
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131 | 140 | BIT_MASK_DESCR(_IRQ_IS_POLLED), |
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132 | 141 | BIT_MASK_DESCR(_IRQ_DISABLE_UNLAZY), |
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| 142 | + BIT_MASK_DESCR(_IRQ_HIDDEN), |
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| 143 | + BIT_MASK_DESCR(_IRQ_RAW), |
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133 | 144 | }; |
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134 | 145 | |
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135 | 146 | static const struct irq_bit_descr irqdesc_istates[] = { |
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.. | .. |
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141 | 152 | BIT_MASK_DESCR(IRQS_WAITING), |
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142 | 153 | BIT_MASK_DESCR(IRQS_PENDING), |
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143 | 154 | BIT_MASK_DESCR(IRQS_SUSPENDED), |
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| 155 | + BIT_MASK_DESCR(IRQS_NMI), |
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144 | 156 | }; |
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145 | 157 | |
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146 | 158 | |
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.. | .. |
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151 | 163 | |
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152 | 164 | raw_spin_lock_irq(&desc->lock); |
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153 | 165 | data = irq_desc_get_irq_data(desc); |
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154 | | - seq_printf(m, "handler: %pf\n", desc->handle_irq); |
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| 166 | + seq_printf(m, "handler: %ps\n", desc->handle_irq); |
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155 | 167 | seq_printf(m, "device: %s\n", desc->dev_name); |
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156 | 168 | seq_printf(m, "status: 0x%08x\n", desc->status_use_accessors); |
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157 | 169 | irq_debug_show_bits(m, 0, desc->status_use_accessors, irqdesc_states, |
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.. | .. |
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188 | 200 | return -EFAULT; |
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189 | 201 | |
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190 | 202 | if (!strncmp(buf, "trigger", size)) { |
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191 | | - unsigned long flags; |
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192 | | - int err; |
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193 | | - |
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194 | | - /* Try the HW interface first */ |
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195 | | - err = irq_set_irqchip_state(irq_desc_get_irq(desc), |
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196 | | - IRQCHIP_STATE_PENDING, true); |
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197 | | - if (!err) |
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198 | | - return count; |
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199 | | - |
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200 | | - /* |
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201 | | - * Otherwise, try to inject via the resend interface, |
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202 | | - * which may or may not succeed. |
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203 | | - */ |
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204 | | - chip_bus_lock(desc); |
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205 | | - raw_spin_lock_irqsave(&desc->lock, flags); |
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206 | | - |
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207 | | - if (irq_settings_is_level(desc)) { |
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208 | | - /* Can't do level, sorry */ |
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209 | | - err = -EINVAL; |
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210 | | - } else { |
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211 | | - desc->istate |= IRQS_PENDING; |
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212 | | - check_irq_resend(desc); |
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213 | | - err = 0; |
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214 | | - } |
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215 | | - |
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216 | | - raw_spin_unlock_irqrestore(&desc->lock, flags); |
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217 | | - chip_bus_sync_unlock(desc); |
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| 203 | + int err = irq_inject_interrupt(irq_desc_get_irq(desc)); |
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218 | 204 | |
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219 | 205 | return err ? err : count; |
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220 | 206 | } |
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.. | .. |
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257 | 243 | int irq; |
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258 | 244 | |
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259 | 245 | root_dir = debugfs_create_dir("irq", NULL); |
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260 | | - if (!root_dir) |
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261 | | - return -ENOMEM; |
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262 | 246 | |
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263 | 247 | irq_domain_debugfs_init(root_dir); |
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264 | 248 | |
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