~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,21 +1,13 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3	4	* Author: Addy Ke <addy.ke@rock-chips.com>
4		- *
5		- * This program is free software; you can redistribute it and/or modify it
6		- * under the terms and conditions of the GNU General Public License,
7		- * version 2, as published by the Free Software Foundation.
8		- *
9		- * This program is distributed in the hope it will be useful, but WITHOUT
10		- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11		- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12		- * more details.
13		- *
14	5	*/
15	6
	7	+#include <linux/acpi.h>
16	8	#include <linux/clk.h>
	9	+#include <linux/delay.h>
17	10	#include <linux/dmaengine.h>
18		-#include <linux/gpio.h>
19	11	#include <linux/interrupt.h>
20	12	#include <linux/miscdevice.h>
21	13	#include <linux/module.h>
..	..	@@ -181,6 +173,12 @@
181	173
182	174	#define ROCKCHIP_SPI_REGISTER_SIZE 0x1000
183	175
	176	+enum rockchip_spi_xfer_mode {
	177	+ ROCKCHIP_SPI_DMA,
	178	+ ROCKCHIP_SPI_IRQ,
	179	+ ROCKCHIP_SPI_POLL,
	180	+};
	181	+
184	182	struct rockchip_spi_quirks {
185	183	u32 max_baud_div_in_cpha;
186	184	};
..	..	@@ -190,6 +188,7 @@
190	188
191	189	struct clk *spiclk;
192	190	struct clk *apb_pclk;
	191	+ struct clk *sclk_in;
193	192
194	193	void __iomem *regs;
195	194	dma_addr_t dma_addr_rx;
..	..	@@ -201,7 +200,9 @@
201	200	unsigned int rx_left;
202	201
203	202	atomic_t state;
	203	+ struct completion xfer_done;
204	204
	205	+ u32 version;
205	206	/depth of the FIFO buffer /
206	207	u32 fifo_len;
207	208	/* frequency of spiclk */
..	..	@@ -211,13 +212,17 @@
211	212
212	213	u8 n_bytes;
213	214	u8 rsd;
	215	+ u8 csm;
	216	+ bool poll; /* only support transfer data by cpu polling */
214	217
215	218	bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
216	219
217	220	struct pinctrl_state *high_speed_state;
218		- bool slave_abort;
219		- bool gpio_requested;
	221	+ bool slave_aborted;
220	222	bool cs_inactive; /* spi slave tansmition stop when cs inactive */
	223	+ bool cs_high_supported; /* native CS supports active-high polarity */
	224	+ struct gpio_desc ready; / spi slave transmission ready */
	225	+
221	226	struct spi_transfer xfer; / Store xfer temporarily */
222	227	phys_addr_t base_addr_phy;
223	228	struct miscdevice miscdev;
..	..	@@ -231,17 +236,29 @@
231	236	writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
232	237	}
233	238
234		-static inline void wait_for_idle(struct rockchip_spi *rs, bool slave_mode)
	239	+static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
235	240	{
236	241	unsigned long timeout = jiffies + msecs_to_jiffies(5);
	242	+ u32 bit_filed = SR_BUSY;
	243	+ u32 idle_val = 0;
	244	+ uint32_t speed, us;
	245	+
	246	+ if (slave_mode && rs->version == ROCKCHIP_SPI_VER2_TYPE2) {
	247	+ bit_filed = SR_SLAVE_TX_BUSY;
	248	+ idle_val = 0;
	249	+ } else if (slave_mode) {
	250	+ bit_filed = SR_TF_EMPTY;
	251	+ idle_val = 1;
	252	+ }
237	253
238	254	do {
239		- if (slave_mode) {
240		- if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY))
241		- return;
242		- } else {
243		- if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
244		- return;
	255	+ if ((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & bit_filed) == idle_val) {
	256	+ if (bit_filed == SR_TF_EMPTY) {
	257	+ speed = rs->speed_hz;
	258	+ us = (8 * 1000000 / speed) * 2;
	259	+ udelay(us);
	260	+ }
	261	+ return;
245	262	}
246	263	} while (!time_after(jiffies, timeout));
247	264
..	..	@@ -250,11 +267,7 @@
250	267
251	268	static u32 get_fifo_len(struct rockchip_spi *rs)
252	269	{
253		- u32 ver;
254		-
255		- ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
256		-
257		- switch (ver) {
	270	+ switch (rs->version) {
258	271	case ROCKCHIP_SPI_VER2_TYPE1:
259	272	case ROCKCHIP_SPI_VER2_TYPE2:
260	273	return 64;
..	..	@@ -277,12 +290,12 @@
277	290	/* Keep things powered as long as CS is asserted */
278	291	pm_runtime_get_sync(rs->dev);
279	292
280		- if (gpio_is_valid(spi->cs_gpio))
	293	+ if (spi->cs_gpiod)
281	294	ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
282	295	else
283	296	ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
284	297	} else {
285		- if (gpio_is_valid(spi->cs_gpio))
	298	+ if (spi->cs_gpiod)
286	299	ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
287	300	else
288	301	ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
..	..	@@ -299,6 +312,11 @@
299	312	{
300	313	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
301	314
	315	+ dev_err(rs->dev, "state=%x\n", atomic_read(&rs->state));
	316	+ dev_err(rs->dev, "tx_left=%x\n", rs->tx_left);
	317	+ dev_err(rs->dev, "rx_left=%x\n", rs->rx_left);
	318	+ print_hex_dump(KERN_ERR, "regs ", DUMP_PREFIX_OFFSET, 4, 4, rs->regs, 0x4c, 0);
	319	+
302	320	/* stop running spi transfer
303	321	* this also flushes both rx and tx fifos
304	322	*/
..	..	@@ -313,6 +331,7 @@
313	331
314	332	if (atomic_read(&rs->state) & RXDMA)
315	333	dmaengine_terminate_async(ctlr->dma_rx);
	334	+ atomic_set(&rs->state, 0);
316	335	}
317	336
318	337	static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
..	..	@@ -337,7 +356,7 @@
337	356	static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
338	357	{
339	358	u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
340		- u32 rx_left = rs->rx_left > words ? rs->rx_left - words : 0;
	359	+ u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
341	360
342	361	/* the hardware doesn't allow us to change fifo threshold
343	362	* level while spi is enabled, so instead make sure to leave
..	..	@@ -374,7 +393,7 @@
374	393	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
375	394
376	395	/* When int_cs_inactive comes, spi slave abort */
377		- if (readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
	396	+ if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_ISR) & INT_CS_INACTIVE) {
378	397	ctlr->slave_abort(ctlr);
379	398	writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
380	399	writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
..	..	@@ -390,7 +409,7 @@
390	409	spi_enable_chip(rs, false);
391	410	writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
392	411	writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
393		- spi_finalize_current_transfer(ctlr);
	412	+ complete(&rs->xfer_done);
394	413	}
395	414
396	415	return IRQ_HANDLED;
..	..	@@ -400,8 +419,6 @@
400	419	struct spi_controller *ctlr,
401	420	struct spi_transfer *xfer)
402	421	{
403		- rs->tx = xfer->tx_buf;
404		- rs->rx = xfer->rx_buf;
405	422	rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
406	423	rs->rx_left = xfer->len / rs->n_bytes;
407	424
..	..	@@ -427,14 +444,16 @@
427	444	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
428	445	int state = atomic_fetch_andnot(RXDMA, &rs->state);
429	446
430		- if (state & TXDMA && !rs->slave_abort)
	447	+ if (state & TXDMA && !rs->slave_aborted)
431	448	return;
432	449
433	450	if (rs->cs_inactive)
434	451	writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
435	452
436	453	spi_enable_chip(rs, false);
437		- spi_finalize_current_transfer(ctlr);
	454	+ writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
	455	+ writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
	456	+ complete(&rs->xfer_done);
438	457	}
439	458
440	459	static void rockchip_spi_dma_txcb(void *data)
..	..	@@ -443,22 +462,24 @@
443	462	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
444	463	int state = atomic_fetch_andnot(TXDMA, &rs->state);
445	464
446		- if (state & RXDMA && !rs->slave_abort)
	465	+ if (state & RXDMA && !rs->slave_aborted)
447	466	return;
448	467
449	468	/* Wait until the FIFO data completely. */
450		- wait_for_idle(rs, ctlr->slave);
	469	+ wait_for_tx_idle(rs, ctlr->slave);
451	470
452	471	spi_enable_chip(rs, false);
453		- spi_finalize_current_transfer(ctlr);
	472	+ writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
	473	+ writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
	474	+ complete(&rs->xfer_done);
454	475	}
455	476
456	477	static u32 rockchip_spi_calc_burst_size(u32 data_len)
457	478	{
458	479	u32 i;
459	480
460		- /* burst size: 1, 2, 4, 8 */
461		- for (i = 1; i < 8; i <<= 1) {
	481	+ /* burst size: 1, 2, 4, 8, 16 */
	482	+ for (i = 1; i < 16; i <<= 1) {
462	483	if (data_len & i)
463	484	break;
464	485	}
..	..	@@ -472,9 +493,6 @@
472	493	struct dma_async_tx_descriptor rxdesc, txdesc;
473	494
474	495	atomic_set(&rs->state, 0);
475		-
476		- rs->tx = xfer->tx_buf;
477		- rs->rx = xfer->rx_buf;
478	496
479	497	rxdesc = NULL;
480	498	if (xfer->rx_buf) {
..	..	@@ -504,7 +522,7 @@
504	522	.direction = DMA_MEM_TO_DEV,
505	523	.dst_addr = rs->dma_addr_tx,
506	524	.dst_addr_width = rs->n_bytes,
507		- .dst_maxburst = 8,
	525	+ .dst_maxburst = rs->fifo_len / 4,
508	526	};
509	527
510	528	dmaengine_slave_config(ctlr->dma_tx, &txconf);
..	..	@@ -545,9 +563,59 @@
545	563	return 1;
546	564	}
547	565
548		-static void rockchip_spi_config(struct rockchip_spi *rs,
	566	+static int rockchip_spi_pio_transfer(struct rockchip_spi *rs,
	567	+ struct spi_controller ctlr, struct spi_transfer xfer)
	568	+{
	569	+ unsigned long time, timeout;
	570	+ u32 speed_hz = xfer->speed_hz;
	571	+ unsigned long long ms;
	572	+ int ret = 0;
	573	+
	574	+ if (!speed_hz)
	575	+ speed_hz = 100000;
	576	+
	577	+ ms = 8LL * 1000LL * xfer->len;
	578	+ do_div(ms, speed_hz);
	579	+ ms += ms + 200; /* some tolerance */
	580	+
	581	+ if (ms > UINT_MAX \|\| ctlr->slave)
	582	+ ms = UINT_MAX;
	583	+
	584	+ timeout = jiffies + msecs_to_jiffies(ms);
	585	+ time = jiffies;
	586	+ rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
	587	+ rs->rx_left = rs->rx ? xfer->len / rs->n_bytes : 0;
	588	+
	589	+ spi_enable_chip(rs, true);
	590	+
	591	+ while (rs->tx_left \|\| rs->rx_left) {
	592	+ if (rs->tx)
	593	+ rockchip_spi_pio_writer(rs);
	594	+
	595	+ if (rs->rx)
	596	+ rockchip_spi_pio_reader(rs);
	597	+
	598	+ cpu_relax();
	599	+
	600	+ if (time_after(time, timeout)) {
	601	+ ret = -EIO;
	602	+ goto out;
	603	+ }
	604	+ };
	605	+
	606	+ /* If tx, wait until the FIFO data completely. */
	607	+ if (rs->tx)
	608	+ wait_for_tx_idle(rs, ctlr->slave);
	609	+
	610	+out:
	611	+ spi_enable_chip(rs, false);
	612	+
	613	+ return ret;
	614	+}
	615	+
	616	+static int rockchip_spi_config(struct rockchip_spi *rs,
549	617	struct spi_device spi, struct spi_transfer xfer,
550		- bool use_dma, bool slave_mode)
	618	+ enum rockchip_spi_xfer_mode xfer_mode, bool slave_mode)
551	619	{
552	620	u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET
553	621	\| CR0_BHT_8BIT << CR0_BHT_OFFSET
..	..	@@ -558,21 +626,33 @@
558	626
559	627	if (slave_mode)
560	628	cr0 \|= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
561		- rs->slave_abort = false;
	629	+ rs->slave_aborted = false;
562	630
563	631	cr0 \|= rs->rsd << CR0_RSD_OFFSET;
	632	+ cr0 \|= rs->csm << CR0_CSM_OFFSET;
564	633	cr0 \|= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
565	634	if (spi->mode & SPI_LSB_FIRST)
566	635	cr0 \|= CR0_FBM_LSB << CR0_FBM_OFFSET;
567	636	if (spi->mode & SPI_CS_HIGH)
568	637	cr0 \|= BIT(spi->chip_select) << CR0_SOI_OFFSET;
569	638
570		- if (xfer->rx_buf && xfer->tx_buf)
	639	+ if (xfer->rx_buf && xfer->tx_buf) {
571	640	cr0 \|= CR0_XFM_TR << CR0_XFM_OFFSET;
572		- else if (xfer->rx_buf)
	641	+ } else if (xfer->rx_buf) {
573	642	cr0 \|= CR0_XFM_RO << CR0_XFM_OFFSET;
574		- else if (use_dma)
575		- cr0 \|= CR0_XFM_TO << CR0_XFM_OFFSET;
	643	+ } else if (xfer->tx_buf) {
	644	+ /*
	645	+ * Use the water line of rx fifo in full duplex mode to trigger
	646	+ * the interruption of tx irq transmission completion.
	647	+ */
	648	+ if (xfer_mode == ROCKCHIP_SPI_IRQ)
	649	+ cr0 \|= CR0_XFM_TR << CR0_XFM_OFFSET;
	650	+ else
	651	+ cr0 \|= CR0_XFM_TO << CR0_XFM_OFFSET;
	652	+ } else {
	653	+ dev_err(rs->dev, "no transmission buffer\n");
	654	+ return -EINVAL;
	655	+ }
576	656
577	657	switch (xfer->bits_per_word) {
578	658	case 4:
..	..	@@ -592,10 +672,12 @@
592	672	* ctlr->bits_per_word_mask, so this shouldn't
593	673	* happen
594	674	*/
595		- unreachable();
	675	+ dev_err(rs->dev, "unknown bits per word: %d\n",
	676	+ xfer->bits_per_word);
	677	+ return -EINVAL;
596	678	}
597	679
598		- if (use_dma) {
	680	+ if (xfer_mode == ROCKCHIP_SPI_DMA) {
599	681	if (xfer->tx_buf)
600	682	dmacr \|= TF_DMA_EN;
601	683	if (xfer->rx_buf)
..	..	@@ -652,6 +734,8 @@
652	734	writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
653	735	rs->regs + ROCKCHIP_SPI_BAUDR);
654	736	rs->speed_hz = xfer->speed_hz;
	737	+
	738	+ return 0;
655	739	}
656	740
657	741	static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
..	..	@@ -663,50 +747,54 @@
663	747	{
664	748	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
665	749	u32 rx_fifo_left;
666		- struct dma_tx_state state;
667		- enum dma_status status;
668	750
669		- /* Get current dma rx point */
670		- if (atomic_read(&rs->state) & RXDMA) {
671		- dmaengine_pause(ctlr->dma_rx);
672		- status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
673		- if (status == DMA_ERROR) {
674		- rs->rx = rs->xfer->rx_buf;
675		- rs->xfer->len = 0;
676		- rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
677		- for (; rx_fifo_left; rx_fifo_left--)
678		- readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
679		- goto out;
680		- } else {
681		- rs->rx += rs->xfer->len - rs->n_bytes * state.residue;
682		- }
683		- }
	751	+ /* Flush rx fifo */
	752	+ rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
	753	+ for (; rx_fifo_left; rx_fifo_left--)
	754	+ readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
684	755
685		- /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */
686		- if (rs->rx) {
687		- rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
688		- for (; rx_fifo_left; rx_fifo_left--) {
689		- u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
	756	+ rs->slave_aborted = true;
	757	+ complete(&rs->xfer_done);
690	758
691		- if (rs->n_bytes == 1)
692		- (u8 )rs->rx = (u8)rxw;
693		- else
694		- (u16 )rs->rx = (u16)rxw;
695		- rs->rx += rs->n_bytes;
	759	+ return 0;
	760	+}
	761	+
	762	+static int rockchip_spi_transfer_wait(struct spi_controller *ctlr,
	763	+ struct spi_transfer *xfer)
	764	+{
	765	+ struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
	766	+ u32 speed_hz = xfer->speed_hz;
	767	+ unsigned long long ms;
	768	+
	769	+ if (spi_controller_is_slave(ctlr)) {
	770	+ if (wait_for_completion_interruptible(&rs->xfer_done)) {
	771	+ dev_dbg(rs->dev, "RK SPI transfer interrupted\n");
	772	+ return -EINTR;
696	773	}
697	774
698		- rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf);
699		- }
	775	+ if (rs->slave_aborted) {
	776	+ dev_err(rs->dev, "RK SPI transfer slave abort\n");
	777	+ return -EIO;
	778	+ }
	779	+ } else {
	780	+ if (!speed_hz)
	781	+ speed_hz = 100000;
700	782
701		-out:
702		- if (atomic_read(&rs->state) & RXDMA)
703		- dmaengine_terminate_sync(ctlr->dma_rx);
704		- if (atomic_read(&rs->state) & TXDMA)
705		- dmaengine_terminate_sync(ctlr->dma_tx);
706		- atomic_set(&rs->state, 0);
707		- spi_enable_chip(rs, false);
708		- rs->slave_abort = true;
709		- complete(&ctlr->xfer_completion);
	783	+ ms = 8LL * 1000LL * xfer->len;
	784	+ do_div(ms, speed_hz);
	785	+ ms += ms + 200; /* some tolerance */
	786	+
	787	+ if (ms > UINT_MAX)
	788	+ ms = UINT_MAX;
	789	+
	790	+ ms = wait_for_completion_timeout(&rs->xfer_done,
	791	+ msecs_to_jiffies(ms));
	792	+
	793	+ if (ms == 0) {
	794	+ dev_err(rs->dev, "RK SPI transfer timed out\n");
	795	+ return -ETIMEDOUT;
	796	+ }
	797	+ }
710	798
711	799	return 0;
712	800	}
..	..	@@ -717,11 +805,13 @@
717	805	struct spi_transfer *xfer)
718	806	{
719	807	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
	808	+ int ret;
720	809	bool use_dma;
	810	+ enum rockchip_spi_xfer_mode xfer_mode;
721	811
722	812	/* Zero length transfers won't trigger an interrupt on completion */
723	813	if (!xfer->len) {
724		- spi_finalize_current_transfer(ctlr);
	814	+ complete(&rs->xfer_done);
725	815	return 1;
726	816	}
727	817
..	..	@@ -740,14 +830,49 @@
740	830
741	831	rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
742	832	rs->xfer = xfer;
743		- use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
	833	+ if (rs->poll) {
	834	+ xfer_mode = ROCKCHIP_SPI_POLL;
	835	+ } else {
	836	+ use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
	837	+ if (use_dma)
	838	+ xfer_mode = ROCKCHIP_SPI_DMA;
	839	+ else
	840	+ xfer_mode = ROCKCHIP_SPI_IRQ;
	841	+ }
744	842
745		- rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
	843	+ ret = rockchip_spi_config(rs, spi, xfer, xfer_mode, ctlr->slave);
	844	+ if (ret)
	845	+ return ret;
746	846
747		- if (use_dma)
748		- return rockchip_spi_prepare_dma(rs, ctlr, xfer);
	847	+ rs->tx = xfer->tx_buf;
	848	+ rs->rx = xfer->rx_buf;
749	849
750		- return rockchip_spi_prepare_irq(rs, ctlr, xfer);
	850	+ reinit_completion(&rs->xfer_done);
	851	+
	852	+ switch (xfer_mode) {
	853	+ case ROCKCHIP_SPI_POLL:
	854	+ ret = rockchip_spi_pio_transfer(rs, ctlr, xfer);
	855	+ break;
	856	+ case ROCKCHIP_SPI_DMA:
	857	+ ret = rockchip_spi_prepare_dma(rs, ctlr, xfer);
	858	+ break;
	859	+ default:
	860	+ ret = rockchip_spi_prepare_irq(rs, ctlr, xfer);
	861	+ }
	862	+
	863	+ if (rs->ready) {
	864	+ gpiod_set_value(rs->ready, 0);
	865	+ udelay(1);
	866	+ gpiod_set_value(rs->ready, 1);
	867	+ }
	868	+
	869	+ if (ret > 0)
	870	+ ret = rockchip_spi_transfer_wait(ctlr, xfer);
	871	+
	872	+ if (rs->ready)
	873	+ gpiod_set_value(rs->ready, 0);
	874	+
	875	+ return ret;
751	876	}
752	877
753	878	static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
..	..	@@ -766,10 +891,13 @@
766	891
767	892	static int rockchip_spi_setup(struct spi_device *spi)
768	893	{
769		-
770		- int ret = -EINVAL;
771	894	struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
772	895	u32 cr0;
	896	+
	897	+ if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
	898	+ dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
	899	+ return -EINVAL;
	900	+ }
773	901
774	902	pm_runtime_get_sync(rs->dev);
775	903
..	..	@@ -778,44 +906,14 @@
778	906	cr0 \|= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
779	907	if (spi->mode & SPI_CS_HIGH)
780	908	cr0 \|= BIT(spi->chip_select) << CR0_SOI_OFFSET;
	909	+ if (spi_controller_is_slave(spi->controller))
	910	+ cr0 \|= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
781	911
782	912	writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
783	913
784	914	pm_runtime_put(rs->dev);
785	915
786		- if (spi->cs_gpio == -ENOENT)
787		- return 0;
788		-
789		- if (!rs->gpio_requested && gpio_is_valid(spi->cs_gpio)) {
790		- ret = gpio_request_one(spi->cs_gpio,
791		- (spi->mode & SPI_CS_HIGH) ?
792		- GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH,
793		- dev_name(&spi->dev));
794		- if (ret)
795		- dev_err(&spi->dev, "can't request chipselect gpio %d\n",
796		- spi->cs_gpio);
797		- else
798		- rs->gpio_requested = true;
799		- } else {
800		- if (gpio_is_valid(spi->cs_gpio)) {
801		- int mode = ((spi->mode & SPI_CS_HIGH) ? 0 : 1);
802		-
803		- ret = gpio_direction_output(spi->cs_gpio, mode);
804		- if (ret)
805		- dev_err(&spi->dev, "chipselect gpio %d setup failed (%d)\n",
806		- spi->cs_gpio, ret);
807		- }
808		- }
809		-
810		- return ret;
811		-}
812		-
813		-static void rockchip_spi_cleanup(struct spi_device *spi)
814		-{
815		- struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
816		-
817		- if (rs->gpio_requested)
818		- gpio_free(spi->cs_gpio);
	916	+ return 0;
819	917	}
820	918
821	919	static int rockchip_spi_misc_open(struct inode inode, struct file filp)
..	..	@@ -879,10 +977,11 @@
879	977	struct spi_controller *ctlr;
880	978	struct resource *mem;
881	979	struct device_node *np = pdev->dev.of_node;
882		- u32 rsd_nsecs;
	980	+ u32 rsd_nsecs, num_cs, csm;
883	981	bool slave_mode;
884	982	struct pinctrl *pinctrl = NULL;
885	983	const struct rockchip_spi_quirks *quirks_cfg;
	984	+ u32 val;
886	985
887	986	slave_mode = of_property_read_bool(np, "spi-slave");
888	987
..	..	@@ -896,6 +995,7 @@
896	995	if (!ctlr)
897	996	return -ENOMEM;
898	997
	998	+ ctlr->rt = device_property_read_bool(&pdev->dev, "rockchip,rt");
899	999	platform_set_drvdata(pdev, ctlr);
900	1000
901	1001	rs = spi_controller_get_devdata(ctlr);
..	..	@@ -910,17 +1010,26 @@
910	1010	}
911	1011	rs->base_addr_phy = mem->start;
912	1012
913		- rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
	1013	+ if (!has_acpi_companion(&pdev->dev))
	1014	+ rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
914	1015	if (IS_ERR(rs->apb_pclk)) {
915	1016	dev_err(&pdev->dev, "Failed to get apb_pclk\n");
916	1017	ret = PTR_ERR(rs->apb_pclk);
917	1018	goto err_put_ctlr;
918	1019	}
919	1020
920		- rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
	1021	+ if (!has_acpi_companion(&pdev->dev))
	1022	+ rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
921	1023	if (IS_ERR(rs->spiclk)) {
922	1024	dev_err(&pdev->dev, "Failed to get spi_pclk\n");
923	1025	ret = PTR_ERR(rs->spiclk);
	1026	+ goto err_put_ctlr;
	1027	+ }
	1028	+
	1029	+ rs->sclk_in = devm_clk_get_optional(&pdev->dev, "sclk_in");
	1030	+ if (IS_ERR(rs->sclk_in)) {
	1031	+ dev_err(&pdev->dev, "Failed to get sclk_in\n");
	1032	+ ret = PTR_ERR(rs->sclk_in);
924	1033	goto err_put_ctlr;
925	1034	}
926	1035
..	..	@@ -936,23 +1045,35 @@
936	1045	goto err_disable_apbclk;
937	1046	}
938	1047
	1048	+ ret = clk_prepare_enable(rs->sclk_in);
	1049	+ if (ret < 0) {
	1050	+ dev_err(&pdev->dev, "Failed to enable sclk_in\n");
	1051	+ goto err_disable_spiclk;
	1052	+ }
	1053	+
939	1054	spi_enable_chip(rs, false);
940	1055
941	1056	ret = platform_get_irq(pdev, 0);
942	1057	if (ret < 0)
943		- goto err_disable_spiclk;
	1058	+ goto err_disable_sclk_in;
944	1059
945	1060	ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
946	1061	IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
947	1062	if (ret)
948		- goto err_disable_spiclk;
	1063	+ goto err_disable_sclk_in;
949	1064
950	1065	rs->dev = &pdev->dev;
951		- rs->freq = clk_get_rate(rs->spiclk);
952		- rs->gpio_requested = false;
953	1066
954		- if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
955		- &rsd_nsecs)) {
	1067	+ rs->freq = clk_get_rate(rs->spiclk);
	1068	+ if (!rs->freq) {
	1069	+ ret = device_property_read_u32(&pdev->dev, "clock-frequency", &rs->freq);
	1070	+ if (ret) {
	1071	+ dev_warn(rs->dev, "Failed to get clock or clock-frequency property\n");
	1072	+ goto err_disable_sclk_in;
	1073	+ }
	1074	+ }
	1075	+
	1076	+ if (!device_property_read_u32(&pdev->dev, "rx-sample-delay-ns", &rsd_nsecs)) {
956	1077	/* rx sample delay is expressed in parent clock cycles (max 3) */
957	1078	u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
958	1079	1000000000 >> 8);
..	..	@@ -968,37 +1089,61 @@
968	1089	rs->rsd = rsd;
969	1090	}
970	1091
	1092	+ if (!device_property_read_u32(&pdev->dev, "csm", &csm)) {
	1093	+ if (csm > CR0_CSM_ONE) {
	1094	+ dev_warn(rs->dev, "The csm value %u exceeds the limit, clamping at %u\n",
	1095	+ csm, CR0_CSM_ONE);
	1096	+ csm = CR0_CSM_ONE;
	1097	+ }
	1098	+ rs->csm = csm;
	1099	+ }
	1100	+
	1101	+ rs->version = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
971	1102	rs->fifo_len = get_fifo_len(rs);
972	1103	if (!rs->fifo_len) {
973	1104	dev_err(&pdev->dev, "Failed to get fifo length\n");
974	1105	ret = -EINVAL;
975		- goto err_disable_spiclk;
	1106	+ goto err_disable_sclk_in;
976	1107	}
977	1108	quirks_cfg = device_get_match_data(&pdev->dev);
978	1109	if (quirks_cfg)
979	1110	rs->max_baud_div_in_cpha = quirks_cfg->max_baud_div_in_cpha;
	1111	+
	1112	+ if (!device_property_read_u32(&pdev->dev, "rockchip,autosuspend-delay-ms", &val)) {
	1113	+ if (val > 0) {
	1114	+ pm_runtime_set_autosuspend_delay(&pdev->dev, val);
	1115	+ pm_runtime_use_autosuspend(&pdev->dev);
	1116	+ }
	1117	+ }
980	1118
981	1119	pm_runtime_set_active(&pdev->dev);
982	1120	pm_runtime_enable(&pdev->dev);
983	1121
984	1122	ctlr->auto_runtime_pm = true;
985	1123	ctlr->bus_num = pdev->id;
986		- ctlr->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_LOOP \| SPI_LSB_FIRST \| SPI_CS_HIGH;
	1124	+ ctlr->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_LOOP \| SPI_LSB_FIRST;
987	1125	if (slave_mode) {
988	1126	ctlr->mode_bits \|= SPI_NO_CS;
989	1127	ctlr->slave_abort = rockchip_spi_slave_abort;
990	1128	} else {
991	1129	ctlr->flags = SPI_MASTER_GPIO_SS;
	1130	+ ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
	1131	+ /*
	1132	+ * rk spi0 has two native cs, spi1..5 one cs only
	1133	+ * if num-cs is missing in the dts, default to 1
	1134	+ */
	1135	+ if (device_property_read_u32(&pdev->dev, "num-cs", &num_cs))
	1136	+ num_cs = 1;
	1137	+ ctlr->num_chipselect = num_cs;
	1138	+ ctlr->use_gpio_descriptors = true;
992	1139	}
993		- ctlr->num_chipselect = ROCKCHIP_SPI_MAX_CS_NUM;
994	1140	ctlr->dev.of_node = pdev->dev.of_node;
995	1141	ctlr->bits_per_word_mask = SPI_BPW_MASK(16) \| SPI_BPW_MASK(8) \| SPI_BPW_MASK(4);
996	1142	ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
997	1143	ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
998	1144
999		- ctlr->set_cs = rockchip_spi_set_cs;
1000	1145	ctlr->setup = rockchip_spi_setup;
1001		- ctlr->cleanup = rockchip_spi_cleanup;
	1146	+ ctlr->set_cs = rockchip_spi_set_cs;
1002	1147	ctlr->transfer_one = rockchip_spi_transfer_one;
1003	1148	ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
1004	1149	ctlr->handle_err = rockchip_spi_handle_err;
..	..	@@ -1030,17 +1175,29 @@
1030	1175	ctlr->can_dma = rockchip_spi_can_dma;
1031	1176	}
1032	1177
1033		- switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
1034		- case ROCKCHIP_SPI_VER2_TYPE1:
	1178	+ rs->poll = device_property_read_bool(&pdev->dev, "rockchip,poll-only");
	1179	+ init_completion(&rs->xfer_done);
	1180	+ if (rs->poll && slave_mode) {
	1181	+ dev_err(rs->dev, "only support rockchip,poll-only property in master mode\n");
	1182	+ ret = -EINVAL;
	1183	+ goto err_free_dma_rx;
	1184	+ }
	1185	+
	1186	+ switch (rs->version) {
1035	1187	case ROCKCHIP_SPI_VER2_TYPE2:
1036		- if (ctlr->can_dma && slave_mode)
	1188	+ rs->cs_high_supported = true;
	1189	+ ctlr->mode_bits \|= SPI_CS_HIGH;
	1190	+ if (slave_mode)
1037	1191	rs->cs_inactive = true;
1038	1192	else
1039	1193	rs->cs_inactive = false;
1040	1194	break;
1041	1195	default:
1042	1196	rs->cs_inactive = false;
	1197	+ break;
1043	1198	}
	1199	+ if (device_property_read_bool(&pdev->dev, "rockchip,cs-inactive-disable"))
	1200	+ rs->cs_inactive = false;
1044	1201
1045	1202	pinctrl = devm_pinctrl_get(&pdev->dev);
1046	1203	if (!IS_ERR(pinctrl)) {
..	..	@@ -1049,6 +1206,13 @@
1049	1206	dev_warn(&pdev->dev, "no high_speed pinctrl state\n");
1050	1207	rs->high_speed_state = NULL;
1051	1208	}
	1209	+ }
	1210	+
	1211	+ rs->ready = devm_gpiod_get_optional(&pdev->dev, "ready", GPIOD_OUT_HIGH);
	1212	+ if (IS_ERR(rs->ready)) {
	1213	+ ret = dev_err_probe(&pdev->dev, PTR_ERR(rs->ready),
	1214	+ "invalid ready-gpios property in node\n");
	1215	+ goto err_free_dma_rx;
1052	1216	}
1053	1217
1054	1218	ret = devm_spi_register_controller(&pdev->dev, ctlr);
..	..	@@ -1073,6 +1237,9 @@
1073	1237	dev_info(&pdev->dev, "register misc device %s\n", misc_name);
1074	1238	}
1075	1239
	1240	+ dev_info(rs->dev, "probed, poll=%d, rsd=%d, cs-inactive=%d, ready=%d\n",
	1241	+ rs->poll, rs->rsd, rs->cs_inactive, rs->ready ? 1 : 0);
	1242	+
1076	1243	return 0;
1077	1244
1078	1245	err_free_dma_rx:
..	..	@@ -1083,6 +1250,8 @@
1083	1250	dma_release_channel(ctlr->dma_tx);
1084	1251	err_disable_pm_runtime:
1085	1252	pm_runtime_disable(&pdev->dev);
	1253	+err_disable_sclk_in:
	1254	+ clk_disable_unprepare(rs->sclk_in);
1086	1255	err_disable_spiclk:
1087	1256	clk_disable_unprepare(rs->spiclk);
1088	1257	err_disable_apbclk:
..	..	@@ -1103,6 +1272,7 @@
1103	1272
1104	1273	pm_runtime_get_sync(&pdev->dev);
1105	1274
	1275	+ clk_disable_unprepare(rs->sclk_in);
1106	1276	clk_disable_unprepare(rs->spiclk);
1107	1277	clk_disable_unprepare(rs->apb_pclk);
1108	1278
..	..	@@ -1119,51 +1289,6 @@
1119	1289
1120	1290	return 0;
1121	1291	}
1122		-
1123		-#ifdef CONFIG_PM_SLEEP
1124		-static int rockchip_spi_suspend(struct device *dev)
1125		-{
1126		- int ret;
1127		- struct spi_controller *ctlr = dev_get_drvdata(dev);
1128		- struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1129		-
1130		- ret = spi_controller_suspend(ctlr);
1131		- if (ret < 0)
1132		- return ret;
1133		-
1134		- clk_disable_unprepare(rs->spiclk);
1135		- clk_disable_unprepare(rs->apb_pclk);
1136		-
1137		- pinctrl_pm_select_sleep_state(dev);
1138		-
1139		- return 0;
1140		-}
1141		-
1142		-static int rockchip_spi_resume(struct device *dev)
1143		-{
1144		- int ret;
1145		- struct spi_controller *ctlr = dev_get_drvdata(dev);
1146		- struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1147		-
1148		- pinctrl_pm_select_default_state(dev);
1149		-
1150		- ret = clk_prepare_enable(rs->apb_pclk);
1151		- if (ret < 0)
1152		- return ret;
1153		-
1154		- ret = clk_prepare_enable(rs->spiclk);
1155		- if (ret < 0)
1156		- clk_disable_unprepare(rs->apb_pclk);
1157		-
1158		- ret = spi_controller_resume(ctlr);
1159		- if (ret < 0) {
1160		- clk_disable_unprepare(rs->spiclk);
1161		- clk_disable_unprepare(rs->apb_pclk);
1162		- }
1163		-
1164		- return 0;
1165		-}
1166		-#endif /* CONFIG_PM_SLEEP */
1167	1292
1168	1293	#ifdef CONFIG_PM
1169	1294	static int rockchip_spi_runtime_suspend(struct device *dev)
..	..	@@ -1195,6 +1320,46 @@
1195	1320	}
1196	1321	#endif /* CONFIG_PM */
1197	1322
	1323	+#ifdef CONFIG_PM_SLEEP
	1324	+static int rockchip_spi_suspend(struct device *dev)
	1325	+{
	1326	+ int ret;
	1327	+ struct spi_controller *ctlr = dev_get_drvdata(dev);
	1328	+
	1329	+ ret = spi_controller_suspend(ctlr);
	1330	+ if (ret < 0)
	1331	+ return ret;
	1332	+
	1333	+ /* Avoid redundant clock disable */
	1334	+ if (!pm_runtime_status_suspended(dev))
	1335	+ rockchip_spi_runtime_suspend(dev);
	1336	+
	1337	+ pinctrl_pm_select_sleep_state(dev);
	1338	+
	1339	+ return 0;
	1340	+}
	1341	+
	1342	+static int rockchip_spi_resume(struct device *dev)
	1343	+{
	1344	+ int ret;
	1345	+ struct spi_controller *ctlr = dev_get_drvdata(dev);
	1346	+
	1347	+ pinctrl_pm_select_default_state(dev);
	1348	+
	1349	+ if (!pm_runtime_status_suspended(dev)) {
	1350	+ ret = rockchip_spi_runtime_resume(dev);
	1351	+ if (ret < 0)
	1352	+ return ret;
	1353	+ }
	1354	+
	1355	+ ret = spi_controller_resume(ctlr);
	1356	+ if (ret < 0)
	1357	+ rockchip_spi_runtime_suspend(dev);
	1358	+
	1359	+ return 0;
	1360	+}
	1361	+#endif /* CONFIG_PM_SLEEP */
	1362	+
1198	1363	static const struct dev_pm_ops rockchip_spi_pm = {
1199	1364	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
1200	1365	SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
..	..	@@ -1210,15 +1375,18 @@
1210	1375	.compatible = "rockchip,px30-spi",
1211	1376	.data = &rockchip_spi_quirks_cfg,
1212	1377	},
1213		- { .compatible = "rockchip,rv1108-spi", },
1214		- { .compatible = "rockchip,rv1126-spi", },
1215	1378	{ .compatible = "rockchip,rk3036-spi", },
1216	1379	{ .compatible = "rockchip,rk3066-spi", },
1217	1380	{ .compatible = "rockchip,rk3188-spi", },
1218	1381	{ .compatible = "rockchip,rk3228-spi", },
1219	1382	{ .compatible = "rockchip,rk3288-spi", },
	1383	+ { .compatible = "rockchip,rk3308-spi", },
	1384	+ { .compatible = "rockchip,rk3328-spi", },
1220	1385	{ .compatible = "rockchip,rk3368-spi", },
1221	1386	{ .compatible = "rockchip,rk3399-spi", },
	1387	+ { .compatible = "rockchip,rv1106-spi", },
	1388	+ { .compatible = "rockchip,rv1108-spi", },
	1389	+ { .compatible = "rockchip,rv1126-spi", },
1222	1390	{ },
1223	1391	};
1224	1392	MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);