forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/spi/spi-rockchip.c
....@@ -221,6 +221,7 @@
221221 	bool slave_aborted;
222222 	bool cs_inactive; /* spi slave tansmition stop when cs inactive */
223223 	bool cs_high_supported; /* native CS supports active-high polarity */
224
+	struct gpio_desc *ready; /* spi slave transmission ready */
224225 
225226 	struct spi_transfer *xfer; /* Store xfer temporarily */
226227 	phys_addr_t base_addr_phy;
....@@ -477,8 +478,8 @@
477478 {
478479 	u32 i;
479480 
480
-	/* burst size: 1, 2, 4, 8 */
481
-	for (i = 1; i < 8; i <<= 1) {
481
+	/* burst size: 1, 2, 4, 8, 16 */
482
+	for (i = 1; i < 16; i <<= 1) {
482483 		if (data_len & i)
483484 			break;
484485 	}
....@@ -859,8 +860,17 @@
859860 		ret = rockchip_spi_prepare_irq(rs, ctlr, xfer);
860861 	}
861862 
863
+	if (rs->ready) {
864
+		gpiod_set_value(rs->ready, 0);
865
+		udelay(1);
866
+		gpiod_set_value(rs->ready, 1);
867
+	}
868
+
862869 	if (ret > 0)
863870 		ret = rockchip_spi_transfer_wait(ctlr, xfer);
871
+
872
+	if (rs->ready)
873
+		gpiod_set_value(rs->ready, 0);
864874 
865875 	return ret;
866876 }
....@@ -896,6 +906,8 @@
896906 	cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
897907 	if (spi->mode & SPI_CS_HIGH)
898908 		cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
909
+	if (spi_controller_is_slave(spi->controller))
910
+		cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
899911 
900912 	writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
901913 
....@@ -969,6 +981,7 @@
969981 	bool slave_mode;
970982 	struct pinctrl *pinctrl = NULL;
971983 	const struct rockchip_spi_quirks *quirks_cfg;
984
+	u32 val;
972985 
973986 	slave_mode = of_property_read_bool(np, "spi-slave");
974987 
....@@ -982,6 +995,7 @@
982995 	if (!ctlr)
983996 		return -ENOMEM;
984997 
998
+	ctlr->rt = device_property_read_bool(&pdev->dev, "rockchip,rt");
985999 	platform_set_drvdata(pdev, ctlr);
9861000 
9871001 	rs = spi_controller_get_devdata(ctlr);
....@@ -1095,6 +1109,13 @@
10951109 	if (quirks_cfg)
10961110 		rs->max_baud_div_in_cpha = quirks_cfg->max_baud_div_in_cpha;
10971111 
1112
+	if (!device_property_read_u32(&pdev->dev, "rockchip,autosuspend-delay-ms", &val)) {
1113
+		if (val > 0) {
1114
+			pm_runtime_set_autosuspend_delay(&pdev->dev, val);
1115
+			pm_runtime_use_autosuspend(&pdev->dev);
1116
+		}
1117
+	}
1118
+
10981119 	pm_runtime_set_active(&pdev->dev);
10991120 	pm_runtime_enable(&pdev->dev);
11001121 
....@@ -1175,6 +1196,8 @@
11751196 		rs->cs_inactive = false;
11761197 		break;
11771198 	}
1199
+	if (device_property_read_bool(&pdev->dev, "rockchip,cs-inactive-disable"))
1200
+		rs->cs_inactive = false;
11781201 
11791202 	pinctrl = devm_pinctrl_get(&pdev->dev);
11801203 	if (!IS_ERR(pinctrl)) {
....@@ -1183,6 +1206,13 @@
11831206 			dev_warn(&pdev->dev, "no high_speed pinctrl state\n");
11841207 			rs->high_speed_state = NULL;
11851208 		}
1209
+	}
1210
+
1211
+	rs->ready = devm_gpiod_get_optional(&pdev->dev, "ready", GPIOD_OUT_HIGH);
1212
+	if (IS_ERR(rs->ready)) {
1213
+		ret = dev_err_probe(&pdev->dev, PTR_ERR(rs->ready),
1214
+				    "invalid ready-gpios property in node\n");
1215
+		goto err_free_dma_rx;
11861216 	}
11871217 
11881218 	ret = devm_spi_register_controller(&pdev->dev, ctlr);
....@@ -1207,7 +1237,8 @@
12071237 			dev_info(&pdev->dev, "register misc device %s\n", misc_name);
12081238 	}
12091239 
1210
-	dev_info(rs->dev, "probed, poll=%d, rsd=%d\n", rs->poll, rs->rsd);
1240
+	dev_info(rs->dev, "probed, poll=%d, rsd=%d, cs-inactive=%d, ready=%d\n",
1241
+		 rs->poll, rs->rsd, rs->cs_inactive, rs->ready ? 1 : 0);
12111242 
12121243 	return 0;
12131244