add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/spi/spi-imx.c
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@@ -242,6 +242,18 @@
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 	return true;
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 }
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+/*
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+ * Note the number of natively supported chip selects for MX51 is 4. Some
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+ * devices may have less actual SS pins but the register map supports 4. When
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+ * using gpio chip selects the cs values passed into the macros below can go
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+ * outside the range 0 - 3. We therefore need to limit the cs value to avoid
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+ * corrupting bits outside the allocated locations.
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+ *
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+ * The simplest way to do this is to just mask the cs bits to 2 bits. This
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+ * still allows all 4 native chip selects to work as well as gpio chip selects
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+ * (which can use any of the 4 chip select configurations).
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+ */
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+
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 #define MX51_ECSPI_CTRL		0x08
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 #define MX51_ECSPI_CTRL_ENABLE		(1 <<  0)
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 #define MX51_ECSPI_CTRL_XCH		(1 <<  2)
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@@ -250,16 +262,16 @@
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 #define MX51_ECSPI_CTRL_DRCTL(drctl)	((drctl) << 16)
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 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET	8
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 #define MX51_ECSPI_CTRL_PREDIV_OFFSET	12
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-#define MX51_ECSPI_CTRL_CS(cs)		((cs) << 18)
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+#define MX51_ECSPI_CTRL_CS(cs)		((cs & 3) << 18)
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 #define MX51_ECSPI_CTRL_BL_OFFSET	20
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 #define MX51_ECSPI_CTRL_BL_MASK		(0xfff << 20)
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 #define MX51_ECSPI_CONFIG	0x0c
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-#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))
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-#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
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-#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
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-#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
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-#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))
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+#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs & 3) +  0))
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+#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs & 3) +  4))
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+#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs & 3) +  8))
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+#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs & 3) + 12))
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+#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs & 3) + 20))
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 #define MX51_ECSPI_INT		0x10
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 #define MX51_ECSPI_INT_TEEN		(1 <<  0)
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@@ -1554,9 +1566,8 @@
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 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
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 	int ret;
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1568
 
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-	ret = pm_runtime_get_sync(spi_imx->dev);
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+	ret = pm_runtime_resume_and_get(spi_imx->dev);
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 	if (ret < 0) {
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-		pm_runtime_put_noidle(spi_imx->dev);
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 		dev_err(spi_imx->dev, "failed to enable clock\n");
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 		return ret;
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 	}
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@@ -1766,13 +1777,10 @@
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 	spi_bitbang_stop(&spi_imx->bitbang);
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 	ret = pm_runtime_get_sync(spi_imx->dev);
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-	if (ret < 0) {
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-		pm_runtime_put_noidle(spi_imx->dev);
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-		dev_err(spi_imx->dev, "failed to enable clock\n");
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-		return ret;
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-	}
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-
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-	writel(0, spi_imx->base + MXC_CSPICTRL);
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+	if (ret >= 0)
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+		writel(0, spi_imx->base + MXC_CSPICTRL);
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+	else
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+		dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n");
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 	pm_runtime_dont_use_autosuspend(spi_imx->dev);
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 	pm_runtime_put_sync(spi_imx->dev);