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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/spi/spi-fsl-spi.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Freescale SPI controller driver.
34  *
....@@ -13,16 +14,11 @@
1314  * GRLIB support:
1415  * Copyright (c) 2012 Aeroflex Gaisler AB.
1516  * Author: Andreas Larsson <andreas@gaisler.com>
16
- *
17
- * This program is free software; you can redistribute  it and/or modify it
18
- * under  the terms of  the GNU General  Public License as published by the
19
- * Free Software Foundation;  either version 2 of the  License, or (at your
20
- * option) any later version.
2117  */
2218 #include <linux/delay.h>
2319 #include <linux/dma-mapping.h>
2420 #include <linux/fsl_devices.h>
25
-#include <linux/gpio.h>
21
+#include <linux/gpio/consumer.h>
2622 #include <linux/interrupt.h>
2723 #include <linux/irq.h>
2824 #include <linux/kernel.h>
....@@ -32,12 +28,19 @@
3228 #include <linux/of.h>
3329 #include <linux/of_address.h>
3430 #include <linux/of_irq.h>
35
-#include <linux/of_gpio.h>
3631 #include <linux/of_platform.h>
3732 #include <linux/platform_device.h>
3833 #include <linux/spi/spi.h>
3934 #include <linux/spi/spi_bitbang.h>
4035 #include <linux/types.h>
36
+
37
+#ifdef CONFIG_FSL_SOC
38
+#include <sysdev/fsl_soc.h>
39
+#endif
40
+
41
+/* Specific to the MPC8306/MPC8309 */
42
+#define IMMR_SPI_CS_OFFSET 0x14c
43
+#define SPI_BOOT_SEL_BIT   0x80000000
4144 
4245 #include "spi-fsl-lib.h"
4346 #include "spi-fsl-cpm.h"
....@@ -87,7 +90,7 @@
8790 {
8891 	struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
8992 	struct spi_mpc8xxx_cs *cs = spi->controller_state;
90
-	struct fsl_spi_reg *reg_base = mspi->reg_base;
93
+	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
9194 	__be32 __iomem *mode = &reg_base->mode;
9295 	unsigned long flags;
9396 
....@@ -112,14 +115,13 @@
112115 {
113116 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
114117 	struct fsl_spi_platform_data *pdata;
115
-	bool pol = spi->mode & SPI_CS_HIGH;
116118 	struct spi_mpc8xxx_cs	*cs = spi->controller_state;
117119 
118120 	pdata = spi->dev.parent->parent->platform_data;
119121 
120122 	if (value == BITBANG_CS_INACTIVE) {
121123 		if (pdata->cs_control)
122
-			pdata->cs_control(spi, !pol);
124
+			pdata->cs_control(spi, false);
123125 	}
124126 
125127 	if (value == BITBANG_CS_ACTIVE) {
....@@ -131,7 +133,7 @@
131133 		fsl_spi_change_mode(spi);
132134 
133135 		if (pdata->cs_control)
134
-			pdata->cs_control(spi, pol);
136
+			pdata->cs_control(spi, true);
135137 	}
136138 }
137139 
....@@ -201,24 +203,6 @@
201203 	return bits_per_word;
202204 }
203205 
204
-static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
205
-				struct spi_device *spi,
206
-				int bits_per_word)
207
-{
208
-	/* QE uses Little Endian for words > 8
209
-	 * so transform all words > 8 into 8 bits
210
-	 * Unfortnatly that doesn't work for LSB so
211
-	 * reject these for now */
212
-	/* Note: 32 bits word, LSB works iff
213
-	 * tfcr/rfcr is set to CPMFCR_GBL */
214
-	if (spi->mode & SPI_LSB_FIRST &&
215
-	    bits_per_word > 8)
216
-		return -EINVAL;
217
-	if (bits_per_word > 8)
218
-		return 8; /* pretend its 8 bits */
219
-	return bits_per_word;
220
-}
221
-
222206 static int fsl_spi_setup_transfer(struct spi_device *spi,
223207 					struct spi_transfer *t)
224208 {
....@@ -246,9 +230,6 @@
246230 		bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
247231 							   mpc8xxx_spi,
248232 							   bits_per_word);
249
-	else if (mpc8xxx_spi->flags & SPI_QE)
250
-		bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
251
-							  bits_per_word);
252233 
253234 	if (bits_per_word < 0)
254235 		return bits_per_word;
....@@ -288,7 +269,7 @@
288269 				struct spi_transfer *t, unsigned int len)
289270 {
290271 	u32 word;
291
-	struct fsl_spi_reg *reg_base = mspi->reg_base;
272
+	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
292273 
293274 	mspi->count = len;
294275 
....@@ -306,7 +287,7 @@
306287 			    bool is_dma_mapped)
307288 {
308289 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
309
-	struct fsl_spi_reg *reg_base;
290
+	struct fsl_spi_reg __iomem *reg_base;
310291 	unsigned int len = t->len;
311292 	u8 bits_per_word;
312293 	int ret;
....@@ -355,33 +336,66 @@
355336 static int fsl_spi_do_one_msg(struct spi_master *master,
356337 			      struct spi_message *m)
357338 {
339
+	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
358340 	struct spi_device *spi = m->spi;
359341 	struct spi_transfer *t, *first;
360342 	unsigned int cs_change;
361343 	const int nsecs = 50;
362
-	int status;
344
+	int status, last_bpw;
345
+
346
+	/*
347
+	 * In CPU mode, optimize large byte transfers to use larger
348
+	 * bits_per_word values to reduce number of interrupts taken.
349
+	 */
350
+	list_for_each_entry(t, &m->transfers, transfer_list) {
351
+		if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
352
+			if (t->len < 256 || t->bits_per_word != 8)
353
+				continue;
354
+			if ((t->len & 3) == 0)
355
+				t->bits_per_word = 32;
356
+			else if ((t->len & 1) == 0)
357
+				t->bits_per_word = 16;
358
+		} else {
359
+			/*
360
+			 * CPM/QE uses Little Endian for words > 8
361
+			 * so transform 16 and 32 bits words into 8 bits
362
+			 * Unfortnatly that doesn't work for LSB so
363
+			 * reject these for now
364
+			 * Note: 32 bits word, LSB works iff
365
+			 * tfcr/rfcr is set to CPMFCR_GBL
366
+			 */
367
+			if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8)
368
+				return -EINVAL;
369
+			if (t->bits_per_word == 16 || t->bits_per_word == 32)
370
+				t->bits_per_word = 8; /* pretend its 8 bits */
371
+			if (t->bits_per_word == 8 && t->len >= 256 &&
372
+			    (mpc8xxx_spi->flags & SPI_CPM1))
373
+				t->bits_per_word = 16;
374
+		}
375
+	}
363376 
364377 	/* Don't allow changes if CS is active */
365
-	first = list_first_entry(&m->transfers, struct spi_transfer,
366
-			transfer_list);
378
+	cs_change = 1;
367379 	list_for_each_entry(t, &m->transfers, transfer_list) {
368
-		if ((first->bits_per_word != t->bits_per_word) ||
369
-			(first->speed_hz != t->speed_hz)) {
380
+		if (cs_change)
381
+			first = t;
382
+		cs_change = t->cs_change;
383
+		if (first->speed_hz != t->speed_hz) {
370384 			dev_err(&spi->dev,
371
-				"bits_per_word/speed_hz should be same for the same SPI transfer\n");
385
+				"speed_hz cannot change while CS is active\n");
372386 			return -EINVAL;
373387 		}
374388 	}
375389 
390
+	last_bpw = -1;
376391 	cs_change = 1;
377392 	status = -EINVAL;
378393 	list_for_each_entry(t, &m->transfers, transfer_list) {
379
-		if (t->bits_per_word || t->speed_hz) {
380
-			if (cs_change)
381
-				status = fsl_spi_setup_transfer(spi, t);
382
-			if (status < 0)
383
-				break;
384
-		}
394
+		if (cs_change || last_bpw != t->bits_per_word)
395
+			status = fsl_spi_setup_transfer(spi, t);
396
+		if (status < 0)
397
+			break;
398
+		last_bpw = t->bits_per_word;
385399 
386400 		if (cs_change) {
387401 			fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
....@@ -396,8 +410,7 @@
396410 		}
397411 		m->actual_length += t->len;
398412 
399
-		if (t->delay_usecs)
400
-			udelay(t->delay_usecs);
413
+		spi_transfer_delay_exec(t);
401414 
402415 		if (cs_change) {
403416 			ndelay(nsecs);
....@@ -421,7 +434,8 @@
421434 static int fsl_spi_setup(struct spi_device *spi)
422435 {
423436 	struct mpc8xxx_spi *mpc8xxx_spi;
424
-	struct fsl_spi_reg *reg_base;
437
+	struct fsl_spi_reg __iomem *reg_base;
438
+	bool initial_setup = false;
425439 	int retval;
426440 	u32 hw_mode;
427441 	struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
....@@ -434,6 +448,7 @@
434448 		if (!cs)
435449 			return -ENOMEM;
436450 		spi_set_ctldata(spi, cs);
451
+		initial_setup = true;
437452 	}
438453 	mpc8xxx_spi = spi_master_get_devdata(spi->master);
439454 
....@@ -457,33 +472,9 @@
457472 	retval = fsl_spi_setup_transfer(spi, NULL);
458473 	if (retval < 0) {
459474 		cs->hw_mode = hw_mode; /* Restore settings */
475
+		if (initial_setup)
476
+			kfree(cs);
460477 		return retval;
461
-	}
462
-
463
-	if (mpc8xxx_spi->type == TYPE_GRLIB) {
464
-		if (gpio_is_valid(spi->cs_gpio)) {
465
-			int desel;
466
-
467
-			retval = gpio_request(spi->cs_gpio,
468
-					      dev_name(&spi->dev));
469
-			if (retval)
470
-				return retval;
471
-
472
-			desel = !(spi->mode & SPI_CS_HIGH);
473
-			retval = gpio_direction_output(spi->cs_gpio, desel);
474
-			if (retval) {
475
-				gpio_free(spi->cs_gpio);
476
-				return retval;
477
-			}
478
-		} else if (spi->cs_gpio != -ENOENT) {
479
-			if (spi->cs_gpio < 0)
480
-				return spi->cs_gpio;
481
-			return -EINVAL;
482
-		}
483
-		/* When spi->cs_gpio == -ENOENT, a hole in the phandle list
484
-		 * indicates to use native chipselect if present, or allow for
485
-		 * an always selected chip
486
-		 */
487478 	}
488479 
489480 	/* Initialize chipselect - might be active for SPI_CS_HIGH mode */
....@@ -494,11 +485,7 @@
494485 
495486 static void fsl_spi_cleanup(struct spi_device *spi)
496487 {
497
-	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
498488 	struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
499
-
500
-	if (mpc8xxx_spi->type == TYPE_GRLIB && gpio_is_valid(spi->cs_gpio))
501
-		gpio_free(spi->cs_gpio);
502489 
503490 	kfree(cs);
504491 	spi_set_ctldata(spi, NULL);
....@@ -506,7 +493,7 @@
506493 
507494 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
508495 {
509
-	struct fsl_spi_reg *reg_base = mspi->reg_base;
496
+	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
510497 
511498 	/* We need handle RX first */
512499 	if (events & SPIE_NE) {
....@@ -541,7 +528,7 @@
541528 	struct mpc8xxx_spi *mspi = context_data;
542529 	irqreturn_t ret = IRQ_NONE;
543530 	u32 events;
544
-	struct fsl_spi_reg *reg_base = mspi->reg_base;
531
+	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
545532 
546533 	/* Get interrupt events(tx/rx) */
547534 	events = mpc8xxx_spi_read_reg(&reg_base->event);
....@@ -561,12 +548,12 @@
561548 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
562549 {
563550 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
564
-	struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
551
+	struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
565552 	u32 slvsel;
566553 	u16 cs = spi->chip_select;
567554 
568
-	if (gpio_is_valid(spi->cs_gpio)) {
569
-		gpio_set_value(spi->cs_gpio, on);
555
+	if (spi->cs_gpiod) {
556
+		gpiod_set_value(spi->cs_gpiod, on);
570557 	} else if (cs < mpc8xxx_spi->native_chipselects) {
571558 		slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
572559 		slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
....@@ -579,7 +566,7 @@
579566 	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
580567 	struct spi_master *master = dev_get_drvdata(dev);
581568 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
582
-	struct fsl_spi_reg *reg_base = mpc8xxx_spi->reg_base;
569
+	struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
583570 	int mbits;
584571 	u32 capabilities;
585572 
....@@ -599,13 +586,13 @@
599586 	pdata->cs_control = fsl_spi_grlib_cs_control;
600587 }
601588 
602
-static struct spi_master * fsl_spi_probe(struct device *dev,
589
+static struct spi_master *fsl_spi_probe(struct device *dev,
603590 		struct resource *mem, unsigned int irq)
604591 {
605592 	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
606593 	struct spi_master *master;
607594 	struct mpc8xxx_spi *mpc8xxx_spi;
608
-	struct fsl_spi_reg *reg_base;
595
+	struct fsl_spi_reg __iomem *reg_base;
609596 	u32 regval;
610597 	int ret = 0;
611598 
....@@ -622,6 +609,7 @@
622609 	master->setup = fsl_spi_setup;
623610 	master->cleanup = fsl_spi_cleanup;
624611 	master->transfer_one_message = fsl_spi_do_one_msg;
612
+	master->use_gpio_descriptors = true;
625613 
626614 	mpc8xxx_spi = spi_master_get_devdata(master);
627615 	mpc8xxx_spi->max_bits_per_word = 32;
....@@ -640,8 +628,14 @@
640628 	if (mpc8xxx_spi->type == TYPE_GRLIB)
641629 		fsl_spi_grlib_probe(dev);
642630 
643
-	master->bits_per_word_mask =
644
-		(SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
631
+	if (mpc8xxx_spi->flags & SPI_CPM_MODE)
632
+		master->bits_per_word_mask =
633
+			(SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32));
634
+	else
635
+		master->bits_per_word_mask =
636
+			(SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32));
637
+
638
+	master->bits_per_word_mask &=
645639 		SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
646640 
647641 	if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
....@@ -697,115 +691,17 @@
697691 
698692 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
699693 {
700
-	struct device *dev = spi->dev.parent->parent;
701
-	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
702
-	struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
703
-	u16 cs = spi->chip_select;
704
-	int gpio = pinfo->gpios[cs];
705
-	bool alow = pinfo->alow_flags[cs];
694
+	if (spi->cs_gpiod) {
695
+		gpiod_set_value(spi->cs_gpiod, on);
696
+	} else {
697
+		struct device *dev = spi->dev.parent->parent;
698
+		struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
699
+		struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
706700 
707
-	gpio_set_value(gpio, on ^ alow);
708
-}
709
-
710
-static int of_fsl_spi_get_chipselects(struct device *dev)
711
-{
712
-	struct device_node *np = dev->of_node;
713
-	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
714
-	struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
715
-	int ngpios;
716
-	int i = 0;
717
-	int ret;
718
-
719
-	ngpios = of_gpio_count(np);
720
-	if (ngpios <= 0) {
721
-		/*
722
-		 * SPI w/o chip-select line. One SPI device is still permitted
723
-		 * though.
724
-		 */
725
-		pdata->max_chipselect = 1;
726
-		return 0;
701
+		if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
702
+			return;
703
+		iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
727704 	}
728
-
729
-	pinfo->gpios = kmalloc_array(ngpios, sizeof(*pinfo->gpios),
730
-				     GFP_KERNEL);
731
-	if (!pinfo->gpios)
732
-		return -ENOMEM;
733
-	memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
734
-
735
-	pinfo->alow_flags = kcalloc(ngpios, sizeof(*pinfo->alow_flags),
736
-				    GFP_KERNEL);
737
-	if (!pinfo->alow_flags) {
738
-		ret = -ENOMEM;
739
-		goto err_alloc_flags;
740
-	}
741
-
742
-	for (; i < ngpios; i++) {
743
-		int gpio;
744
-		enum of_gpio_flags flags;
745
-
746
-		gpio = of_get_gpio_flags(np, i, &flags);
747
-		if (!gpio_is_valid(gpio)) {
748
-			dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
749
-			ret = gpio;
750
-			goto err_loop;
751
-		}
752
-
753
-		ret = gpio_request(gpio, dev_name(dev));
754
-		if (ret) {
755
-			dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
756
-			goto err_loop;
757
-		}
758
-
759
-		pinfo->gpios[i] = gpio;
760
-		pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
761
-
762
-		ret = gpio_direction_output(pinfo->gpios[i],
763
-					    pinfo->alow_flags[i]);
764
-		if (ret) {
765
-			dev_err(dev,
766
-				"can't set output direction for gpio #%d: %d\n",
767
-				i, ret);
768
-			goto err_loop;
769
-		}
770
-	}
771
-
772
-	pdata->max_chipselect = ngpios;
773
-	pdata->cs_control = fsl_spi_cs_control;
774
-
775
-	return 0;
776
-
777
-err_loop:
778
-	while (i >= 0) {
779
-		if (gpio_is_valid(pinfo->gpios[i]))
780
-			gpio_free(pinfo->gpios[i]);
781
-		i--;
782
-	}
783
-
784
-	kfree(pinfo->alow_flags);
785
-	pinfo->alow_flags = NULL;
786
-err_alloc_flags:
787
-	kfree(pinfo->gpios);
788
-	pinfo->gpios = NULL;
789
-	return ret;
790
-}
791
-
792
-static int of_fsl_spi_free_chipselects(struct device *dev)
793
-{
794
-	struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
795
-	struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
796
-	int i;
797
-
798
-	if (!pinfo->gpios)
799
-		return 0;
800
-
801
-	for (i = 0; i < pdata->max_chipselect; i++) {
802
-		if (gpio_is_valid(pinfo->gpios[i]))
803
-			gpio_free(pinfo->gpios[i]);
804
-	}
805
-
806
-	kfree(pinfo->gpios);
807
-	kfree(pinfo->alow_flags);
808
-	return 0;
809705 }
810706 
811707 static int of_fsl_spi_probe(struct platform_device *ofdev)
....@@ -814,8 +710,13 @@
814710 	struct device_node *np = ofdev->dev.of_node;
815711 	struct spi_master *master;
816712 	struct resource mem;
817
-	int irq = 0, type;
818
-	int ret = -ENOMEM;
713
+	int irq, type;
714
+	int ret;
715
+	bool spisel_boot = false;
716
+#if IS_ENABLED(CONFIG_FSL_SOC)
717
+	struct mpc8xxx_spi_probe_info *pinfo = NULL;
718
+#endif
719
+
819720 
820721 	ret = of_mpc8xxx_spi_probe(ofdev);
821722 	if (ret)
....@@ -823,32 +724,54 @@
823724 
824725 	type = fsl_spi_get_type(&ofdev->dev);
825726 	if (type == TYPE_FSL) {
826
-		ret = of_fsl_spi_get_chipselects(dev);
827
-		if (ret)
828
-			goto err;
727
+		struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
728
+#if IS_ENABLED(CONFIG_FSL_SOC)
729
+		pinfo = to_of_pinfo(pdata);
730
+
731
+		spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
732
+		if (spisel_boot) {
733
+			pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
734
+			if (!pinfo->immr_spi_cs)
735
+				return -ENOMEM;
736
+		}
737
+#endif
738
+		/*
739
+		 * Handle the case where we have one hardwired (always selected)
740
+		 * device on the first "chipselect". Else we let the core code
741
+		 * handle any GPIOs or native chip selects and assign the
742
+		 * appropriate callback for dealing with the CS lines. This isn't
743
+		 * supported on the GRLIB variant.
744
+		 */
745
+		ret = gpiod_count(dev, "cs");
746
+		if (ret < 0)
747
+			ret = 0;
748
+		if (ret == 0 && !spisel_boot) {
749
+			pdata->max_chipselect = 1;
750
+		} else {
751
+			pdata->max_chipselect = ret + spisel_boot;
752
+			pdata->cs_control = fsl_spi_cs_control;
753
+		}
829754 	}
830755 
831756 	ret = of_address_to_resource(np, 0, &mem);
832757 	if (ret)
833
-		goto err;
758
+		goto unmap_out;
834759 
835760 	irq = platform_get_irq(ofdev, 0);
836761 	if (irq < 0) {
837762 		ret = irq;
838
-		goto err;
763
+		goto unmap_out;
839764 	}
840765 
841766 	master = fsl_spi_probe(dev, &mem, irq);
842
-	if (IS_ERR(master)) {
843
-		ret = PTR_ERR(master);
844
-		goto err;
845
-	}
846767 
847
-	return 0;
768
+	return PTR_ERR_OR_ZERO(master);
848769 
849
-err:
850
-	if (type == TYPE_FSL)
851
-		of_fsl_spi_free_chipselects(dev);
770
+unmap_out:
771
+#if IS_ENABLED(CONFIG_FSL_SOC)
772
+	if (spisel_boot)
773
+		iounmap(pinfo->immr_spi_cs);
774
+#endif
852775 	return ret;
853776 }
854777 
....@@ -858,8 +781,6 @@
858781 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
859782 
860783 	fsl_spi_cpm_free(mpc8xxx_spi);
861
-	if (mpc8xxx_spi->type == TYPE_FSL)
862
-		of_fsl_spi_free_chipselects(&ofdev->dev);
863784 	return 0;
864785 }
865786