~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,8 +1,7 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* QLogic Fibre Channel HBA Driver
3	4	* Copyright (c) 2003-2014 QLogic Corporation
4		- *
5		- * See LICENSE.qla2xxx for copyright and licensing details.
6	5	*/
7	6	#include "qla_def.h"
8	7
..	..	@@ -26,24 +25,24 @@
26	25	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
27	26
28	27	if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
29		- data = RD_REG_WORD(&reg->nvram);
	28	+ data = rd_reg_word(&reg->nvram);
30	29	while (data & NVR_BUSY) {
31	30	udelay(100);
32		- data = RD_REG_WORD(&reg->nvram);
	31	+ data = rd_reg_word(&reg->nvram);
33	32	}
34	33
35	34	/* Lock resource */
36		- WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
37		- RD_REG_WORD(&reg->u.isp2300.host_semaphore);
	35	+ wrt_reg_word(&reg->u.isp2300.host_semaphore, 0x1);
	36	+ rd_reg_word(&reg->u.isp2300.host_semaphore);
38	37	udelay(5);
39		- data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
	38	+ data = rd_reg_word(&reg->u.isp2300.host_semaphore);
40	39	while ((data & BIT_0) == 0) {
41	40	/* Lock failed */
42	41	udelay(100);
43		- WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
44		- RD_REG_WORD(&reg->u.isp2300.host_semaphore);
	42	+ wrt_reg_word(&reg->u.isp2300.host_semaphore, 0x1);
	43	+ rd_reg_word(&reg->u.isp2300.host_semaphore);
45	44	udelay(5);
46		- data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
	45	+ data = rd_reg_word(&reg->u.isp2300.host_semaphore);
47	46	}
48	47	}
49	48	}
..	..	@@ -58,8 +57,8 @@
58	57	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
59	58
60	59	if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
61		- WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
62		- RD_REG_WORD(&reg->u.isp2300.host_semaphore);
	60	+ wrt_reg_word(&reg->u.isp2300.host_semaphore, 0);
	61	+ rd_reg_word(&reg->u.isp2300.host_semaphore);
63	62	}
64	63	}
65	64
..	..	@@ -73,15 +72,15 @@
73	72	{
74	73	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
75	74
76		- WRT_REG_WORD(&reg->nvram, data \| NVR_SELECT \| NVR_WRT_ENABLE);
77		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	75	+ wrt_reg_word(&reg->nvram, data \| NVR_SELECT \| NVR_WRT_ENABLE);
	76	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
78	77	NVRAM_DELAY();
79		- WRT_REG_WORD(&reg->nvram, data \| NVR_SELECT \| NVR_CLOCK \|
	78	+ wrt_reg_word(&reg->nvram, data \| NVR_SELECT \| NVR_CLOCK \|
80	79	NVR_WRT_ENABLE);
81		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	80	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
82	81	NVRAM_DELAY();
83		- WRT_REG_WORD(&reg->nvram, data \| NVR_SELECT \| NVR_WRT_ENABLE);
84		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	82	+ wrt_reg_word(&reg->nvram, data \| NVR_SELECT \| NVR_WRT_ENABLE);
	83	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
85	84	NVRAM_DELAY();
86	85	}
87	86
..	..	@@ -120,21 +119,21 @@
120	119
121	120	/* Read data from NVRAM. */
122	121	for (cnt = 0; cnt < 16; cnt++) {
123		- WRT_REG_WORD(&reg->nvram, NVR_SELECT \| NVR_CLOCK);
124		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	122	+ wrt_reg_word(&reg->nvram, NVR_SELECT \| NVR_CLOCK);
	123	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
125	124	NVRAM_DELAY();
126	125	data <<= 1;
127		- reg_data = RD_REG_WORD(&reg->nvram);
	126	+ reg_data = rd_reg_word(&reg->nvram);
128	127	if (reg_data & NVR_DATA_IN)
129	128	data \|= BIT_0;
130		- WRT_REG_WORD(&reg->nvram, NVR_SELECT);
131		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	129	+ wrt_reg_word(&reg->nvram, NVR_SELECT);
	130	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
132	131	NVRAM_DELAY();
133	132	}
134	133
135	134	/* Deselect chip. */
136		- WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
137		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	135	+ wrt_reg_word(&reg->nvram, NVR_DESELECT);
	136	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
138	137	NVRAM_DELAY();
139	138
140	139	return data;
..	..	@@ -171,8 +170,8 @@
171	170	{
172	171	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
173	172
174		- WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
175		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	173	+ wrt_reg_word(&reg->nvram, NVR_DESELECT);
	174	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
176	175	NVRAM_DELAY();
177	176	}
178	177
..	..	@@ -183,7 +182,7 @@
183	182	* @data: word to program
184	183	*/
185	184	static void
186		-qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
	185	+qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, __le16 data)
187	186	{
188	187	int count;
189	188	uint16_t word;
..	..	@@ -202,7 +201,7 @@
202	201
203	202	/* Write data */
204	203	nv_cmd = (addr << 16) \| NV_WRITE_OP;
205		- nv_cmd \|= data;
	204	+ nv_cmd \|= (__force u16)data;
206	205	nv_cmd <<= 5;
207	206	for (count = 0; count < 27; count++) {
208	207	if (nv_cmd & BIT_31)
..	..	@@ -216,8 +215,8 @@
216	215	qla2x00_nv_deselect(ha);
217	216
218	217	/* Wait for NVRAM to become ready */
219		- WRT_REG_WORD(&reg->nvram, NVR_SELECT);
220		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	218	+ wrt_reg_word(&reg->nvram, NVR_SELECT);
	219	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
221	220	wait_cnt = NVR_WAIT_CNT;
222	221	do {
223	222	if (!--wait_cnt) {
..	..	@@ -226,7 +225,7 @@
226	225	break;
227	226	}
228	227	NVRAM_DELAY();
229		- word = RD_REG_WORD(&reg->nvram);
	228	+ word = rd_reg_word(&reg->nvram);
230	229	} while ((word & NVR_DATA_IN) == 0);
231	230
232	231	qla2x00_nv_deselect(ha);
..	..	@@ -241,7 +240,7 @@
241	240
242	241	static int
243	242	qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
244		- uint16_t data, uint32_t tmo)
	243	+ __le16 data, uint32_t tmo)
245	244	{
246	245	int ret, count;
247	246	uint16_t word;
..	..	@@ -261,7 +260,7 @@
261	260
262	261	/* Write data */
263	262	nv_cmd = (addr << 16) \| NV_WRITE_OP;
264		- nv_cmd \|= data;
	263	+ nv_cmd \|= (__force u16)data;
265	264	nv_cmd <<= 5;
266	265	for (count = 0; count < 27; count++) {
267	266	if (nv_cmd & BIT_31)
..	..	@@ -275,11 +274,11 @@
275	274	qla2x00_nv_deselect(ha);
276	275
277	276	/* Wait for NVRAM to become ready */
278		- WRT_REG_WORD(&reg->nvram, NVR_SELECT);
279		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	277	+ wrt_reg_word(&reg->nvram, NVR_SELECT);
	278	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
280	279	do {
281	280	NVRAM_DELAY();
282		- word = RD_REG_WORD(&reg->nvram);
	281	+ word = rd_reg_word(&reg->nvram);
283	282	if (!--tmo) {
284	283	ret = QLA_FUNCTION_FAILED;
285	284	break;
..	..	@@ -308,7 +307,7 @@
308	307	int ret, stat;
309	308	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
310	309	uint32_t word, wait_cnt;
311		- uint16_t wprot, wprot_old;
	310	+ __le16 wprot, wprot_old;
312	311	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
313	312
314	313	/* Clear NVRAM write protection. */
..	..	@@ -318,7 +317,7 @@
318	317	stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
319	318	cpu_to_le16(0x1234), 100000);
320	319	wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
321		- if (stat != QLA_SUCCESS \|\| wprot != 0x1234) {
	320	+ if (stat != QLA_SUCCESS \|\| wprot != cpu_to_le16(0x1234)) {
322	321	/* Write enable. */
323	322	qla2x00_nv_write(ha, NVR_DATA_OUT);
324	323	qla2x00_nv_write(ha, 0);
..	..	@@ -347,8 +346,8 @@
347	346	qla2x00_nv_deselect(ha);
348	347
349	348	/* Wait for NVRAM to become ready. */
350		- WRT_REG_WORD(&reg->nvram, NVR_SELECT);
351		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	349	+ wrt_reg_word(&reg->nvram, NVR_SELECT);
	350	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
352	351	wait_cnt = NVR_WAIT_CNT;
353	352	do {
354	353	if (!--wait_cnt) {
..	..	@@ -357,7 +356,7 @@
357	356	break;
358	357	}
359	358	NVRAM_DELAY();
360		- word = RD_REG_WORD(&reg->nvram);
	359	+ word = rd_reg_word(&reg->nvram);
361	360	} while ((word & NVR_DATA_IN) == 0);
362	361
363	362	if (wait_cnt)
..	..	@@ -407,8 +406,8 @@
407	406	qla2x00_nv_deselect(ha);
408	407
409	408	/* Wait for NVRAM to become ready. */
410		- WRT_REG_WORD(&reg->nvram, NVR_SELECT);
411		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	409	+ wrt_reg_word(&reg->nvram, NVR_SELECT);
	410	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
412	411	wait_cnt = NVR_WAIT_CNT;
413	412	do {
414	413	if (!--wait_cnt) {
..	..	@@ -417,7 +416,7 @@
417	416	break;
418	417	}
419	418	NVRAM_DELAY();
420		- word = RD_REG_WORD(&reg->nvram);
	419	+ word = rd_reg_word(&reg->nvram);
421	420	} while ((word & NVR_DATA_IN) == 0);
422	421	}
423	422
..	..	@@ -429,102 +428,104 @@
429	428	static inline uint32_t
430	429	flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
431	430	{
432		- return ha->flash_conf_off \| faddr;
	431	+ return ha->flash_conf_off + faddr;
433	432	}
434	433
435	434	static inline uint32_t
436	435	flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
437	436	{
438		- return ha->flash_data_off \| faddr;
	437	+ return ha->flash_data_off + faddr;
439	438	}
440	439
441	440	static inline uint32_t
442	441	nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
443	442	{
444		- return ha->nvram_conf_off \| naddr;
	443	+ return ha->nvram_conf_off + naddr;
445	444	}
446	445
447	446	static inline uint32_t
448	447	nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
449	448	{
450		- return ha->nvram_data_off \| naddr;
	449	+ return ha->nvram_data_off + naddr;
451	450	}
452	451
453		-static uint32_t
454		-qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
	452	+static int
	453	+qla24xx_read_flash_dword(struct qla_hw_data ha, uint32_t addr, uint32_t data)
455	454	{
456		- int rval;
457		- uint32_t cnt, data;
458	455	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
	456	+ ulong cnt = 30000;
459	457
460		- WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
461		- /* Wait for READ cycle to complete. */
462		- rval = QLA_SUCCESS;
463		- for (cnt = 3000;
464		- (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
465		- rval == QLA_SUCCESS; cnt--) {
466		- if (cnt)
467		- udelay(10);
468		- else
469		- rval = QLA_FUNCTION_TIMEOUT;
	458	+ wrt_reg_dword(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
	459	+
	460	+ while (cnt--) {
	461	+ if (rd_reg_dword(&reg->flash_addr) & FARX_DATA_FLAG) {
	462	+ *data = rd_reg_dword(&reg->flash_data);
	463	+ return QLA_SUCCESS;
	464	+ }
	465	+ udelay(10);
470	466	cond_resched();
471	467	}
472	468
473		- /* TODO: What happens if we time out? */
474		- data = 0xDEADDEAD;
475		- if (rval == QLA_SUCCESS)
476		- data = RD_REG_DWORD(&reg->flash_data);
477		-
478		- return data;
	469	+ ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090,
	470	+ "Flash read dword at %x timeout.\n", addr);
	471	+ *data = 0xDEADDEAD;
	472	+ return QLA_FUNCTION_TIMEOUT;
479	473	}
480	474
481		-uint32_t *
	475	+int
482	476	qla24xx_read_flash_data(scsi_qla_host_t vha, uint32_t dwptr, uint32_t faddr,
483	477	uint32_t dwords)
484	478	{
485		- uint32_t i;
	479	+ ulong i;
	480	+ int ret = QLA_SUCCESS;
486	481	struct qla_hw_data *ha = vha->hw;
487	482
488	483	/* Dword reads to flash. */
489		- for (i = 0; i < dwords; i++, faddr++)
490		- dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
491		- flash_data_addr(ha, faddr)));
	484	+ faddr = flash_data_addr(ha, faddr);
	485	+ for (i = 0; i < dwords; i++, faddr++, dwptr++) {
	486	+ ret = qla24xx_read_flash_dword(ha, faddr, dwptr);
	487	+ if (ret != QLA_SUCCESS)
	488	+ break;
	489	+ cpu_to_le32s(dwptr);
	490	+ }
492	491
493		- return dwptr;
	492	+ return ret;
494	493	}
495	494
496	495	static int
497	496	qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
498	497	{
499		- int rval;
500		- uint32_t cnt;
501	498	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
	499	+ ulong cnt = 500000;
502	500
503		- WRT_REG_DWORD(&reg->flash_data, data);
504		- RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
505		- WRT_REG_DWORD(&reg->flash_addr, addr \| FARX_DATA_FLAG);
506		- /* Wait for Write cycle to complete. */
507		- rval = QLA_SUCCESS;
508		- for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
509		- rval == QLA_SUCCESS; cnt--) {
510		- if (cnt)
511		- udelay(10);
512		- else
513		- rval = QLA_FUNCTION_TIMEOUT;
	501	+ wrt_reg_dword(&reg->flash_data, data);
	502	+ wrt_reg_dword(&reg->flash_addr, addr \| FARX_DATA_FLAG);
	503	+
	504	+ while (cnt--) {
	505	+ if (!(rd_reg_dword(&reg->flash_addr) & FARX_DATA_FLAG))
	506	+ return QLA_SUCCESS;
	507	+ udelay(10);
514	508	cond_resched();
515	509	}
516		- return rval;
	510	+
	511	+ ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090,
	512	+ "Flash write dword at %x timeout.\n", addr);
	513	+ return QLA_FUNCTION_TIMEOUT;
517	514	}
518	515
519	516	static void
520	517	qla24xx_get_flash_manufacturer(struct qla_hw_data ha, uint8_t man_id,
521	518	uint8_t *flash_id)
522	519	{
523		- uint32_t ids;
	520	+ uint32_t faddr, ids = 0;
524	521
525		- ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
526		- *man_id = LSB(ids);
527		- *flash_id = MSB(ids);
	522	+ man_id = flash_id = 0;
	523	+
	524	+ faddr = flash_conf_addr(ha, 0x03ab);
	525	+ if (!qla24xx_read_flash_dword(ha, faddr, &ids)) {
	526	+ *man_id = LSB(ids);
	527	+ *flash_id = MSB(ids);
	528	+ }
528	529
529	530	/* Check if man_id and flash_id are valid. */
530	531	if (ids != 0xDEADDEAD && (man_id == 0 \|\| flash_id == 0)) {
..	..	@@ -534,9 +535,11 @@
534	535	* Example: ATMEL 0x00 01 45 1F
535	536	* Extract MFG and Dev ID from last two bytes.
536	537	*/
537		- ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
538		- *man_id = LSB(ids);
539		- *flash_id = MSB(ids);
	538	+ faddr = flash_conf_addr(ha, 0x009f);
	539	+ if (!qla24xx_read_flash_dword(ha, faddr, &ids)) {
	540	+ *man_id = LSB(ids);
	541	+ *flash_id = MSB(ids);
	542	+ }
540	543	}
541	544	}
542	545
..	..	@@ -545,12 +548,13 @@
545	548	{
546	549	const char loc, locations[] = { "DEF", "PCI" };
547	550	uint32_t pcihdr, pcids;
548		- uint32_t *dcode;
549		- uint8_t buf, bcode, last_image;
550		- uint16_t cnt, chksum, *wptr;
551		- struct qla_flt_location *fltl;
	551	+ uint16_t cnt, chksum;
	552	+ __le16 *wptr;
552	553	struct qla_hw_data *ha = vha->hw;
553	554	struct req_que *req = ha->req_q_map[0];
	555	+ struct qla_flt_location fltl = (void )req->ring;
	556	+ uint32_t dcode = (uint32_t )req->ring;
	557	+ uint8_t buf = (void )req->ring, *bcode, last_image;
554	558
555	559	/*
556	560	* FLT-location structure resides after the last PCI region.
..	..	@@ -571,12 +575,13 @@
571	575	} else if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) {
572	576	*start = FA_FLASH_LAYOUT_ADDR_83;
573	577	goto end;
	578	+ } else if (IS_QLA28XX(ha)) {
	579	+ *start = FA_FLASH_LAYOUT_ADDR_28;
	580	+ goto end;
574	581	}
	582	+
575	583	/* Begin with first PCI expansion ROM header. */
576		- buf = (uint8_t *)req->ring;
577		- dcode = (uint32_t *)req->ring;
578	584	pcihdr = 0;
579		- last_image = 1;
580	585	do {
581	586	/* Verify PCI expansion ROM header. */
582	587	qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
..	..	@@ -601,22 +606,19 @@
601	606	} while (!last_image);
602	607
603	608	/* Now verify FLT-location structure. */
604		- fltl = (struct qla_flt_location *)req->ring;
605		- qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
606		- sizeof(struct qla_flt_location) >> 2);
607		- if (fltl->sig[0] != 'Q' \|\| fltl->sig[1] != 'F' \|\|
608		- fltl->sig[2] != 'L' \|\| fltl->sig[3] != 'T')
	609	+ qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, sizeof(*fltl) >> 2);
	610	+ if (memcmp(fltl->sig, "QFLT", 4))
609	611	goto end;
610	612
611		- wptr = (uint16_t *)req->ring;
612		- cnt = sizeof(struct qla_flt_location) >> 1;
	613	+ wptr = (__force __le16 *)req->ring;
	614	+ cnt = sizeof(fltl) / sizeof(wptr);
613	615	for (chksum = 0; cnt--; wptr++)
614	616	chksum += le16_to_cpu(*wptr);
615	617	if (chksum) {
616	618	ql_log(ql_log_fatal, vha, 0x0045,
617	619	"Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
618	620	ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
619		- buf, sizeof(struct qla_flt_location));
	621	+ fltl, sizeof(*fltl));
620	622	return QLA_FUNCTION_FAILED;
621	623	}
622	624
..	..	@@ -634,7 +636,7 @@
634	636	static void
635	637	qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
636	638	{
637		- const char loc, locations[] = { "DEF", "FLT" };
	639	+ const char locations[] = { "DEF", "FLT" }, loc = locations[1];
638	640	const uint32_t def_fw[] =
639	641	{ FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
640	642	const uint32_t def_boot[] =
..	..	@@ -664,20 +666,14 @@
664	666	const uint32_t fcp_prio_cfg1[] =
665	667	{ FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
666	668	0 };
667		- uint32_t def;
668		- uint16_t *wptr;
	669	+
	670	+ struct qla_hw_data *ha = vha->hw;
	671	+ uint32_t def = IS_QLA81XX(ha) ? 2 : IS_QLA25XX(ha) ? 1 : 0;
	672	+ struct qla_flt_header *flt = ha->flt;
	673	+ struct qla_flt_region *region = &flt->region[0];
	674	+ __le16 *wptr;
669	675	uint16_t cnt, chksum;
670	676	uint32_t start;
671		- struct qla_flt_header *flt;
672		- struct qla_flt_region *region;
673		- struct qla_hw_data *ha = vha->hw;
674		- struct req_que *req = ha->req_q_map[0];
675		-
676		- def = 0;
677		- if (IS_QLA25XX(ha))
678		- def = 1;
679		- else if (IS_QLA81XX(ha))
680		- def = 2;
681	677
682	678	/* Assign FCP prio region since older adapters may not have FLT, or
683	679	FCP prio region in it's FLT.
..	..	@@ -686,12 +682,11 @@
686	682	fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
687	683
688	684	ha->flt_region_flt = flt_addr;
689		- wptr = (uint16_t *)req->ring;
690		- flt = (struct qla_flt_header *)req->ring;
691		- region = (struct qla_flt_region *)&flt[1];
692		- ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
693		- flt_addr << 2, OPTROM_BURST_SIZE);
694		- if (*wptr == cpu_to_le16(0xffff))
	685	+ wptr = (__force __le16 *)ha->flt;
	686	+ ha->isp_ops->read_optrom(vha, flt, flt_addr << 2,
	687	+ (sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE));
	688	+
	689	+ if (le16_to_cpu(*wptr) == 0xffff)
695	690	goto no_flash_data;
696	691	if (flt->version != cpu_to_le16(1)) {
697	692	ql_log(ql_log_warn, vha, 0x0047,
..	..	@@ -701,7 +696,7 @@
701	696	goto no_flash_data;
702	697	}
703	698
704		- cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
	699	+ cnt = (sizeof(flt) + le16_to_cpu(flt->length)) / sizeof(wptr);
705	700	for (chksum = 0; cnt--; wptr++)
706	701	chksum += le16_to_cpu(*wptr);
707	702	if (chksum) {
..	..	@@ -712,18 +707,20 @@
712	707	goto no_flash_data;
713	708	}
714	709
715		- loc = locations[1];
716		- cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
	710	+ cnt = le16_to_cpu(flt->length) / sizeof(*region);
717	711	for ( ; cnt; cnt--, region++) {
718	712	/* Store addresses as DWORD offsets. */
719	713	start = le32_to_cpu(region->start) >> 2;
720	714	ql_dbg(ql_dbg_init, vha, 0x0049,
721		- "FLT[%02x]: start=0x%x "
722		- "end=0x%x size=0x%x.\n", le32_to_cpu(region->code) & 0xff,
723		- start, le32_to_cpu(region->end) >> 2,
724		- le32_to_cpu(region->size));
	715	+ "FLT[%#x]: start=%#x end=%#x size=%#x.\n",
	716	+ le16_to_cpu(region->code), start,
	717	+ le32_to_cpu(region->end) >> 2,
	718	+ le32_to_cpu(region->size) >> 2);
	719	+ if (region->attribute)
	720	+ ql_log(ql_dbg_init, vha, 0xffff,
	721	+ "Region %x is secure\n", region->code);
725	722
726		- switch (le32_to_cpu(region->code) & 0xff) {
	723	+ switch (le16_to_cpu(region->code)) {
727	724	case FLT_REG_FCOE_FW:
728	725	if (!IS_QLA8031(ha))
729	726	break;
..	..	@@ -753,13 +750,13 @@
753	750	ha->flt_region_vpd = start;
754	751	break;
755	752	case FLT_REG_VPD_2:
756		- if (!IS_QLA27XX(ha))
	753	+ if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
757	754	break;
758	755	if (ha->port_no == 2)
759	756	ha->flt_region_vpd = start;
760	757	break;
761	758	case FLT_REG_VPD_3:
762		- if (!IS_QLA27XX(ha))
	759	+ if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
763	760	break;
764	761	if (ha->port_no == 3)
765	762	ha->flt_region_vpd = start;
..	..	@@ -777,13 +774,13 @@
777	774	ha->flt_region_nvram = start;
778	775	break;
779	776	case FLT_REG_NVRAM_2:
780		- if (!IS_QLA27XX(ha))
	777	+ if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
781	778	break;
782	779	if (ha->port_no == 2)
783	780	ha->flt_region_nvram = start;
784	781	break;
785	782	case FLT_REG_NVRAM_3:
786		- if (!IS_QLA27XX(ha))
	783	+ if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
787	784	break;
788	785	if (ha->port_no == 3)
789	786	ha->flt_region_nvram = start;
..	..	@@ -847,36 +844,74 @@
847	844	ha->flt_region_nvram = start;
848	845	break;
849	846	case FLT_REG_IMG_PRI_27XX:
850		- if (IS_QLA27XX(ha))
	847	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
851	848	ha->flt_region_img_status_pri = start;
852	849	break;
853	850	case FLT_REG_IMG_SEC_27XX:
854		- if (IS_QLA27XX(ha))
	851	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
855	852	ha->flt_region_img_status_sec = start;
856	853	break;
857	854	case FLT_REG_FW_SEC_27XX:
858		- if (IS_QLA27XX(ha))
	855	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
859	856	ha->flt_region_fw_sec = start;
860	857	break;
861	858	case FLT_REG_BOOTLOAD_SEC_27XX:
862		- if (IS_QLA27XX(ha))
	859	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
863	860	ha->flt_region_boot_sec = start;
864	861	break;
	862	+ case FLT_REG_AUX_IMG_PRI_28XX:
	863	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	864	+ ha->flt_region_aux_img_status_pri = start;
	865	+ break;
	866	+ case FLT_REG_AUX_IMG_SEC_28XX:
	867	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	868	+ ha->flt_region_aux_img_status_sec = start;
	869	+ break;
	870	+ case FLT_REG_NVRAM_SEC_28XX_0:
	871	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	872	+ if (ha->port_no == 0)
	873	+ ha->flt_region_nvram_sec = start;
	874	+ break;
	875	+ case FLT_REG_NVRAM_SEC_28XX_1:
	876	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	877	+ if (ha->port_no == 1)
	878	+ ha->flt_region_nvram_sec = start;
	879	+ break;
	880	+ case FLT_REG_NVRAM_SEC_28XX_2:
	881	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	882	+ if (ha->port_no == 2)
	883	+ ha->flt_region_nvram_sec = start;
	884	+ break;
	885	+ case FLT_REG_NVRAM_SEC_28XX_3:
	886	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	887	+ if (ha->port_no == 3)
	888	+ ha->flt_region_nvram_sec = start;
	889	+ break;
865	890	case FLT_REG_VPD_SEC_27XX_0:
866		- if (IS_QLA27XX(ha))
867		- ha->flt_region_vpd_sec = start;
	891	+ case FLT_REG_VPD_SEC_28XX_0:
	892	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
	893	+ ha->flt_region_vpd_nvram_sec = start;
	894	+ if (ha->port_no == 0)
	895	+ ha->flt_region_vpd_sec = start;
	896	+ }
868	897	break;
869	898	case FLT_REG_VPD_SEC_27XX_1:
870		- if (IS_QLA27XX(ha))
871		- ha->flt_region_vpd_sec = start;
	899	+ case FLT_REG_VPD_SEC_28XX_1:
	900	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	901	+ if (ha->port_no == 1)
	902	+ ha->flt_region_vpd_sec = start;
872	903	break;
873	904	case FLT_REG_VPD_SEC_27XX_2:
874		- if (IS_QLA27XX(ha))
875		- ha->flt_region_vpd_sec = start;
	905	+ case FLT_REG_VPD_SEC_28XX_2:
	906	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	907	+ if (ha->port_no == 2)
	908	+ ha->flt_region_vpd_sec = start;
876	909	break;
877	910	case FLT_REG_VPD_SEC_27XX_3:
878		- if (IS_QLA27XX(ha))
879		- ha->flt_region_vpd_sec = start;
	911	+ case FLT_REG_VPD_SEC_28XX_3:
	912	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	913	+ if (ha->port_no == 3)
	914	+ ha->flt_region_vpd_sec = start;
880	915	break;
881	916	}
882	917	}
..	..	@@ -912,22 +947,19 @@
912	947	#define FLASH_BLK_SIZE_32K 0x8000
913	948	#define FLASH_BLK_SIZE_64K 0x10000
914	949	const char loc, locations[] = { "MID", "FDT" };
915		- uint16_t cnt, chksum;
916		- uint16_t *wptr;
917		- struct qla_fdt_layout *fdt;
918		- uint8_t man_id, flash_id;
919		- uint16_t mid = 0, fid = 0;
920	950	struct qla_hw_data *ha = vha->hw;
921	951	struct req_que *req = ha->req_q_map[0];
	952	+ uint16_t cnt, chksum;
	953	+ __le16 wptr = (__force __le16 )req->ring;
	954	+ struct qla_fdt_layout fdt = (struct qla_fdt_layout )req->ring;
	955	+ uint8_t man_id, flash_id;
	956	+ uint16_t mid = 0, fid = 0;
922	957
923		- wptr = (uint16_t *)req->ring;
924		- fdt = (struct qla_fdt_layout *)req->ring;
925		- ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
926		- ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
927		- if (*wptr == cpu_to_le16(0xffff))
	958	+ ha->isp_ops->read_optrom(vha, fdt, ha->flt_region_fdt << 2,
	959	+ OPTROM_BURST_DWORDS);
	960	+ if (le16_to_cpu(*wptr) == 0xffff)
928	961	goto no_flash_data;
929		- if (fdt->sig[0] != 'Q' \|\| fdt->sig[1] != 'L' \|\| fdt->sig[2] != 'I' \|\|
930		- fdt->sig[3] != 'D')
	962	+ if (memcmp(fdt->sig, "QLID", 4))
931	963	goto no_flash_data;
932	964
933	965	for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++)
..	..	@@ -938,7 +970,7 @@
938	970	" checksum=0x%x id=%c version0x%x.\n", chksum,
939	971	fdt->sig[0], le16_to_cpu(fdt->version));
940	972	ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
941		- (uint8_t )fdt, sizeof(fdt));
	973	+ fdt, sizeof(*fdt));
942	974	goto no_flash_data;
943	975	}
944	976
..	..	@@ -958,7 +990,7 @@
958	990	ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 \|
959	991	fdt->unprotect_sec_cmd);
960	992	ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
961		- flash_conf_addr(ha, 0x0300 \| fdt->protect_sec_cmd):
	993	+ flash_conf_addr(ha, 0x0300 \| fdt->protect_sec_cmd) :
962	994	flash_conf_addr(ha, 0x0336);
963	995	}
964	996	goto done;
..	..	@@ -1011,16 +1043,15 @@
1011	1043	qla2xxx_get_idc_param(scsi_qla_host_t *vha)
1012	1044	{
1013	1045	#define QLA82XX_IDC_PARAM_ADDR 0x003e885c
1014		- uint32_t *wptr;
	1046	+ __le32 *wptr;
1015	1047	struct qla_hw_data *ha = vha->hw;
1016	1048	struct req_que *req = ha->req_q_map[0];
1017	1049
1018	1050	if (!(IS_P3P_TYPE(ha)))
1019	1051	return;
1020	1052
1021		- wptr = (uint32_t *)req->ring;
1022		- ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
1023		- QLA82XX_IDC_PARAM_ADDR , 8);
	1053	+ wptr = (__force __le32 *)req->ring;
	1054	+ ha->isp_ops->read_optrom(vha, req->ring, QLA82XX_IDC_PARAM_ADDR, 8);
1024	1055
1025	1056	if (*wptr == cpu_to_le32(0xffffffff)) {
1026	1057	ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
..	..	@@ -1045,7 +1076,8 @@
1045	1076	struct qla_hw_data *ha = vha->hw;
1046	1077
1047	1078	if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1048		- !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLA27XX(ha))
	1079	+ !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) &&
	1080	+ !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
1049	1081	return QLA_SUCCESS;
1050	1082
1051	1083	ret = qla2xxx_find_flt_start(vha, &flt_addr);
..	..	@@ -1064,7 +1096,7 @@
1064	1096	{
1065	1097	#define NPIV_CONFIG_SIZE (16*1024)
1066	1098	void *data;
1067		- uint16_t *wptr;
	1099	+ __le16 *wptr;
1068	1100	uint16_t cnt, chksum;
1069	1101	int i;
1070	1102	struct qla_npiv_header hdr;
..	..	@@ -1081,8 +1113,8 @@
1081	1113	if (IS_QLA8044(ha))
1082	1114	return;
1083	1115
1084		- ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
1085		- ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
	1116	+ ha->isp_ops->read_optrom(vha, &hdr, ha->flt_region_npiv_conf << 2,
	1117	+ sizeof(struct qla_npiv_header));
1086	1118	if (hdr.version == cpu_to_le16(0xffff))
1087	1119	return;
1088	1120	if (hdr.version != cpu_to_le16(1)) {
..	..	@@ -1101,8 +1133,8 @@
1101	1133	return;
1102	1134	}
1103	1135
1104		- ha->isp_ops->read_optrom(vha, (uint8_t *)data,
1105		- ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
	1136	+ ha->isp_ops->read_optrom(vha, data, ha->flt_region_npiv_conf << 2,
	1137	+ NPIV_CONFIG_SIZE);
1106	1138
1107	1139	cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1;
1108	1140	for (wptr = data, chksum = 0; cnt--; wptr++)
..	..	@@ -1139,10 +1171,8 @@
1139	1171	vid.node_name = wwn_to_u64(entry->node_name);
1140	1172
1141	1173	ql_dbg(ql_dbg_user, vha, 0x7093,
1142		- "NPIV[%02x]: wwpn=%llx "
1143		- "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
1144		- (unsigned long long)vid.port_name,
1145		- (unsigned long long)vid.node_name,
	1174	+ "NPIV[%02x]: wwpn=%llx wwnn=%llx vf_id=%#x Q_qos=%#x F_qos=%#x.\n",
	1175	+ cnt, vid.port_name, vid.node_name,
1146	1176	le16_to_cpu(entry->vf_id),
1147	1177	entry->q_qos, entry->f_qos);
1148	1178
..	..	@@ -1150,10 +1180,8 @@
1150	1180	vport = fc_vport_create(vha->host, 0, &vid);
1151	1181	if (!vport)
1152	1182	ql_log(ql_log_warn, vha, 0x7094,
1153		- "NPIV-Config Failed to create vport [%02x]: "
1154		- "wwpn=%llx wwnn=%llx.\n", cnt,
1155		- (unsigned long long)vid.port_name,
1156		- (unsigned long long)vid.node_name);
	1183	+ "NPIV-Config Failed to create vport [%02x]: wwpn=%llx wwnn=%llx.\n",
	1184	+ cnt, vid.port_name, vid.node_name);
1157	1185	}
1158	1186	}
1159	1187	done:
..	..	@@ -1170,9 +1198,9 @@
1170	1198	return qla81xx_fac_do_write_enable(vha, 1);
1171	1199
1172	1200	/* Enable flash write. */
1173		- WRT_REG_DWORD(&reg->ctrl_status,
1174		- RD_REG_DWORD(&reg->ctrl_status) \| CSRX_FLASH_ENABLE);
1175		- RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
	1201	+ wrt_reg_dword(&reg->ctrl_status,
	1202	+ rd_reg_dword(&reg->ctrl_status) \| CSRX_FLASH_ENABLE);
	1203	+ rd_reg_dword(&reg->ctrl_status); /* PCI Posting. */
1176	1204
1177	1205	if (!ha->fdt_wrt_disable)
1178	1206	goto done;
..	..	@@ -1188,9 +1216,10 @@
1188	1216	static int
1189	1217	qla24xx_protect_flash(scsi_qla_host_t *vha)
1190	1218	{
1191		- uint32_t cnt;
1192	1219	struct qla_hw_data *ha = vha->hw;
1193	1220	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
	1221	+ ulong cnt = 300;
	1222	+ uint32_t faddr, dword;
1194	1223
1195	1224	if (ha->flags.fac_supported)
1196	1225	return qla81xx_fac_do_write_enable(vha, 0);
..	..	@@ -1199,19 +1228,21 @@
1199	1228	goto skip_wrt_protect;
1200	1229
1201	1230	/* Enable flash write-protection and wait for completion. */
1202		- qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1203		- ha->fdt_wrt_disable);
1204		- for (cnt = 300; cnt &&
1205		- qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1206		- cnt--) {
	1231	+ faddr = flash_conf_addr(ha, 0x101);
	1232	+ qla24xx_write_flash_dword(ha, faddr, ha->fdt_wrt_disable);
	1233	+ faddr = flash_conf_addr(ha, 0x5);
	1234	+ while (cnt--) {
	1235	+ if (!qla24xx_read_flash_dword(ha, faddr, &dword)) {
	1236	+ if (!(dword & BIT_0))
	1237	+ break;
	1238	+ }
1207	1239	udelay(10);
1208	1240	}
1209	1241
1210	1242	skip_wrt_protect:
1211	1243	/* Disable flash write. */
1212		- WRT_REG_DWORD(&reg->ctrl_status,
1213		- RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1214		- RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
	1244	+ wrt_reg_dword(&reg->ctrl_status,
	1245	+ rd_reg_dword(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1215	1246
1216	1247	return QLA_SUCCESS;
1217	1248	}
..	..	@@ -1235,111 +1266,107 @@
1235	1266	}
1236	1267
1237	1268	static int
1238		-qla24xx_write_flash_data(scsi_qla_host_t vha, uint32_t dwptr, uint32_t faddr,
	1269	+qla24xx_write_flash_data(scsi_qla_host_t vha, __le32 dwptr, uint32_t faddr,
1239	1270	uint32_t dwords)
1240	1271	{
1241	1272	int ret;
1242		- uint32_t liter;
1243		- uint32_t sec_mask, rest_addr;
1244		- uint32_t fdata;
	1273	+ ulong liter;
	1274	+ ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */
	1275	+ uint32_t sec_mask, rest_addr, fdata;
1245	1276	dma_addr_t optrom_dma;
1246	1277	void *optrom = NULL;
1247	1278	struct qla_hw_data *ha = vha->hw;
1248	1279
1249		- /* Prepare burst-capable write on supported ISPs. */
1250		- if ((IS_QLA25XX(ha) \|\| IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\|
1251		- IS_QLA27XX(ha)) &&
1252		- !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) {
1253		- optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1254		- &optrom_dma, GFP_KERNEL);
1255		- if (!optrom) {
1256		- ql_log(ql_log_warn, vha, 0x7095,
1257		- "Unable to allocate "
1258		- "memory for optrom burst write (%x KB).\n",
1259		- OPTROM_BURST_SIZE / 1024);
1260		- }
	1280	+ if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
	1281	+ !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
	1282	+ goto next;
	1283	+
	1284	+ /* Allocate dma buffer for burst write */
	1285	+ optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
	1286	+ &optrom_dma, GFP_KERNEL);
	1287	+ if (!optrom) {
	1288	+ ql_log(ql_log_warn, vha, 0x7095,
	1289	+ "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE);
	1290	+ }
	1291	+
	1292	+next:
	1293	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
	1294	+ "Unprotect flash...\n");
	1295	+ ret = qla24xx_unprotect_flash(vha);
	1296	+ if (ret) {
	1297	+ ql_log(ql_log_warn, vha, 0x7096,
	1298	+ "Failed to unprotect flash.\n");
	1299	+ goto done;
1261	1300	}
1262	1301
1263	1302	rest_addr = (ha->fdt_block_size >> 2) - 1;
1264	1303	sec_mask = ~rest_addr;
1265		-
1266		- ret = qla24xx_unprotect_flash(vha);
1267		- if (ret != QLA_SUCCESS) {
1268		- ql_log(ql_log_warn, vha, 0x7096,
1269		- "Unable to unprotect flash for update.\n");
1270		- goto done;
1271		- }
1272		-
1273	1304	for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1274	1305	fdata = (faddr & sec_mask) << 2;
1275	1306
1276	1307	/* Are we at the beginning of a sector? */
1277		- if ((faddr & rest_addr) == 0) {
1278		- /* Do sector unprotect. */
1279		- if (ha->fdt_unprotect_sec_cmd)
1280		- qla24xx_write_flash_dword(ha,
1281		- ha->fdt_unprotect_sec_cmd,
1282		- (fdata & 0xff00) \| ((fdata << 16) &
1283		- 0xff0000) \| ((fdata >> 16) & 0xff));
	1308	+ if (!(faddr & rest_addr)) {
	1309	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
	1310	+ "Erase sector %#x...\n", faddr);
	1311	+
1284	1312	ret = qla24xx_erase_sector(vha, fdata);
1285		- if (ret != QLA_SUCCESS) {
	1313	+ if (ret) {
1286	1314	ql_dbg(ql_dbg_user, vha, 0x7007,
1287		- "Unable to erase erase sector: address=%x.\n",
1288		- faddr);
	1315	+ "Failed to erase sector %x.\n", faddr);
1289	1316	break;
1290	1317	}
1291	1318	}
1292	1319
1293		- /* Go with burst-write. */
1294		- if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1295		- /* Copy data to DMA'ble buffer. */
1296		- memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
	1320	+ if (optrom) {
	1321	+ /* If smaller than a burst remaining */
	1322	+ if (dwords - liter < dburst)
	1323	+ dburst = dwords - liter;
1297	1324
	1325	+ /* Copy to dma buffer */
	1326	+ memcpy(optrom, dwptr, dburst << 2);
	1327	+
	1328	+ /* Burst write */
	1329	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
	1330	+ "Write burst (%#lx dwords)...\n", dburst);
1298	1331	ret = qla2x00_load_ram(vha, optrom_dma,
1299		- flash_data_addr(ha, faddr),
1300		- OPTROM_BURST_DWORDS);
1301		- if (ret != QLA_SUCCESS) {
1302		- ql_log(ql_log_warn, vha, 0x7097,
1303		- "Unable to burst-write optrom segment "
1304		- "(%x/%x/%llx).\n", ret,
1305		- flash_data_addr(ha, faddr),
1306		- (unsigned long long)optrom_dma);
1307		- ql_log(ql_log_warn, vha, 0x7098,
1308		- "Reverting to slow-write.\n");
1309		-
1310		- dma_free_coherent(&ha->pdev->dev,
1311		- OPTROM_BURST_SIZE, optrom, optrom_dma);
1312		- optrom = NULL;
1313		- } else {
1314		- liter += OPTROM_BURST_DWORDS - 1;
1315		- faddr += OPTROM_BURST_DWORDS - 1;
1316		- dwptr += OPTROM_BURST_DWORDS - 1;
	1332	+ flash_data_addr(ha, faddr), dburst);
	1333	+ if (!ret) {
	1334	+ liter += dburst - 1;
	1335	+ faddr += dburst - 1;
	1336	+ dwptr += dburst - 1;
1317	1337	continue;
1318	1338	}
	1339	+
	1340	+ ql_log(ql_log_warn, vha, 0x7097,
	1341	+ "Failed burst-write at %x (%p/%#llx)....\n",
	1342	+ flash_data_addr(ha, faddr), optrom,
	1343	+ (u64)optrom_dma);
	1344	+
	1345	+ dma_free_coherent(&ha->pdev->dev,
	1346	+ OPTROM_BURST_SIZE, optrom, optrom_dma);
	1347	+ optrom = NULL;
	1348	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	1349	+ break;
	1350	+ ql_log(ql_log_warn, vha, 0x7098,
	1351	+ "Reverting to slow write...\n");
1319	1352	}
1320	1353
	1354	+ /* Slow write */
1321	1355	ret = qla24xx_write_flash_dword(ha,
1322		- flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1323		- if (ret != QLA_SUCCESS) {
	1356	+ flash_data_addr(ha, faddr), le32_to_cpu(*dwptr));
	1357	+ if (ret) {
1324	1358	ql_dbg(ql_dbg_user, vha, 0x7006,
1325		- "Unable to program flash address=%x data=%x.\n",
1326		- faddr, *dwptr);
	1359	+ "Failed slow write %x (%x)\n", faddr, *dwptr);
1327	1360	break;
1328	1361	}
1329		-
1330		- /* Do sector protect. */
1331		- if (ha->fdt_unprotect_sec_cmd &&
1332		- ((faddr & rest_addr) == rest_addr))
1333		- qla24xx_write_flash_dword(ha,
1334		- ha->fdt_protect_sec_cmd,
1335		- (fdata & 0xff00) \| ((fdata << 16) &
1336		- 0xff0000) \| ((fdata >> 16) & 0xff));
1337	1362	}
1338	1363
	1364	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
	1365	+ "Protect flash...\n");
1339	1366	ret = qla24xx_protect_flash(vha);
1340		- if (ret != QLA_SUCCESS)
	1367	+ if (ret)
1341	1368	ql_log(ql_log_warn, vha, 0x7099,
1342		- "Unable to protect flash after update.\n");
	1369	+ "Failed to protect flash\n");
1343	1370	done:
1344	1371	if (optrom)
1345	1372	dma_free_coherent(&ha->pdev->dev,
..	..	@@ -1349,15 +1376,15 @@
1349	1376	}
1350	1377
1351	1378	uint8_t *
1352		-qla2x00_read_nvram_data(scsi_qla_host_t vha, uint8_t buf, uint32_t naddr,
	1379	+qla2x00_read_nvram_data(scsi_qla_host_t vha, void buf, uint32_t naddr,
1353	1380	uint32_t bytes)
1354	1381	{
1355	1382	uint32_t i;
1356		- uint16_t *wptr;
	1383	+ __le16 *wptr;
1357	1384	struct qla_hw_data *ha = vha->hw;
1358	1385
1359	1386	/* Word reads to NVRAM via registers. */
1360		- wptr = (uint16_t *)buf;
	1387	+ wptr = buf;
1361	1388	qla2x00_lock_nvram_access(ha);
1362	1389	for (i = 0; i < bytes >> 1; i++, naddr++)
1363	1390	wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
..	..	@@ -1368,27 +1395,30 @@
1368	1395	}
1369	1396
1370	1397	uint8_t *
1371		-qla24xx_read_nvram_data(scsi_qla_host_t vha, uint8_t buf, uint32_t naddr,
	1398	+qla24xx_read_nvram_data(scsi_qla_host_t vha, void buf, uint32_t naddr,
1372	1399	uint32_t bytes)
1373	1400	{
1374		- uint32_t i;
1375		- uint32_t *dwptr;
1376	1401	struct qla_hw_data *ha = vha->hw;
	1402	+ uint32_t *dwptr = buf;
	1403	+ uint32_t i;
1377	1404
1378	1405	if (IS_P3P_TYPE(ha))
1379	1406	return buf;
1380	1407
1381	1408	/* Dword reads to flash. */
1382		- dwptr = (uint32_t *)buf;
1383		- for (i = 0; i < bytes >> 2; i++, naddr++)
1384		- dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1385		- nvram_data_addr(ha, naddr)));
	1409	+ naddr = nvram_data_addr(ha, naddr);
	1410	+ bytes >>= 2;
	1411	+ for (i = 0; i < bytes; i++, naddr++, dwptr++) {
	1412	+ if (qla24xx_read_flash_dword(ha, naddr, dwptr))
	1413	+ break;
	1414	+ cpu_to_le32s(dwptr);
	1415	+ }
1386	1416
1387	1417	return buf;
1388	1418	}
1389	1419
1390	1420	int
1391		-qla2x00_write_nvram_data(scsi_qla_host_t vha, uint8_t buf, uint32_t naddr,
	1421	+qla2x00_write_nvram_data(scsi_qla_host_t vha, void buf, uint32_t naddr,
1392	1422	uint32_t bytes)
1393	1423	{
1394	1424	int ret, stat;
..	..	@@ -1422,14 +1452,14 @@
1422	1452	}
1423	1453
1424	1454	int
1425		-qla24xx_write_nvram_data(scsi_qla_host_t vha, uint8_t buf, uint32_t naddr,
	1455	+qla24xx_write_nvram_data(scsi_qla_host_t vha, void buf, uint32_t naddr,
1426	1456	uint32_t bytes)
1427	1457	{
1428		- int ret;
1429		- uint32_t i;
1430		- uint32_t *dwptr;
1431	1458	struct qla_hw_data *ha = vha->hw;
1432	1459	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
	1460	+ __le32 *dwptr = buf;
	1461	+ uint32_t i;
	1462	+ int ret;
1433	1463
1434	1464	ret = QLA_SUCCESS;
1435	1465
..	..	@@ -1437,20 +1467,19 @@
1437	1467	return ret;
1438	1468
1439	1469	/* Enable flash write. */
1440		- WRT_REG_DWORD(&reg->ctrl_status,
1441		- RD_REG_DWORD(&reg->ctrl_status) \| CSRX_FLASH_ENABLE);
1442		- RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
	1470	+ wrt_reg_dword(&reg->ctrl_status,
	1471	+ rd_reg_dword(&reg->ctrl_status) \| CSRX_FLASH_ENABLE);
	1472	+ rd_reg_dword(&reg->ctrl_status); /* PCI Posting. */
1443	1473
1444	1474	/* Disable NVRAM write-protection. */
1445	1475	qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1446	1476	qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1447	1477
1448	1478	/* Dword writes to flash. */
1449		- dwptr = (uint32_t *)buf;
1450		- for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1451		- ret = qla24xx_write_flash_dword(ha,
1452		- nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1453		- if (ret != QLA_SUCCESS) {
	1479	+ naddr = nvram_data_addr(ha, naddr);
	1480	+ bytes >>= 2;
	1481	+ for (i = 0; i < bytes; i++, naddr++, dwptr++) {
	1482	+ if (qla24xx_write_flash_dword(ha, naddr, le32_to_cpu(*dwptr))) {
1454	1483	ql_dbg(ql_dbg_user, vha, 0x709a,
1455	1484	"Unable to program nvram address=%x data=%x.\n",
1456	1485	naddr, *dwptr);
..	..	@@ -1462,39 +1491,42 @@
1462	1491	qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1463	1492
1464	1493	/* Disable flash write. */
1465		- WRT_REG_DWORD(&reg->ctrl_status,
1466		- RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1467		- RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
	1494	+ wrt_reg_dword(&reg->ctrl_status,
	1495	+ rd_reg_dword(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
	1496	+ rd_reg_dword(&reg->ctrl_status); /* PCI Posting. */
1468	1497
1469	1498	return ret;
1470	1499	}
1471	1500
1472	1501	uint8_t *
1473		-qla25xx_read_nvram_data(scsi_qla_host_t vha, uint8_t buf, uint32_t naddr,
	1502	+qla25xx_read_nvram_data(scsi_qla_host_t vha, void buf, uint32_t naddr,
1474	1503	uint32_t bytes)
1475	1504	{
1476		- uint32_t i;
1477		- uint32_t *dwptr;
1478	1505	struct qla_hw_data *ha = vha->hw;
	1506	+ uint32_t *dwptr = buf;
	1507	+ uint32_t i;
1479	1508
1480	1509	/* Dword reads to flash. */
1481		- dwptr = (uint32_t *)buf;
1482		- for (i = 0; i < bytes >> 2; i++, naddr++)
1483		- dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1484		- flash_data_addr(ha, ha->flt_region_vpd_nvram \| naddr)));
	1510	+ naddr = flash_data_addr(ha, ha->flt_region_vpd_nvram \| naddr);
	1511	+ bytes >>= 2;
	1512	+ for (i = 0; i < bytes; i++, naddr++, dwptr++) {
	1513	+ if (qla24xx_read_flash_dword(ha, naddr, dwptr))
	1514	+ break;
	1515	+
	1516	+ cpu_to_le32s(dwptr);
	1517	+ }
1485	1518
1486	1519	return buf;
1487	1520	}
1488	1521
	1522	+#define RMW_BUFFER_SIZE (64 * 1024)
1489	1523	int
1490		-qla25xx_write_nvram_data(scsi_qla_host_t vha, uint8_t buf, uint32_t naddr,
	1524	+qla25xx_write_nvram_data(scsi_qla_host_t vha, void buf, uint32_t naddr,
1491	1525	uint32_t bytes)
1492	1526	{
1493	1527	struct qla_hw_data *ha = vha->hw;
1494		-#define RMW_BUFFER_SIZE (64 * 1024)
1495		- uint8_t *dbuf;
	1528	+ uint8_t *dbuf = vmalloc(RMW_BUFFER_SIZE);
1496	1529
1497		- dbuf = vmalloc(RMW_BUFFER_SIZE);
1498	1530	if (!dbuf)
1499	1531	return QLA_MEMORY_ALLOC_FAILED;
1500	1532	ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
..	..	@@ -1557,8 +1589,8 @@
1557	1589	gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1558	1590	gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1559	1591	} else {
1560		- gpio_enable = RD_REG_WORD(&reg->gpioe);
1561		- gpio_data = RD_REG_WORD(&reg->gpiod);
	1592	+ gpio_enable = rd_reg_word(&reg->gpioe);
	1593	+ gpio_data = rd_reg_word(&reg->gpiod);
1562	1594	}
1563	1595
1564	1596	/* Set the modified gpio_enable values */
..	..	@@ -1567,8 +1599,8 @@
1567	1599	if (ha->pio_address) {
1568	1600	WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1569	1601	} else {
1570		- WRT_REG_WORD(&reg->gpioe, gpio_enable);
1571		- RD_REG_WORD(&reg->gpioe);
	1602	+ wrt_reg_word(&reg->gpioe, gpio_enable);
	1603	+ rd_reg_word(&reg->gpioe);
1572	1604	}
1573	1605
1574	1606	qla2x00_flip_colors(ha, &led_color);
..	..	@@ -1583,8 +1615,8 @@
1583	1615	if (ha->pio_address) {
1584	1616	WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1585	1617	} else {
1586		- WRT_REG_WORD(&reg->gpiod, gpio_data);
1587		- RD_REG_WORD(&reg->gpiod);
	1618	+ wrt_reg_word(&reg->gpiod, gpio_data);
	1619	+ rd_reg_word(&reg->gpiod);
1588	1620	}
1589	1621
1590	1622	spin_unlock_irqrestore(&ha->hardware_lock, flags);
..	..	@@ -1614,8 +1646,8 @@
1614	1646	gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1615	1647	gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1616	1648	} else {
1617		- gpio_enable = RD_REG_WORD(&reg->gpioe);
1618		- gpio_data = RD_REG_WORD(&reg->gpiod);
	1649	+ gpio_enable = rd_reg_word(&reg->gpioe);
	1650	+ gpio_data = rd_reg_word(&reg->gpiod);
1619	1651	}
1620	1652	gpio_enable \|= GPIO_LED_MASK;
1621	1653
..	..	@@ -1623,8 +1655,8 @@
1623	1655	if (ha->pio_address) {
1624	1656	WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1625	1657	} else {
1626		- WRT_REG_WORD(&reg->gpioe, gpio_enable);
1627		- RD_REG_WORD(&reg->gpioe);
	1658	+ wrt_reg_word(&reg->gpioe, gpio_enable);
	1659	+ rd_reg_word(&reg->gpioe);
1628	1660	}
1629	1661
1630	1662	/* Clear out previously set LED colour. */
..	..	@@ -1632,8 +1664,8 @@
1632	1664	if (ha->pio_address) {
1633	1665	WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1634	1666	} else {
1635		- WRT_REG_WORD(&reg->gpiod, gpio_data);
1636		- RD_REG_WORD(&reg->gpiod);
	1667	+ wrt_reg_word(&reg->gpiod, gpio_data);
	1668	+ rd_reg_word(&reg->gpiod);
1637	1669	}
1638	1670	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1639	1671
..	..	@@ -1700,13 +1732,13 @@
1700	1732
1701	1733	/* Save the Original GPIOD. */
1702	1734	spin_lock_irqsave(&ha->hardware_lock, flags);
1703		- gpio_data = RD_REG_DWORD(&reg->gpiod);
	1735	+ gpio_data = rd_reg_dword(&reg->gpiod);
1704	1736
1705	1737	/* Enable the gpio_data reg for update. */
1706	1738	gpio_data \|= GPDX_LED_UPDATE_MASK;
1707	1739
1708		- WRT_REG_DWORD(&reg->gpiod, gpio_data);
1709		- gpio_data = RD_REG_DWORD(&reg->gpiod);
	1740	+ wrt_reg_dword(&reg->gpiod, gpio_data);
	1741	+ gpio_data = rd_reg_dword(&reg->gpiod);
1710	1742
1711	1743	/* Set the color bits. */
1712	1744	qla24xx_flip_colors(ha, &led_color);
..	..	@@ -1718,8 +1750,8 @@
1718	1750	gpio_data \|= led_color;
1719	1751
1720	1752	/* Set the modified gpio_data values. */
1721		- WRT_REG_DWORD(&reg->gpiod, gpio_data);
1722		- gpio_data = RD_REG_DWORD(&reg->gpiod);
	1753	+ wrt_reg_dword(&reg->gpiod, gpio_data);
	1754	+ gpio_data = rd_reg_dword(&reg->gpiod);
1723	1755	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1724	1756	}
1725	1757
..	..	@@ -1728,7 +1760,7 @@
1728	1760	{
1729	1761	uint32_t led_select_value = 0;
1730	1762
1731		- if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
	1763	+ if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
1732	1764	goto out;
1733	1765
1734	1766	if (ha->port_no == 0)
..	..	@@ -1749,13 +1781,14 @@
1749	1781	uint16_t orig_led_cfg[6];
1750	1782	uint32_t led_10_value, led_43_value;
1751	1783
1752		- if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha))
	1784	+ if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha) &&
	1785	+ !IS_QLA28XX(ha))
1753	1786	return;
1754	1787
1755	1788	if (!ha->beacon_blink_led)
1756	1789	return;
1757	1790
1758		- if (IS_QLA27XX(ha)) {
	1791	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
1759	1792	qla2x00_write_ram_word(vha, 0x1003, 0x40000230);
1760	1793	qla2x00_write_ram_word(vha, 0x1004, 0x40000230);
1761	1794	} else if (IS_QLA2031(ha)) {
..	..	@@ -1845,16 +1878,16 @@
1845	1878	return QLA_FUNCTION_FAILED;
1846	1879	}
1847	1880
1848		- if (IS_QLA2031(ha) \|\| IS_QLA27XX(ha))
	1881	+ if (IS_QLA2031(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
1849	1882	goto skip_gpio;
1850	1883
1851	1884	spin_lock_irqsave(&ha->hardware_lock, flags);
1852		- gpio_data = RD_REG_DWORD(&reg->gpiod);
	1885	+ gpio_data = rd_reg_dword(&reg->gpiod);
1853	1886
1854	1887	/* Enable the gpio_data reg for update. */
1855	1888	gpio_data \|= GPDX_LED_UPDATE_MASK;
1856		- WRT_REG_DWORD(&reg->gpiod, gpio_data);
1857		- RD_REG_DWORD(&reg->gpiod);
	1889	+ wrt_reg_dword(&reg->gpiod, gpio_data);
	1890	+ rd_reg_dword(&reg->gpiod);
1858	1891
1859	1892	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1860	1893	}
..	..	@@ -1885,7 +1918,7 @@
1885	1918
1886	1919	ha->beacon_blink_led = 0;
1887	1920
1888		- if (IS_QLA2031(ha) \|\| IS_QLA27XX(ha))
	1921	+ if (IS_QLA2031(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
1889	1922	goto set_fw_options;
1890	1923
1891	1924	if (IS_QLA8031(ha) \|\| IS_QLA81XX(ha))
..	..	@@ -1897,12 +1930,12 @@
1897	1930
1898	1931	/* Give control back to firmware. */
1899	1932	spin_lock_irqsave(&ha->hardware_lock, flags);
1900		- gpio_data = RD_REG_DWORD(&reg->gpiod);
	1933	+ gpio_data = rd_reg_dword(&reg->gpiod);
1901	1934
1902	1935	/* Disable the gpio_data reg for update. */
1903	1936	gpio_data &= ~GPDX_LED_UPDATE_MASK;
1904		- WRT_REG_DWORD(&reg->gpiod, gpio_data);
1905		- RD_REG_DWORD(&reg->gpiod);
	1937	+ wrt_reg_dword(&reg->gpiod, gpio_data);
	1938	+ rd_reg_dword(&reg->gpiod);
1906	1939	spin_unlock_irqrestore(&ha->hardware_lock, flags);
1907	1940
1908	1941	set_fw_options:
..	..	@@ -1938,10 +1971,10 @@
1938	1971	uint16_t data;
1939	1972	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1940	1973
1941		- data = RD_REG_WORD(&reg->ctrl_status);
	1974	+ data = rd_reg_word(&reg->ctrl_status);
1942	1975	data \|= CSR_FLASH_ENABLE;
1943		- WRT_REG_WORD(&reg->ctrl_status, data);
1944		- RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
	1976	+ wrt_reg_word(&reg->ctrl_status, data);
	1977	+ rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
1945	1978	}
1946	1979
1947	1980	/**
..	..	@@ -1954,10 +1987,10 @@
1954	1987	uint16_t data;
1955	1988	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1956	1989
1957		- data = RD_REG_WORD(&reg->ctrl_status);
	1990	+ data = rd_reg_word(&reg->ctrl_status);
1958	1991	data &= ~(CSR_FLASH_ENABLE);
1959		- WRT_REG_WORD(&reg->ctrl_status, data);
1960		- RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
	1992	+ wrt_reg_word(&reg->ctrl_status, data);
	1993	+ rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
1961	1994	}
1962	1995
1963	1996	/**
..	..	@@ -1976,7 +2009,7 @@
1976	2009	uint16_t bank_select;
1977	2010	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1978	2011
1979		- bank_select = RD_REG_WORD(&reg->ctrl_status);
	2012	+ bank_select = rd_reg_word(&reg->ctrl_status);
1980	2013
1981	2014	if (IS_QLA2322(ha) \|\| IS_QLA6322(ha)) {
1982	2015	/* Specify 64K address range: */
..	..	@@ -1984,11 +2017,11 @@
1984	2017	bank_select &= ~0xf8;
1985	2018	bank_select \|= addr >> 12 & 0xf0;
1986	2019	bank_select \|= CSR_FLASH_64K_BANK;
1987		- WRT_REG_WORD(&reg->ctrl_status, bank_select);
1988		- RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
	2020	+ wrt_reg_word(&reg->ctrl_status, bank_select);
	2021	+ rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
1989	2022
1990		- WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1991		- data = RD_REG_WORD(&reg->flash_data);
	2023	+ wrt_reg_word(&reg->flash_address, (uint16_t)addr);
	2024	+ data = rd_reg_word(&reg->flash_data);
1992	2025
1993	2026	return (uint8_t)data;
1994	2027	}
..	..	@@ -1996,13 +2029,13 @@
1996	2029	/* Setup bit 16 of flash address. */
1997	2030	if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1998	2031	bank_select \|= CSR_FLASH_64K_BANK;
1999		- WRT_REG_WORD(&reg->ctrl_status, bank_select);
2000		- RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
	2032	+ wrt_reg_word(&reg->ctrl_status, bank_select);
	2033	+ rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
2001	2034	} else if (((addr & BIT_16) == 0) &&
2002	2035	(bank_select & CSR_FLASH_64K_BANK)) {
2003	2036	bank_select &= ~(CSR_FLASH_64K_BANK);
2004		- WRT_REG_WORD(&reg->ctrl_status, bank_select);
2005		- RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
	2037	+ wrt_reg_word(&reg->ctrl_status, bank_select);
	2038	+ rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
2006	2039	}
2007	2040
2008	2041	/* Always perform IO mapped accesses to the FLASH registers. */
..	..	@@ -2017,7 +2050,7 @@
2017	2050	data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
2018	2051	} while (data != data2);
2019	2052	} else {
2020		- WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
	2053	+ wrt_reg_word(&reg->flash_address, (uint16_t)addr);
2021	2054	data = qla2x00_debounce_register(&reg->flash_data);
2022	2055	}
2023	2056
..	..	@@ -2036,20 +2069,20 @@
2036	2069	uint16_t bank_select;
2037	2070	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2038	2071
2039		- bank_select = RD_REG_WORD(&reg->ctrl_status);
	2072	+ bank_select = rd_reg_word(&reg->ctrl_status);
2040	2073	if (IS_QLA2322(ha) \|\| IS_QLA6322(ha)) {
2041	2074	/* Specify 64K address range: */
2042	2075	/* clear out Module Select and Flash Address bits [19:16]. */
2043	2076	bank_select &= ~0xf8;
2044	2077	bank_select \|= addr >> 12 & 0xf0;
2045	2078	bank_select \|= CSR_FLASH_64K_BANK;
2046		- WRT_REG_WORD(&reg->ctrl_status, bank_select);
2047		- RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
	2079	+ wrt_reg_word(&reg->ctrl_status, bank_select);
	2080	+ rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
2048	2081
2049		- WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
2050		- RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2051		- WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
2052		- RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
	2082	+ wrt_reg_word(&reg->flash_address, (uint16_t)addr);
	2083	+ rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
	2084	+ wrt_reg_word(&reg->flash_data, (uint16_t)data);
	2085	+ rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
2053	2086
2054	2087	return;
2055	2088	}
..	..	@@ -2057,13 +2090,13 @@
2057	2090	/* Setup bit 16 of flash address. */
2058	2091	if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
2059	2092	bank_select \|= CSR_FLASH_64K_BANK;
2060		- WRT_REG_WORD(&reg->ctrl_status, bank_select);
2061		- RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
	2093	+ wrt_reg_word(&reg->ctrl_status, bank_select);
	2094	+ rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
2062	2095	} else if (((addr & BIT_16) == 0) &&
2063	2096	(bank_select & CSR_FLASH_64K_BANK)) {
2064	2097	bank_select &= ~(CSR_FLASH_64K_BANK);
2065		- WRT_REG_WORD(&reg->ctrl_status, bank_select);
2066		- RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
	2098	+ wrt_reg_word(&reg->ctrl_status, bank_select);
	2099	+ rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
2067	2100	}
2068	2101
2069	2102	/* Always perform IO mapped accesses to the FLASH registers. */
..	..	@@ -2071,10 +2104,10 @@
2071	2104	WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
2072	2105	WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
2073	2106	} else {
2074		- WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
2075		- RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2076		- WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
2077		- RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
	2107	+ wrt_reg_word(&reg->flash_address, (uint16_t)addr);
	2108	+ rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
	2109	+ wrt_reg_word(&reg->flash_data, (uint16_t)data);
	2110	+ rd_reg_word(&reg->ctrl_status); /* PCI Posting. */
2078	2111	}
2079	2112	}
2080	2113
..	..	@@ -2229,7 +2262,7 @@
2229	2262
2230	2263	/**
2231	2264	* qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2232		- * @ha:
	2265	+ * @ha: host adapter
2233	2266	* @man_id: Flash manufacturer ID
2234	2267	* @flash_id: Flash ID
2235	2268	*/
..	..	@@ -2257,12 +2290,12 @@
2257	2290
2258	2291	midpoint = length / 2;
2259	2292
2260		- WRT_REG_WORD(&reg->nvram, 0);
2261		- RD_REG_WORD(&reg->nvram);
	2293	+ wrt_reg_word(&reg->nvram, 0);
	2294	+ rd_reg_word(&reg->nvram);
2262	2295	for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2263	2296	if (ilength == midpoint) {
2264		- WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2265		- RD_REG_WORD(&reg->nvram);
	2297	+ wrt_reg_word(&reg->nvram, NVR_SELECT);
	2298	+ rd_reg_word(&reg->nvram);
2266	2299	}
2267	2300	data = qla2x00_read_flash_byte(ha, saddr);
2268	2301	if (saddr % 100)
..	..	@@ -2287,11 +2320,11 @@
2287	2320
2288	2321	/* Pause RISC. */
2289	2322	spin_lock_irqsave(&ha->hardware_lock, flags);
2290		- WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2291		- RD_REG_WORD(&reg->hccr);
	2323	+ wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);
	2324	+ rd_reg_word(&reg->hccr);
2292	2325	if (IS_QLA2100(ha) \|\| IS_QLA2200(ha) \|\| IS_QLA2300(ha)) {
2293	2326	for (cnt = 0; cnt < 30000; cnt++) {
2294		- if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
	2327	+ if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
2295	2328	break;
2296	2329	udelay(100);
2297	2330	}
..	..	@@ -2314,8 +2347,8 @@
2314	2347	scsi_unblock_requests(vha->host);
2315	2348	}
2316	2349
2317		-uint8_t *
2318		-qla2x00_read_optrom_data(struct scsi_qla_host vha, uint8_t buf,
	2350	+void *
	2351	+qla2x00_read_optrom_data(struct scsi_qla_host vha, void buf,
2319	2352	uint32_t offset, uint32_t length)
2320	2353	{
2321	2354	uint32_t addr, midpoint;
..	..	@@ -2330,12 +2363,12 @@
2330	2363	midpoint = ha->optrom_size / 2;
2331	2364
2332	2365	qla2x00_flash_enable(ha);
2333		- WRT_REG_WORD(&reg->nvram, 0);
2334		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	2366	+ wrt_reg_word(&reg->nvram, 0);
	2367	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
2335	2368	for (addr = offset, data = buf; addr < length; addr++, data++) {
2336	2369	if (addr == midpoint) {
2337		- WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2338		- RD_REG_WORD(&reg->nvram); /* PCI Posting. */
	2370	+ wrt_reg_word(&reg->nvram, NVR_SELECT);
	2371	+ rd_reg_word(&reg->nvram); /* PCI Posting. */
2339	2372	}
2340	2373
2341	2374	*data = qla2x00_read_flash_byte(ha, addr);
..	..	@@ -2349,12 +2382,12 @@
2349	2382	}
2350	2383
2351	2384	int
2352		-qla2x00_write_optrom_data(struct scsi_qla_host vha, uint8_t buf,
	2385	+qla2x00_write_optrom_data(struct scsi_qla_host vha, void buf,
2353	2386	uint32_t offset, uint32_t length)
2354	2387	{
2355	2388
2356	2389	int rval;
2357		- uint8_t man_id, flash_id, sec_number, data;
	2390	+ uint8_t man_id, flash_id, sec_number, *data;
2358	2391	uint16_t wd;
2359	2392	uint32_t addr, liter, sec_mask, rest_addr;
2360	2393	struct qla_hw_data *ha = vha->hw;
..	..	@@ -2367,7 +2400,7 @@
2367	2400	sec_number = 0;
2368	2401
2369	2402	/* Reset ISP chip. */
2370		- WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
	2403	+ wrt_reg_word(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2371	2404	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2372	2405
2373	2406	/* Go with write. */
..	..	@@ -2423,7 +2456,7 @@
2423	2456	sec_mask = 0x10000;
2424	2457	break;
2425	2458	}
2426		- /* Fall through... */
	2459	+ fallthrough;
2427	2460
2428	2461	case 0x1f: /* Atmel flash. */
2429	2462	/* 512k sector size. */
..	..	@@ -2432,7 +2465,7 @@
2432	2465	sec_mask = 0x80000000;
2433	2466	break;
2434	2467	}
2435		- /* Fall through... */
	2468	+ fallthrough;
2436	2469
2437	2470	case 0x01: /* AMD flash. */
2438	2471	if (flash_id == 0x38 \|\| flash_id == 0x40 \|\|
..	..	@@ -2465,7 +2498,7 @@
2465	2498	sec_mask = 0x1e000;
2466	2499	break;
2467	2500	}
2468		- /* fall through */
	2501	+ fallthrough;
2469	2502	default:
2470	2503	/* Default to 16 kb sector size. */
2471	2504	rest_addr = 0x3fff;
..	..	@@ -2483,7 +2516,7 @@
2483	2516
2484	2517	for (addr = offset, liter = 0; liter < length; liter++,
2485	2518	addr++) {
2486		- data = buf[liter];
	2519	+ data = buf + liter;
2487	2520	/* Are we at the beginning of a sector? */
2488	2521	if ((addr & rest_addr) == 0) {
2489	2522	if (IS_QLA2322(ha) \|\| IS_QLA6322(ha)) {
..	..	@@ -2516,8 +2549,8 @@
2516	2549	}
2517	2550	}
2518	2551	} else if (addr == ha->optrom_size / 2) {
2519		- WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2520		- RD_REG_WORD(&reg->nvram);
	2552	+ wrt_reg_word(&reg->nvram, NVR_SELECT);
	2553	+ rd_reg_word(&reg->nvram);
2521	2554	}
2522	2555
2523	2556	if (flash_id == 0xda && man_id == 0xc1) {
..	..	@@ -2551,7 +2584,7 @@
2551	2584	}
2552	2585	}
2553	2586
2554		- if (qla2x00_program_flash_address(ha, addr, data,
	2587	+ if (qla2x00_program_flash_address(ha, addr, *data,
2555	2588	man_id, flash_id)) {
2556	2589	rval = QLA_FUNCTION_FAILED;
2557	2590	break;
..	..	@@ -2567,8 +2600,8 @@
2567	2600	return rval;
2568	2601	}
2569	2602
2570		-uint8_t *
2571		-qla24xx_read_optrom_data(struct scsi_qla_host vha, uint8_t buf,
	2603	+void *
	2604	+qla24xx_read_optrom_data(struct scsi_qla_host vha, void buf,
2572	2605	uint32_t offset, uint32_t length)
2573	2606	{
2574	2607	struct qla_hw_data *ha = vha->hw;
..	..	@@ -2578,7 +2611,7 @@
2578	2611	set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2579	2612
2580	2613	/* Go with read. */
2581		- qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
	2614	+ qla24xx_read_flash_data(vha, buf, offset >> 2, length >> 2);
2582	2615
2583	2616	/* Resume HBA. */
2584	2617	clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
..	..	@@ -2587,8 +2620,358 @@
2587	2620	return buf;
2588	2621	}
2589	2622
	2623	+static int
	2624	+qla28xx_extract_sfub_and_verify(struct scsi_qla_host vha, uint32_t buf,
	2625	+ uint32_t len, uint32_t buf_size_without_sfub, uint8_t *sfub_buf)
	2626	+{
	2627	+ uint32_t *p, check_sum = 0;
	2628	+ int i;
	2629	+
	2630	+ p = buf + buf_size_without_sfub;
	2631	+
	2632	+ /* Extract SFUB from end of file */
	2633	+ memcpy(sfub_buf, (uint8_t *)p,
	2634	+ sizeof(struct secure_flash_update_block));
	2635	+
	2636	+ for (i = 0; i < (sizeof(struct secure_flash_update_block) >> 2); i++)
	2637	+ check_sum += p[i];
	2638	+
	2639	+ check_sum = (~check_sum) + 1;
	2640	+
	2641	+ if (check_sum != p[i]) {
	2642	+ ql_log(ql_log_warn, vha, 0x7097,
	2643	+ "SFUB checksum failed, 0x%x, 0x%x\n",
	2644	+ check_sum, p[i]);
	2645	+ return QLA_COMMAND_ERROR;
	2646	+ }
	2647	+
	2648	+ return QLA_SUCCESS;
	2649	+}
	2650	+
	2651	+static int
	2652	+qla28xx_get_flash_region(struct scsi_qla_host *vha, uint32_t start,
	2653	+ struct qla_flt_region *region)
	2654	+{
	2655	+ struct qla_hw_data *ha = vha->hw;
	2656	+ struct qla_flt_header *flt = ha->flt;
	2657	+ struct qla_flt_region *flt_reg = &flt->region[0];
	2658	+ uint16_t cnt;
	2659	+ int rval = QLA_FUNCTION_FAILED;
	2660	+
	2661	+ if (!ha->flt)
	2662	+ return QLA_FUNCTION_FAILED;
	2663	+
	2664	+ cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
	2665	+ for (; cnt; cnt--, flt_reg++) {
	2666	+ if (le32_to_cpu(flt_reg->start) == start) {
	2667	+ memcpy((uint8_t *)region, flt_reg,
	2668	+ sizeof(struct qla_flt_region));
	2669	+ rval = QLA_SUCCESS;
	2670	+ break;
	2671	+ }
	2672	+ }
	2673	+
	2674	+ return rval;
	2675	+}
	2676	+
	2677	+static int
	2678	+qla28xx_write_flash_data(scsi_qla_host_t vha, uint32_t dwptr, uint32_t faddr,
	2679	+ uint32_t dwords)
	2680	+{
	2681	+ struct qla_hw_data *ha = vha->hw;
	2682	+ ulong liter;
	2683	+ ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */
	2684	+ uint32_t sec_mask, rest_addr, fdata;
	2685	+ void *optrom = NULL;
	2686	+ dma_addr_t optrom_dma;
	2687	+ int rval, ret;
	2688	+ struct secure_flash_update_block *sfub;
	2689	+ dma_addr_t sfub_dma;
	2690	+ uint32_t offset = faddr << 2;
	2691	+ uint32_t buf_size_without_sfub = 0;
	2692	+ struct qla_flt_region region;
	2693	+ bool reset_to_rom = false;
	2694	+ uint32_t risc_size, risc_attr = 0;
	2695	+ __be32 *fw_array = NULL;
	2696	+
	2697	+ /* Retrieve region info - must be a start address passed in */
	2698	+ rval = qla28xx_get_flash_region(vha, offset, &region);
	2699	+
	2700	+ if (rval != QLA_SUCCESS) {
	2701	+ ql_log(ql_log_warn, vha, 0xffff,
	2702	+ "Invalid address %x - not a region start address\n",
	2703	+ offset);
	2704	+ goto done;
	2705	+ }
	2706	+
	2707	+ /* Allocate dma buffer for burst write */
	2708	+ optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
	2709	+ &optrom_dma, GFP_KERNEL);
	2710	+ if (!optrom) {
	2711	+ ql_log(ql_log_warn, vha, 0x7095,
	2712	+ "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE);
	2713	+ rval = QLA_COMMAND_ERROR;
	2714	+ goto done;
	2715	+ }
	2716	+
	2717	+ /*
	2718	+ * If adapter supports secure flash and region is secure
	2719	+ * extract secure flash update block (SFUB) and verify
	2720	+ */
	2721	+ if (ha->flags.secure_adapter && region.attribute) {
	2722	+
	2723	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
	2724	+ "Region %x is secure\n", region.code);
	2725	+
	2726	+ switch (le16_to_cpu(region.code)) {
	2727	+ case FLT_REG_FW:
	2728	+ case FLT_REG_FW_SEC_27XX:
	2729	+ case FLT_REG_MPI_PRI_28XX:
	2730	+ case FLT_REG_MPI_SEC_28XX:
	2731	+ fw_array = (__force __be32 *)dwptr;
	2732	+
	2733	+ /* 1st fw array */
	2734	+ risc_size = be32_to_cpu(fw_array[3]);
	2735	+ risc_attr = be32_to_cpu(fw_array[9]);
	2736	+
	2737	+ buf_size_without_sfub = risc_size;
	2738	+ fw_array += risc_size;
	2739	+
	2740	+ /* 2nd fw array */
	2741	+ risc_size = be32_to_cpu(fw_array[3]);
	2742	+
	2743	+ buf_size_without_sfub += risc_size;
	2744	+ fw_array += risc_size;
	2745	+
	2746	+ /* 1st dump template */
	2747	+ risc_size = be32_to_cpu(fw_array[2]);
	2748	+
	2749	+ /* skip header and ignore checksum */
	2750	+ buf_size_without_sfub += risc_size;
	2751	+ fw_array += risc_size;
	2752	+
	2753	+ if (risc_attr & BIT_9) {
	2754	+ /* 2nd dump template */
	2755	+ risc_size = be32_to_cpu(fw_array[2]);
	2756	+
	2757	+ /* skip header and ignore checksum */
	2758	+ buf_size_without_sfub += risc_size;
	2759	+ fw_array += risc_size;
	2760	+ }
	2761	+ break;
	2762	+
	2763	+ case FLT_REG_PEP_PRI_28XX:
	2764	+ case FLT_REG_PEP_SEC_28XX:
	2765	+ fw_array = (__force __be32 *)dwptr;
	2766	+
	2767	+ /* 1st fw array */
	2768	+ risc_size = be32_to_cpu(fw_array[3]);
	2769	+ risc_attr = be32_to_cpu(fw_array[9]);
	2770	+
	2771	+ buf_size_without_sfub = risc_size;
	2772	+ fw_array += risc_size;
	2773	+ break;
	2774	+
	2775	+ default:
	2776	+ ql_log(ql_log_warn + ql_dbg_verbose, vha,
	2777	+ 0xffff, "Secure region %x not supported\n",
	2778	+ region.code);
	2779	+ rval = QLA_COMMAND_ERROR;
	2780	+ goto done;
	2781	+ }
	2782	+
	2783	+ sfub = dma_alloc_coherent(&ha->pdev->dev,
	2784	+ sizeof(struct secure_flash_update_block), &sfub_dma,
	2785	+ GFP_KERNEL);
	2786	+ if (!sfub) {
	2787	+ ql_log(ql_log_warn, vha, 0xffff,
	2788	+ "Unable to allocate memory for SFUB\n");
	2789	+ rval = QLA_COMMAND_ERROR;
	2790	+ goto done;
	2791	+ }
	2792	+
	2793	+ rval = qla28xx_extract_sfub_and_verify(vha, dwptr, dwords,
	2794	+ buf_size_without_sfub, (uint8_t *)sfub);
	2795	+
	2796	+ if (rval != QLA_SUCCESS)
	2797	+ goto done;
	2798	+
	2799	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
	2800	+ "SFUB extract and verify successful\n");
	2801	+ }
	2802	+
	2803	+ rest_addr = (ha->fdt_block_size >> 2) - 1;
	2804	+ sec_mask = ~rest_addr;
	2805	+
	2806	+ /* Lock semaphore */
	2807	+ rval = qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_LOCK);
	2808	+ if (rval != QLA_SUCCESS) {
	2809	+ ql_log(ql_log_warn, vha, 0xffff,
	2810	+ "Unable to lock flash semaphore.");
	2811	+ goto done;
	2812	+ }
	2813	+
	2814	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
	2815	+ "Unprotect flash...\n");
	2816	+ rval = qla24xx_unprotect_flash(vha);
	2817	+ if (rval) {
	2818	+ qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK);
	2819	+ ql_log(ql_log_warn, vha, 0x7096, "Failed unprotect flash\n");
	2820	+ goto done;
	2821	+ }
	2822	+
	2823	+ for (liter = 0; liter < dwords; liter++, faddr++) {
	2824	+ fdata = (faddr & sec_mask) << 2;
	2825	+
	2826	+ /* If start of sector */
	2827	+ if (!(faddr & rest_addr)) {
	2828	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
	2829	+ "Erase sector %#x...\n", faddr);
	2830	+ rval = qla24xx_erase_sector(vha, fdata);
	2831	+ if (rval) {
	2832	+ ql_dbg(ql_dbg_user, vha, 0x7007,
	2833	+ "Failed erase sector %#x\n", faddr);
	2834	+ goto write_protect;
	2835	+ }
	2836	+ }
	2837	+ }
	2838	+
	2839	+ if (ha->flags.secure_adapter) {
	2840	+ /*
	2841	+ * If adapter supports secure flash but FW doesn't,
	2842	+ * disable write protect, release semaphore and reset
	2843	+ * chip to execute ROM code in order to update region securely
	2844	+ */
	2845	+ if (!ha->flags.secure_fw) {
	2846	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
	2847	+ "Disable Write and Release Semaphore.");
	2848	+ rval = qla24xx_protect_flash(vha);
	2849	+ if (rval != QLA_SUCCESS) {
	2850	+ qla81xx_fac_semaphore_access(vha,
	2851	+ FAC_SEMAPHORE_UNLOCK);
	2852	+ ql_log(ql_log_warn, vha, 0xffff,
	2853	+ "Unable to protect flash.");
	2854	+ goto done;
	2855	+ }
	2856	+
	2857	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
	2858	+ "Reset chip to ROM.");
	2859	+ set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
	2860	+ set_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags);
	2861	+ qla2xxx_wake_dpc(vha);
	2862	+ rval = qla2x00_wait_for_chip_reset(vha);
	2863	+ if (rval != QLA_SUCCESS) {
	2864	+ ql_log(ql_log_warn, vha, 0xffff,
	2865	+ "Unable to reset to ROM code.");
	2866	+ goto done;
	2867	+ }
	2868	+ reset_to_rom = true;
	2869	+ ha->flags.fac_supported = 0;
	2870	+
	2871	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
	2872	+ "Lock Semaphore");
	2873	+ rval = qla2xxx_write_remote_register(vha,
	2874	+ FLASH_SEMAPHORE_REGISTER_ADDR, 0x00020002);
	2875	+ if (rval != QLA_SUCCESS) {
	2876	+ ql_log(ql_log_warn, vha, 0xffff,
	2877	+ "Unable to lock flash semaphore.");
	2878	+ goto done;
	2879	+ }
	2880	+
	2881	+ /* Unprotect flash */
	2882	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
	2883	+ "Enable Write.");
	2884	+ rval = qla2x00_write_ram_word(vha, 0x7ffd0101, 0);
	2885	+ if (rval) {
	2886	+ ql_log(ql_log_warn, vha, 0x7096,
	2887	+ "Failed unprotect flash\n");
	2888	+ goto done;
	2889	+ }
	2890	+ }
	2891	+
	2892	+ /* If region is secure, send Secure Flash MB Cmd */
	2893	+ if (region.attribute && buf_size_without_sfub) {
	2894	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
	2895	+ "Sending Secure Flash MB Cmd\n");
	2896	+ rval = qla28xx_secure_flash_update(vha, 0,
	2897	+ le16_to_cpu(region.code),
	2898	+ buf_size_without_sfub, sfub_dma,
	2899	+ sizeof(struct secure_flash_update_block) >> 2);
	2900	+ if (rval != QLA_SUCCESS) {
	2901	+ ql_log(ql_log_warn, vha, 0xffff,
	2902	+ "Secure Flash MB Cmd failed %x.", rval);
	2903	+ goto write_protect;
	2904	+ }
	2905	+ }
	2906	+
	2907	+ }
	2908	+
	2909	+ /* re-init flash offset */
	2910	+ faddr = offset >> 2;
	2911	+
	2912	+ for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
	2913	+ fdata = (faddr & sec_mask) << 2;
	2914	+
	2915	+ /* If smaller than a burst remaining */
	2916	+ if (dwords - liter < dburst)
	2917	+ dburst = dwords - liter;
	2918	+
	2919	+ /* Copy to dma buffer */
	2920	+ memcpy(optrom, dwptr, dburst << 2);
	2921	+
	2922	+ /* Burst write */
	2923	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
	2924	+ "Write burst (%#lx dwords)...\n", dburst);
	2925	+ rval = qla2x00_load_ram(vha, optrom_dma,
	2926	+ flash_data_addr(ha, faddr), dburst);
	2927	+ if (rval != QLA_SUCCESS) {
	2928	+ ql_log(ql_log_warn, vha, 0x7097,
	2929	+ "Failed burst write at %x (%p/%#llx)...\n",
	2930	+ flash_data_addr(ha, faddr), optrom,
	2931	+ (u64)optrom_dma);
	2932	+ break;
	2933	+ }
	2934	+
	2935	+ liter += dburst - 1;
	2936	+ faddr += dburst - 1;
	2937	+ dwptr += dburst - 1;
	2938	+ continue;
	2939	+ }
	2940	+
	2941	+write_protect:
	2942	+ ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
	2943	+ "Protect flash...\n");
	2944	+ ret = qla24xx_protect_flash(vha);
	2945	+ if (ret) {
	2946	+ qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK);
	2947	+ ql_log(ql_log_warn, vha, 0x7099,
	2948	+ "Failed protect flash\n");
	2949	+ rval = QLA_COMMAND_ERROR;
	2950	+ }
	2951	+
	2952	+ if (reset_to_rom == true) {
	2953	+ /* Schedule DPC to restart the RISC */
	2954	+ set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
	2955	+ qla2xxx_wake_dpc(vha);
	2956	+
	2957	+ ret = qla2x00_wait_for_hba_online(vha);
	2958	+ if (ret != QLA_SUCCESS) {
	2959	+ ql_log(ql_log_warn, vha, 0xffff,
	2960	+ "Adapter did not come out of reset\n");
	2961	+ rval = QLA_COMMAND_ERROR;
	2962	+ }
	2963	+ }
	2964	+
	2965	+done:
	2966	+ if (optrom)
	2967	+ dma_free_coherent(&ha->pdev->dev,
	2968	+ OPTROM_BURST_SIZE, optrom, optrom_dma);
	2969	+
	2970	+ return rval;
	2971	+}
	2972	+
2590	2973	int
2591		-qla24xx_write_optrom_data(struct scsi_qla_host vha, uint8_t buf,
	2974	+qla24xx_write_optrom_data(struct scsi_qla_host vha, void buf,
2592	2975	uint32_t offset, uint32_t length)
2593	2976	{
2594	2977	int rval;
..	..	@@ -2599,8 +2982,12 @@
2599	2982	set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2600	2983
2601	2984	/* Go with write. */
2602		- rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2603		- length >> 2);
	2985	+ if (IS_QLA28XX(ha))
	2986	+ rval = qla28xx_write_flash_data(vha, buf, offset >> 2,
	2987	+ length >> 2);
	2988	+ else
	2989	+ rval = qla24xx_write_flash_data(vha, buf, offset >> 2,
	2990	+ length >> 2);
2604	2991
2605	2992	clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2606	2993	scsi_unblock_requests(vha->host);
..	..	@@ -2608,8 +2995,8 @@
2608	2995	return rval;
2609	2996	}
2610	2997
2611		-uint8_t *
2612		-qla25xx_read_optrom_data(struct scsi_qla_host vha, uint8_t buf,
	2998	+void *
	2999	+qla25xx_read_optrom_data(struct scsi_qla_host vha, void buf,
2613	3000	uint32_t offset, uint32_t length)
2614	3001	{
2615	3002	int rval;
..	..	@@ -2620,7 +3007,7 @@
2620	3007	struct qla_hw_data *ha = vha->hw;
2621	3008
2622	3009	if (IS_QLA25XX(ha) \|\| IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\|
2623		- IS_QLA27XX(ha))
	3010	+ IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
2624	3011	goto try_fast;
2625	3012	if (offset & 0xfff)
2626	3013	goto slow_read;
..	..	@@ -2628,6 +3015,8 @@
2628	3015	goto slow_read;
2629	3016
2630	3017	try_fast:
	3018	+ if (offset & 0xff)
	3019	+ goto slow_read;
2631	3020	optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2632	3021	&optrom_dma, GFP_KERNEL);
2633	3022	if (!optrom) {
..	..	@@ -2874,7 +3263,7 @@
2874	3263	"Dumping fw "
2875	3264	"ver from flash:.\n");
2876	3265	ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
2877		- (uint8_t *)dbyte, 8);
	3266	+ dbyte, 32);
2878	3267
2879	3268	if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2880	3269	dcode[2] == 0xffff && dcode[3] == 0xffff) \|\|
..	..	@@ -2905,8 +3294,8 @@
2905	3294	{
2906	3295	int ret = QLA_SUCCESS;
2907	3296	uint32_t pcihdr, pcids;
2908		- uint32_t *dcode;
2909		- uint8_t *bcode;
	3297	+ uint32_t *dcode = mbuf;
	3298	+ uint8_t *bcode = mbuf;
2910	3299	uint8_t code_type, last_image;
2911	3300	struct qla_hw_data *ha = vha->hw;
2912	3301
..	..	@@ -2918,17 +3307,14 @@
2918	3307	memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2919	3308	memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2920	3309
2921		- dcode = mbuf;
2922		-
2923	3310	/* Begin with first PCI expansion ROM header. */
2924	3311	pcihdr = ha->flt_region_boot << 2;
2925	3312	last_image = 1;
2926	3313	do {
2927	3314	/* Verify PCI expansion ROM header. */
2928		- ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcihdr,
2929		- 0x20 * 4);
	3315	+ ha->isp_ops->read_optrom(vha, dcode, pcihdr, 0x20 * 4);
2930	3316	bcode = mbuf + (pcihdr % 4);
2931		- if (bcode[0x0] != 0x55 \|\| bcode[0x1] != 0xaa) {
	3317	+ if (memcmp(bcode, "\x55\xaa", 2)) {
2932	3318	/* No signature */
2933	3319	ql_log(ql_log_fatal, vha, 0x0154,
2934	3320	"No matching ROM signature.\n");
..	..	@@ -2939,13 +3325,11 @@
2939	3325	/* Locate PCI data structure. */
2940	3326	pcids = pcihdr + ((bcode[0x19] << 8) \| bcode[0x18]);
2941	3327
2942		- ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, pcids,
2943		- 0x20 * 4);
	3328	+ ha->isp_ops->read_optrom(vha, dcode, pcids, 0x20 * 4);
2944	3329	bcode = mbuf + (pcihdr % 4);
2945	3330
2946	3331	/* Validate signature of PCI data structure. */
2947		- if (bcode[0x0] != 'P' \|\| bcode[0x1] != 'C' \|\|
2948		- bcode[0x2] != 'I' \|\| bcode[0x3] != 'R') {
	3332	+ if (memcmp(bcode, "PCIR", 4)) {
2949	3333	/* Incorrect header. */
2950	3334	ql_log(ql_log_fatal, vha, 0x0155,
2951	3335	"PCI data struct not found pcir_adr=%x.\n", pcids);
..	..	@@ -2996,8 +3380,7 @@
2996	3380	/* Read firmware image information. */
2997	3381	memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2998	3382	dcode = mbuf;
2999		- ha->isp_ops->read_optrom(vha, (uint8_t *)dcode, ha->flt_region_fw << 2,
3000		- 0x20);
	3383	+ ha->isp_ops->read_optrom(vha, dcode, ha->flt_region_fw << 2, 0x20);
3001	3384	bcode = mbuf + (pcihdr % 4);
3002	3385
3003	3386	/* Validate signature of PCI data structure. */
..	..	@@ -3019,15 +3402,14 @@
3019	3402	qla24xx_get_flash_version(scsi_qla_host_t vha, void mbuf)
3020	3403	{
3021	3404	int ret = QLA_SUCCESS;
3022		- uint32_t pcihdr, pcids;
3023		- uint32_t *dcode;
3024		- uint8_t *bcode;
	3405	+ uint32_t pcihdr = 0, pcids = 0;
	3406	+ uint32_t *dcode = mbuf;
	3407	+ uint8_t *bcode = mbuf;
3025	3408	uint8_t code_type, last_image;
3026	3409	int i;
3027	3410	struct qla_hw_data *ha = vha->hw;
3028	3411	uint32_t faddr = 0;
3029		-
3030		- pcihdr = pcids = 0;
	3412	+ struct active_regions active_regions = { };
3031	3413
3032	3414	if (IS_P3P_TYPE(ha))
3033	3415	return ret;
..	..	@@ -3040,18 +3422,19 @@
3040	3422	memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3041	3423	memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3042	3424
3043		- dcode = mbuf;
3044	3425	pcihdr = ha->flt_region_boot << 2;
3045		- if (IS_QLA27XX(ha) &&
3046		- qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
3047		- pcihdr = ha->flt_region_boot_sec << 2;
	3426	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
	3427	+ qla27xx_get_active_image(vha, &active_regions);
	3428	+ if (active_regions.global == QLA27XX_SECONDARY_IMAGE) {
	3429	+ pcihdr = ha->flt_region_boot_sec << 2;
	3430	+ }
	3431	+ }
3048	3432
3049		- last_image = 1;
3050	3433	do {
3051	3434	/* Verify PCI expansion ROM header. */
3052	3435	qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
3053	3436	bcode = mbuf + (pcihdr % 4);
3054		- if (bcode[0x0] != 0x55 \|\| bcode[0x1] != 0xaa) {
	3437	+ if (memcmp(bcode, "\x55\xaa", 2)) {
3055	3438	/* No signature */
3056	3439	ql_log(ql_log_fatal, vha, 0x0059,
3057	3440	"No matching ROM signature.\n");
..	..	@@ -3066,11 +3449,11 @@
3066	3449	bcode = mbuf + (pcihdr % 4);
3067	3450
3068	3451	/* Validate signature of PCI data structure. */
3069		- if (bcode[0x0] != 'P' \|\| bcode[0x1] != 'C' \|\|
3070		- bcode[0x2] != 'I' \|\| bcode[0x3] != 'R') {
	3452	+ if (memcmp(bcode, "PCIR", 4)) {
3071	3453	/* Incorrect header. */
3072	3454	ql_log(ql_log_fatal, vha, 0x005a,
3073	3455	"PCI data struct not found pcir_adr=%x.\n", pcids);
	3456	+ ql_dump_buffer(ql_dbg_init, vha, 0x0059, dcode, 32);
3074	3457	ret = QLA_FUNCTION_FAILED;
3075	3458	break;
3076	3459	}
..	..	@@ -3117,30 +3500,25 @@
3117	3500
3118	3501	/* Read firmware image information. */
3119	3502	memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3120		- dcode = mbuf;
3121	3503	faddr = ha->flt_region_fw;
3122		- if (IS_QLA27XX(ha) &&
3123		- qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
3124		- faddr = ha->flt_region_fw_sec;
	3504	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
	3505	+ qla27xx_get_active_image(vha, &active_regions);
	3506	+ if (active_regions.global == QLA27XX_SECONDARY_IMAGE)
	3507	+ faddr = ha->flt_region_fw_sec;
	3508	+ }
3125	3509
3126		- qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
3127		- for (i = 0; i < 4; i++)
3128		- dcode[i] = be32_to_cpu(dcode[i]);
3129		-
3130		- if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
3131		- dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) \|\|
3132		- (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
3133		- dcode[3] == 0)) {
	3510	+ qla24xx_read_flash_data(vha, dcode, faddr, 8);
	3511	+ if (qla24xx_risc_firmware_invalid(dcode)) {
3134	3512	ql_log(ql_log_warn, vha, 0x005f,
3135	3513	"Unrecognized fw revision at %x.\n",
3136	3514	ha->flt_region_fw * 4);
	3515	+ ql_dump_buffer(ql_dbg_init, vha, 0x005f, dcode, 32);
3137	3516	} else {
3138		- ha->fw_revision[0] = dcode[0];
3139		- ha->fw_revision[1] = dcode[1];
3140		- ha->fw_revision[2] = dcode[2];
3141		- ha->fw_revision[3] = dcode[3];
	3517	+ for (i = 0; i < 4; i++)
	3518	+ ha->fw_revision[i] =
	3519	+ be32_to_cpu((__force __be32)dcode[4+i]);
3142	3520	ql_dbg(ql_dbg_init, vha, 0x0060,
3143		- "Firmware revision %d.%d.%d (%x).\n",
	3521	+ "Firmware revision (flash) %u.%u.%u (%x).\n",
3144	3522	ha->fw_revision[0], ha->fw_revision[1],
3145	3523	ha->fw_revision[2], ha->fw_revision[3]);
3146	3524	}
..	..	@@ -3152,20 +3530,18 @@
3152	3530	}
3153	3531
3154	3532	memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
3155		- dcode = mbuf;
3156		- ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
3157		- ha->flt_region_gold_fw << 2, 32);
3158		-
3159		- if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
3160		- dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
	3533	+ faddr = ha->flt_region_gold_fw;
	3534	+ qla24xx_read_flash_data(vha, dcode, ha->flt_region_gold_fw, 8);
	3535	+ if (qla24xx_risc_firmware_invalid(dcode)) {
3161	3536	ql_log(ql_log_warn, vha, 0x0056,
3162		- "Unrecognized golden fw at 0x%x.\n",
3163		- ha->flt_region_gold_fw * 4);
	3537	+ "Unrecognized golden fw at %#x.\n", faddr);
	3538	+ ql_dump_buffer(ql_dbg_init, vha, 0x0056, dcode, 32);
3164	3539	return ret;
3165	3540	}
3166	3541
3167		- for (i = 4; i < 8; i++)
3168		- ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
	3542	+ for (i = 0; i < 4; i++)
	3543	+ ha->gold_fw_version[i] =
	3544	+ be32_to_cpu((__force __be32)dcode[4+i]);
3169	3545
3170	3546	return ret;
3171	3547	}
..	..	@@ -3237,7 +3613,7 @@
3237	3613	fcp_prio_addr = ha->flt_region_fcp_prio;
3238	3614
3239	3615	/* first read the fcp priority data header from flash */
3240		- ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
	3616	+ ha->isp_ops->read_optrom(vha, ha->fcp_prio_cfg,
3241	3617	fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
3242	3618
3243	3619	if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
..	..	@@ -3245,10 +3621,10 @@
3245	3621
3246	3622	/* read remaining FCP CMD config data from flash */
3247	3623	fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
3248		- len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
	3624	+ len = ha->fcp_prio_cfg->num_entries * sizeof(struct qla_fcp_prio_entry);
3249	3625	max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
3250	3626
3251		- ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
	3627	+ ha->isp_ops->read_optrom(vha, &ha->fcp_prio_cfg->entry[0],
3252	3628	fcp_prio_addr << 2, (len < max_len ? len : max_len));
3253	3629
3254	3630	/* revalidate the entire FCP priority config data, including entries */