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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/scsi/qla2xxx/qla_nx.c
....@@ -1,11 +1,11 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * QLogic Fibre Channel HBA Driver
34  * Copyright (c)  2003-2014 QLogic Corporation
4
- *
5
- * See LICENSE.qla2xxx for copyright and licensing details.
65  */
76 #include "qla_def.h"
87 #include <linux/delay.h>
8
+#include <linux/io-64-nonatomic-lo-hi.h>
99 #include <linux/pci.h>
1010 #include <linux/ratelimit.h>
1111 #include <linux/vmalloc.h>
....@@ -369,7 +369,7 @@
369369 	/* Read back value to make sure write has gone through before trying
370370 	 * to use it.
371371 	 */
372
-	win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
372
+	win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase);
373373 	if (win_read != ha->crb_win) {
374374 		ql_dbg(ql_dbg_p3p, vha, 0xb000,
375375 		    "%s: Written crbwin (0x%x) "
....@@ -377,47 +377,6 @@
377377 		    __func__, ha->crb_win, win_read, off_in);
378378 	}
379379 	*off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
380
-}
381
-
382
-static inline unsigned long
383
-qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
384
-{
385
-	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
386
-	/* See if we are currently pointing to the region we want to use next */
387
-	if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
388
-		/* No need to change window. PCIX and PCIEregs are in both
389
-		 * regs are in both windows.
390
-		 */
391
-		return off;
392
-	}
393
-
394
-	if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
395
-		/* We are in first CRB window */
396
-		if (ha->curr_window != 0)
397
-			WARN_ON(1);
398
-		return off;
399
-	}
400
-
401
-	if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
402
-		/* We are in second CRB window */
403
-		off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
404
-
405
-		if (ha->curr_window != 1)
406
-			return off;
407
-
408
-		/* We are in the QM or direct access
409
-		 * register region - do nothing
410
-		 */
411
-		if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
412
-			(off < QLA82XX_PCI_CAMQM_MAX))
413
-			return off;
414
-	}
415
-	/* strange address given */
416
-	ql_dbg(ql_dbg_p3p, vha, 0xb001,
417
-	    "%s: Warning: unm_nic_pci_set_crbwindow "
418
-	    "called with an unknown address(%llx).\n",
419
-	    QLA2XXX_DRIVER_NAME, off);
420
-	return off;
421380 }
422381 
423382 static int
....@@ -519,7 +478,7 @@
519478 		qla82xx_crb_win_lock(ha);
520479 		qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
521480 	}
522
-	data = RD_REG_DWORD(off);
481
+	data = rd_reg_dword(off);
523482 
524483 	if (rv == 1) {
525484 		qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
....@@ -608,6 +567,7 @@
608567 	} else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
609568 		QLA82XX_ADDR_OCM0_MAX)) {
610569 		unsigned int temp1;
570
+
611571 		if ((addr & 0x00ff800) == 0xff800) {
612572 			ql_log(ql_log_warn, vha, 0xb004,
613573 			    "%s: QM access not handled.\n", __func__);
....@@ -935,17 +895,17 @@
935895 {
936896 	uint32_t  off_value, rval = 0;
937897 
938
-	WRT_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
898
+	wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
939899 
940900 	/* Read back value to make sure write has gone through */
941
-	RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
901
+	rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase);
942902 	off_value  = (off & 0x0000FFFF);
943903 
944904 	if (flag)
945
-		WRT_REG_DWORD(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
905
+		wrt_reg_dword(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
946906 			      data);
947907 	else
948
-		rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M +
908
+		rval = rd_reg_dword(off_value + CRB_INDIRECT_2M +
949909 				    ha->nx_pcibase);
950910 
951911 	return rval;
....@@ -990,6 +950,7 @@
990950 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
991951 {
992952 	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
953
+
993954 	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
994955 	qla82xx_wait_rom_busy(ha);
995956 	if (qla82xx_wait_rom_done(ha)) {
....@@ -1004,32 +965,28 @@
1004965 static int
1005966 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
1006967 {
1007
-	long timeout = 0;
1008
-	uint32_t done = 1 ;
1009968 	uint32_t val;
1010
-	int ret = 0;
969
+	int i, ret;
1011970 	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1012971 
1013972 	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1014
-	while ((done != 0) && (ret == 0)) {
973
+	for (i = 0; i < 50000; i++) {
1015974 		ret = qla82xx_read_status_reg(ha, &val);
1016
-		done = val & 1;
1017
-		timeout++;
975
+		if (ret < 0 || (val & 1) == 0)
976
+			return ret;
1018977 		udelay(10);
1019978 		cond_resched();
1020
-		if (timeout >= 50000) {
1021
-			ql_log(ql_log_warn, vha, 0xb00d,
1022
-			    "Timeout reached waiting for write finish.\n");
1023
-			return -1;
1024
-		}
1025979 	}
1026
-	return ret;
980
+	ql_log(ql_log_warn, vha, 0xb00d,
981
+	       "Timeout reached waiting for write finish.\n");
982
+	return -1;
1027983 }
1028984 
1029985 static int
1030986 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1031987 {
1032988 	uint32_t val;
989
+
1033990 	qla82xx_wait_rom_busy(ha);
1034991 	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1035992 	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
....@@ -1047,6 +1004,7 @@
10471004 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
10481005 {
10491006 	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1007
+
10501008 	if (qla82xx_flash_set_write_enable(ha))
10511009 		return -1;
10521010 	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
....@@ -1063,6 +1021,7 @@
10631021 qla82xx_write_disable_flash(struct qla_hw_data *ha)
10641022 {
10651023 	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1024
+
10661025 	qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
10671026 	if (qla82xx_wait_rom_done(ha)) {
10681027 		ql_log(ql_log_warn, vha, 0xb00f,
....@@ -1208,6 +1167,7 @@
12081167 	 * Offset 4: Offset and number of addr/value pairs
12091168 	 * that present in CRB initialize sequence
12101169 	 */
1170
+	n = 0;
12111171 	if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
12121172 	    qla82xx_rom_fast_read(ha, 4, &n) != 0) {
12131173 		ql_log(ql_log_fatal, vha, 0x006e,
....@@ -1436,6 +1396,7 @@
14361396 	long memaddr = BOOTLD_START;
14371397 	u64 data;
14381398 	u32 high, low;
1399
+
14391400 	size = (IMAGE_START - BOOTLD_START) / 8;
14401401 
14411402 	for (i = 0; i < size; i++) {
....@@ -1555,14 +1516,14 @@
15551516 	uint32_t i;
15561517 	struct qla82xx_uri_table_desc *directory =
15571518 		(struct qla82xx_uri_table_desc *)&unirom[0];
1558
-	__le32 offset;
1559
-	__le32 tab_type;
1560
-	__le32 entries = cpu_to_le32(directory->num_entries);
1519
+	uint32_t offset;
1520
+	uint32_t tab_type;
1521
+	uint32_t entries = le32_to_cpu(directory->num_entries);
15611522 
15621523 	for (i = 0; i < entries; i++) {
1563
-		offset = cpu_to_le32(directory->findex) +
1564
-		    (i * cpu_to_le32(directory->entry_size));
1565
-		tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1524
+		offset = le32_to_cpu(directory->findex) +
1525
+		    (i * le32_to_cpu(directory->entry_size));
1526
+		tab_type = get_unaligned_le32((u32 *)&unirom[offset] + 8);
15661527 
15671528 		if (tab_type == section)
15681529 			return (struct qla82xx_uri_table_desc *)&unirom[offset];
....@@ -1576,16 +1537,17 @@
15761537 	u32 section, u32 idx_offset)
15771538 {
15781539 	const u8 *unirom = ha->hablob->fw->data;
1579
-	int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1540
+	int idx = get_unaligned_le32((u32 *)&unirom[ha->file_prd_off] +
1541
+				     idx_offset);
15801542 	struct qla82xx_uri_table_desc *tab_desc = NULL;
1581
-	__le32 offset;
1543
+	uint32_t offset;
15821544 
15831545 	tab_desc = qla82xx_get_table_desc(unirom, section);
15841546 	if (!tab_desc)
15851547 		return NULL;
15861548 
1587
-	offset = cpu_to_le32(tab_desc->findex) +
1588
-	    (cpu_to_le32(tab_desc->entry_size) * idx);
1549
+	offset = le32_to_cpu(tab_desc->findex) +
1550
+	    (le32_to_cpu(tab_desc->entry_size) * idx);
15891551 
15901552 	return (struct qla82xx_uri_data_desc *)&unirom[offset];
15911553 }
....@@ -1600,7 +1562,7 @@
16001562 		uri_desc = qla82xx_get_data_desc(ha,
16011563 		    QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
16021564 		if (uri_desc)
1603
-			offset = cpu_to_le32(uri_desc->findex);
1565
+			offset = le32_to_cpu(uri_desc->findex);
16041566 	}
16051567 
16061568 	return (u8 *)&ha->hablob->fw->data[offset];
....@@ -1614,7 +1576,7 @@
16141576 		uri_desc =  qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
16151577 		    QLA82XX_URI_FIRMWARE_IDX_OFF);
16161578 		if (uri_desc)
1617
-			return cpu_to_le32(uri_desc->size);
1579
+			return le32_to_cpu(uri_desc->size);
16181580 	}
16191581 
16201582 	return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]);
....@@ -1630,7 +1592,7 @@
16301592 		uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
16311593 			QLA82XX_URI_FIRMWARE_IDX_OFF);
16321594 		if (uri_desc)
1633
-			offset = cpu_to_le32(uri_desc->findex);
1595
+			offset = le32_to_cpu(uri_desc->findex);
16341596 	}
16351597 
16361598 	return (u8 *)&ha->hablob->fw->data[offset];
....@@ -1757,11 +1719,14 @@
17571719  *
17581720  * Returns 0 on success.
17591721  */
1760
-void
1722
+int
17611723 qla82xx_reset_chip(scsi_qla_host_t *vha)
17621724 {
17631725 	struct qla_hw_data *ha = vha->hw;
1726
+
17641727 	ha->isp_ops->disable_intrs(ha);
1728
+
1729
+	return QLA_SUCCESS;
17651730 }
17661731 
17671732 void qla82xx_config_rings(struct scsi_qla_host *vha)
....@@ -1778,14 +1743,12 @@
17781743 	icb->response_q_inpointer = cpu_to_le16(0);
17791744 	icb->request_q_length = cpu_to_le16(req->length);
17801745 	icb->response_q_length = cpu_to_le16(rsp->length);
1781
-	icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1782
-	icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1783
-	icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1784
-	icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1746
+	put_unaligned_le64(req->dma, &icb->request_q_address);
1747
+	put_unaligned_le64(rsp->dma, &icb->response_q_address);
17851748 
1786
-	WRT_REG_DWORD(&reg->req_q_out[0], 0);
1787
-	WRT_REG_DWORD(&reg->rsp_q_in[0], 0);
1788
-	WRT_REG_DWORD(&reg->rsp_q_out[0], 0);
1749
+	wrt_reg_dword(&reg->req_q_out[0], 0);
1750
+	wrt_reg_dword(&reg->rsp_q_in[0], 0);
1751
+	wrt_reg_dword(&reg->rsp_q_out[0], 0);
17891752 }
17901753 
17911754 static int
....@@ -1840,8 +1803,8 @@
18401803 	struct qla82xx_uri_table_desc *ptab_desc = NULL;
18411804 	const uint8_t *unirom = ha->hablob->fw->data;
18421805 	uint32_t i;
1843
-	__le32 entries;
1844
-	__le32 flags, file_chiprev, offset;
1806
+	uint32_t entries;
1807
+	uint32_t flags, file_chiprev, offset;
18451808 	uint8_t chiprev = ha->chip_revision;
18461809 	/* Hardcoding mn_present flag for P3P */
18471810 	int mn_present = 0;
....@@ -1852,14 +1815,14 @@
18521815 	if (!ptab_desc)
18531816 		return -1;
18541817 
1855
-	entries = cpu_to_le32(ptab_desc->num_entries);
1818
+	entries = le32_to_cpu(ptab_desc->num_entries);
18561819 
18571820 	for (i = 0; i < entries; i++) {
1858
-		offset = cpu_to_le32(ptab_desc->findex) +
1859
-			(i * cpu_to_le32(ptab_desc->entry_size));
1860
-		flags = cpu_to_le32(*((int *)&unirom[offset] +
1821
+		offset = le32_to_cpu(ptab_desc->findex) +
1822
+			(i * le32_to_cpu(ptab_desc->entry_size));
1823
+		flags = le32_to_cpu(*((__le32 *)&unirom[offset] +
18611824 			QLA82XX_URI_FLAGS_OFF));
1862
-		file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1825
+		file_chiprev = le32_to_cpu(*((__le32 *)&unirom[offset] +
18631826 			QLA82XX_URI_CHIP_REV_OFF));
18641827 
18651828 		flagbit = mn_present ? 1 : 2;
....@@ -1875,7 +1838,7 @@
18751838 static int
18761839 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
18771840 {
1878
-	__le32 val;
1841
+	uint32_t val;
18791842 	uint32_t min_size;
18801843 	struct qla_hw_data *ha = vha->hw;
18811844 	const struct firmware *fw = ha->hablob->fw;
....@@ -1888,8 +1851,8 @@
18881851 
18891852 		min_size = QLA82XX_URI_FW_MIN_SIZE;
18901853 	} else {
1891
-		val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1892
-		if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
1854
+		val = get_unaligned_le32(&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1855
+		if (val != QLA82XX_BDINFO_MAGIC)
18931856 			return -EINVAL;
18941857 
18951858 		min_size = QLA82XX_FW_MIN_SIZE;
....@@ -1969,7 +1932,7 @@
19691932 	} while (--retries);
19701933 
19711934 	ql_log(ql_log_fatal, vha, 0x00ac,
1972
-	    "Rcv Peg initializatin failed: 0x%x.\n", val);
1935
+	    "Rcv Peg initialization failed: 0x%x.\n", val);
19731936 	read_lock(&ha->hw_lock);
19741937 	qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
19751938 	read_unlock(&ha->hw_lock);
....@@ -1977,7 +1940,7 @@
19771940 }
19781941 
19791942 /* ISR related functions */
1980
-static struct qla82xx_legacy_intr_set legacy_intr[] = \
1943
+static struct qla82xx_legacy_intr_set legacy_intr[] =
19811944 	QLA82XX_LEGACY_INTR_CONFIG;
19821945 
19831946 /*
....@@ -1989,17 +1952,18 @@
19891952 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
19901953 {
19911954 	uint16_t	cnt;
1992
-	uint16_t __iomem *wptr;
1955
+	__le16 __iomem *wptr;
19931956 	struct qla_hw_data *ha = vha->hw;
19941957 	struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1995
-	wptr = (uint16_t __iomem *)&reg->mailbox_out[1];
1958
+
1959
+	wptr = &reg->mailbox_out[1];
19961960 
19971961 	/* Load return mailbox registers. */
19981962 	ha->flags.mbox_int = 1;
19991963 	ha->mailbox_out[0] = mb0;
20001964 
20011965 	for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2002
-		ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
1966
+		ha->mailbox_out[cnt] = rd_reg_word(wptr);
20031967 		wptr++;
20041968 	}
20051969 
....@@ -2010,7 +1974,7 @@
20101974 
20111975 /**
20121976  * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2013
- * @irq:
1977
+ * @irq: interrupt number
20141978  * @dev_id: SCSI driver HA context
20151979  *
20161980  * Called by system whenever the host adapter generates an interrupt.
....@@ -2028,7 +1992,7 @@
20281992 	unsigned long	flags;
20291993 	unsigned long	iter;
20301994 	uint32_t	stat = 0;
2031
-	uint16_t	mb[4];
1995
+	uint16_t	mb[8];
20321996 
20331997 	rsp = (struct rsp_que *) dev_id;
20341998 	if (!rsp) {
....@@ -2061,8 +2025,8 @@
20612025 	vha = pci_get_drvdata(ha->pdev);
20622026 	for (iter = 1; iter--; ) {
20632027 
2064
-		if (RD_REG_DWORD(&reg->host_int)) {
2065
-			stat = RD_REG_DWORD(&reg->host_status);
2028
+		if (rd_reg_dword(&reg->host_int)) {
2029
+			stat = rd_reg_dword(&reg->host_status);
20662030 
20672031 			switch (stat & 0xff) {
20682032 			case 0x1:
....@@ -2074,9 +2038,9 @@
20742038 				break;
20752039 			case 0x12:
20762040 				mb[0] = MSW(stat);
2077
-				mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2078
-				mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2079
-				mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2041
+				mb[1] = rd_reg_word(&reg->mailbox_out[1]);
2042
+				mb[2] = rd_reg_word(&reg->mailbox_out[2]);
2043
+				mb[3] = rd_reg_word(&reg->mailbox_out[3]);
20802044 				qla2x00_async_event(vha, rsp, mb);
20812045 				break;
20822046 			case 0x13:
....@@ -2089,7 +2053,7 @@
20892053 				break;
20902054 			}
20912055 		}
2092
-		WRT_REG_DWORD(&reg->host_int, 0);
2056
+		wrt_reg_dword(&reg->host_int, 0);
20932057 	}
20942058 
20952059 	qla2x00_handle_mbx_completion(ha, status);
....@@ -2112,7 +2076,7 @@
21122076 	unsigned long flags;
21132077 	uint32_t stat = 0;
21142078 	uint32_t host_int = 0;
2115
-	uint16_t mb[4];
2079
+	uint16_t mb[8];
21162080 
21172081 	rsp = (struct rsp_que *) dev_id;
21182082 	if (!rsp) {
....@@ -2127,11 +2091,11 @@
21272091 	spin_lock_irqsave(&ha->hardware_lock, flags);
21282092 	vha = pci_get_drvdata(ha->pdev);
21292093 	do {
2130
-		host_int = RD_REG_DWORD(&reg->host_int);
2094
+		host_int = rd_reg_dword(&reg->host_int);
21312095 		if (qla2x00_check_reg32_for_disconnect(vha, host_int))
21322096 			break;
21332097 		if (host_int) {
2134
-			stat = RD_REG_DWORD(&reg->host_status);
2098
+			stat = rd_reg_dword(&reg->host_status);
21352099 
21362100 			switch (stat & 0xff) {
21372101 			case 0x1:
....@@ -2143,9 +2107,9 @@
21432107 				break;
21442108 			case 0x12:
21452109 				mb[0] = MSW(stat);
2146
-				mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2147
-				mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2148
-				mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2110
+				mb[1] = rd_reg_word(&reg->mailbox_out[1]);
2111
+				mb[2] = rd_reg_word(&reg->mailbox_out[2]);
2112
+				mb[3] = rd_reg_word(&reg->mailbox_out[3]);
21492113 				qla2x00_async_event(vha, rsp, mb);
21502114 				break;
21512115 			case 0x13:
....@@ -2158,7 +2122,7 @@
21582122 				break;
21592123 			}
21602124 		}
2161
-		WRT_REG_DWORD(&reg->host_int, 0);
2125
+		wrt_reg_dword(&reg->host_int, 0);
21622126 	} while (0);
21632127 
21642128 	qla2x00_handle_mbx_completion(ha, status);
....@@ -2188,11 +2152,11 @@
21882152 	reg = &ha->iobase->isp82;
21892153 	spin_lock_irqsave(&ha->hardware_lock, flags);
21902154 	vha = pci_get_drvdata(ha->pdev);
2191
-	host_int = RD_REG_DWORD(&reg->host_int);
2155
+	host_int = rd_reg_dword(&reg->host_int);
21922156 	if (qla2x00_check_reg32_for_disconnect(vha, host_int))
21932157 		goto out;
21942158 	qla24xx_process_response_queue(vha, rsp);
2195
-	WRT_REG_DWORD(&reg->host_int, 0);
2159
+	wrt_reg_dword(&reg->host_int, 0);
21962160 out:
21972161 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
21982162 	return IRQ_HANDLED;
....@@ -2208,7 +2172,7 @@
22082172 	int status = 0;
22092173 	uint32_t stat;
22102174 	uint32_t host_int = 0;
2211
-	uint16_t mb[4];
2175
+	uint16_t mb[8];
22122176 	unsigned long flags;
22132177 
22142178 	rsp = (struct rsp_que *) dev_id;
....@@ -2223,11 +2187,11 @@
22232187 	spin_lock_irqsave(&ha->hardware_lock, flags);
22242188 	vha = pci_get_drvdata(ha->pdev);
22252189 
2226
-	host_int = RD_REG_DWORD(&reg->host_int);
2190
+	host_int = rd_reg_dword(&reg->host_int);
22272191 	if (qla2x00_check_reg32_for_disconnect(vha, host_int))
22282192 		goto out;
22292193 	if (host_int) {
2230
-		stat = RD_REG_DWORD(&reg->host_status);
2194
+		stat = rd_reg_dword(&reg->host_status);
22312195 		switch (stat & 0xff) {
22322196 		case 0x1:
22332197 		case 0x2:
....@@ -2238,9 +2202,9 @@
22382202 			break;
22392203 		case 0x12:
22402204 			mb[0] = MSW(stat);
2241
-			mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2242
-			mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2243
-			mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2205
+			mb[1] = rd_reg_word(&reg->mailbox_out[1]);
2206
+			mb[2] = rd_reg_word(&reg->mailbox_out[2]);
2207
+			mb[3] = rd_reg_word(&reg->mailbox_out[3]);
22442208 			qla2x00_async_event(vha, rsp, mb);
22452209 			break;
22462210 		case 0x13:
....@@ -2252,7 +2216,7 @@
22522216 			    stat * 0xff);
22532217 			break;
22542218 		}
2255
-		WRT_REG_DWORD(&reg->host_int, 0);
2219
+		wrt_reg_dword(&reg->host_int, 0);
22562220 	}
22572221 out:
22582222 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
....@@ -2262,6 +2226,7 @@
22622226 qla82xx_enable_intrs(struct qla_hw_data *ha)
22632227 {
22642228 	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2229
+
22652230 	qla82xx_mbx_intr_enable(vha);
22662231 	spin_lock_irq(&ha->hardware_lock);
22672232 	if (IS_QLA8044(ha))
....@@ -2276,7 +2241,10 @@
22762241 qla82xx_disable_intrs(struct qla_hw_data *ha)
22772242 {
22782243 	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2279
-	qla82xx_mbx_intr_disable(vha);
2244
+
2245
+	if (ha->interrupts_on)
2246
+		qla82xx_mbx_intr_disable(vha);
2247
+
22802248 	spin_lock_irq(&ha->hardware_lock);
22812249 	if (IS_QLA8044(ha))
22822250 		qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1);
....@@ -2537,8 +2505,8 @@
25372505 	return qla82xx_check_rcvpeg_state(ha);
25382506 }
25392507 
2540
-static uint32_t *
2541
-qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2508
+static __le32 *
2509
+qla82xx_read_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr,
25422510 	uint32_t length)
25432511 {
25442512 	uint32_t i;
....@@ -2658,18 +2626,18 @@
26582626 /*
26592627  * Address and length are byte address
26602628  */
2661
-uint8_t *
2662
-qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2629
+void *
2630
+qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
26632631 	uint32_t offset, uint32_t length)
26642632 {
26652633 	scsi_block_requests(vha->host);
2666
-	qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
2634
+	qla82xx_read_flash_data(vha, buf, offset, length);
26672635 	scsi_unblock_requests(vha->host);
26682636 	return buf;
26692637 }
26702638 
26712639 static int
2672
-qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
2640
+qla82xx_write_flash_data(struct scsi_qla_host *vha, __le32 *dwptr,
26732641 	uint32_t faddr, uint32_t dwords)
26742642 {
26752643 	int ret;
....@@ -2746,7 +2714,7 @@
27462714 		}
27472715 
27482716 		ret = qla82xx_write_flash_dword(ha, faddr,
2749
-		    cpu_to_le32(*dwptr));
2717
+						le32_to_cpu(*dwptr));
27502718 		if (ret) {
27512719 			ql_dbg(ql_dbg_p3p, vha, 0xb020,
27522720 			    "Unable to program flash address=%x data=%x.\n",
....@@ -2767,15 +2735,14 @@
27672735 }
27682736 
27692737 int
2770
-qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2738
+qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf,
27712739 	uint32_t offset, uint32_t length)
27722740 {
27732741 	int rval;
27742742 
27752743 	/* Suspend HBA. */
27762744 	scsi_block_requests(vha->host);
2777
-	rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
2778
-		length >> 2);
2745
+	rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2);
27792746 	scsi_unblock_requests(vha->host);
27802747 
27812748 	/* Convert return ISP82xx to generic */
....@@ -2807,10 +2774,10 @@
28072774 	if (ql2xdbwr)
28082775 		qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval);
28092776 	else {
2810
-		WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2777
+		wrt_reg_dword(ha->nxdb_wr_ptr, dbval);
28112778 		wmb();
2812
-		while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
2813
-			WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2779
+		while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) {
2780
+			wrt_reg_dword(ha->nxdb_wr_ptr, dbval);
28142781 			wmb();
28152782 		}
28162783 	}
....@@ -3018,7 +2985,7 @@
30182985 	/* Set DEV_FAILED flag to disable timer */
30192986 	vha->device_flags |= DFLG_DEV_FAILED;
30202987 	qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3021
-	qla2x00_mark_all_devices_lost(vha, 0);
2988
+	qla2x00_mark_all_devices_lost(vha);
30222989 	vha->flags.online = 0;
30232990 	vha->flags.init_done = 0;
30242991 }
....@@ -3276,7 +3243,7 @@
32763243 		case QLA8XXX_DEV_NEED_QUIESCENT:
32773244 			qla82xx_need_qsnt_handler(vha);
32783245 			/* Reset timeout value after quiescence handler */
3279
-			dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
3246
+			dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
32803247 							 * HZ);
32813248 			break;
32823249 		case QLA8XXX_DEV_QUIESCENT:
....@@ -3291,7 +3258,7 @@
32913258 			qla82xx_idc_lock(ha);
32923259 
32933260 			/* Reset timeout value after quiescence handler */
3294
-			dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
3261
+			dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
32953262 							 * HZ);
32963263 			break;
32973264 		case QLA8XXX_DEV_FAILED:
....@@ -3676,7 +3643,7 @@
36763643 			for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
36773644 				sp = req->outstanding_cmds[cnt];
36783645 				if (sp) {
3679
-					if ((!sp->u.scmd.ctx ||
3646
+					if ((!sp->u.scmd.crc_ctx ||
36803647 					    (sp->flags &
36813648 						SRB_FCP_CMND_DMA_VALID)) &&
36823649 						!ha->flags.isp82xx_fw_hung) {
....@@ -3699,11 +3666,13 @@
36993666 		spin_unlock_irqrestore(&ha->hardware_lock, flags);
37003667 
37013668 		/* Wait for pending cmds (physical and virtual) to complete */
3702
-		if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3669
+		if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
37033670 		    WAIT_HOST) == QLA_SUCCESS) {
37043671 			ql_dbg(ql_dbg_init, vha, 0x00b3,
37053672 			    "Done wait for "
37063673 			    "pending commands.\n");
3674
+		} else {
3675
+			WARN_ON_ONCE(true);
37073676 		}
37083677 	}
37093678 }
....@@ -3711,7 +3680,7 @@
37113680 /* Minidump related functions */
37123681 static int
37133682 qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3714
-	qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3683
+	qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
37153684 {
37163685 	struct qla_hw_data *ha = vha->hw;
37173686 	struct qla82xx_md_entry_crb *crb_entry;
....@@ -3828,12 +3797,12 @@
38283797 
38293798 static void
38303799 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3831
-	qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3800
+	qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
38323801 {
38333802 	struct qla_hw_data *ha = vha->hw;
38343803 	uint32_t r_addr, r_stride, loop_cnt, i, r_value;
38353804 	struct qla82xx_md_entry_rdocm *ocm_hdr;
3836
-	uint32_t *data_ptr = *d_ptr;
3805
+	__le32 *data_ptr = *d_ptr;
38373806 
38383807 	ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
38393808 	r_addr = ocm_hdr->read_addr;
....@@ -3841,7 +3810,7 @@
38413810 	loop_cnt = ocm_hdr->op_count;
38423811 
38433812 	for (i = 0; i < loop_cnt; i++) {
3844
-		r_value = RD_REG_DWORD(r_addr + ha->nx_pcibase);
3813
+		r_value = rd_reg_dword(r_addr + ha->nx_pcibase);
38453814 		*data_ptr++ = cpu_to_le32(r_value);
38463815 		r_addr += r_stride;
38473816 	}
....@@ -3850,12 +3819,12 @@
38503819 
38513820 static void
38523821 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3853
-	qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3822
+	qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
38543823 {
38553824 	struct qla_hw_data *ha = vha->hw;
38563825 	uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
38573826 	struct qla82xx_md_entry_mux *mux_hdr;
3858
-	uint32_t *data_ptr = *d_ptr;
3827
+	__le32 *data_ptr = *d_ptr;
38593828 
38603829 	mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
38613830 	r_addr = mux_hdr->read_addr;
....@@ -3876,12 +3845,12 @@
38763845 
38773846 static void
38783847 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3879
-	qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3848
+	qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
38803849 {
38813850 	struct qla_hw_data *ha = vha->hw;
38823851 	uint32_t r_addr, r_stride, loop_cnt, i, r_value;
38833852 	struct qla82xx_md_entry_crb *crb_hdr;
3884
-	uint32_t *data_ptr = *d_ptr;
3853
+	__le32 *data_ptr = *d_ptr;
38853854 
38863855 	crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
38873856 	r_addr = crb_hdr->addr;
....@@ -3899,7 +3868,7 @@
38993868 
39003869 static int
39013870 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3902
-	qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3871
+	qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
39033872 {
39043873 	struct qla_hw_data *ha = vha->hw;
39053874 	uint32_t addr, r_addr, c_addr, t_r_addr;
....@@ -3908,7 +3877,7 @@
39083877 	uint32_t c_value_w, c_value_r;
39093878 	struct qla82xx_md_entry_cache *cache_hdr;
39103879 	int rval = QLA_FUNCTION_FAILED;
3911
-	uint32_t *data_ptr = *d_ptr;
3880
+	__le32 *data_ptr = *d_ptr;
39123881 
39133882 	cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
39143883 	loop_count = cache_hdr->op_count;
....@@ -3958,14 +3927,14 @@
39583927 
39593928 static void
39603929 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3961
-	qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3930
+	qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
39623931 {
39633932 	struct qla_hw_data *ha = vha->hw;
39643933 	uint32_t addr, r_addr, c_addr, t_r_addr;
39653934 	uint32_t i, k, loop_count, t_value, r_cnt, r_value;
39663935 	uint32_t c_value_w;
39673936 	struct qla82xx_md_entry_cache *cache_hdr;
3968
-	uint32_t *data_ptr = *d_ptr;
3937
+	__le32 *data_ptr = *d_ptr;
39693938 
39703939 	cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
39713940 	loop_count = cache_hdr->op_count;
....@@ -3993,14 +3962,14 @@
39933962 
39943963 static void
39953964 qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
3996
-	qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3965
+	qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
39973966 {
39983967 	struct qla_hw_data *ha = vha->hw;
39993968 	uint32_t s_addr, r_addr;
40003969 	uint32_t r_stride, r_value, r_cnt, qid = 0;
40013970 	uint32_t i, k, loop_cnt;
40023971 	struct qla82xx_md_entry_queue *q_hdr;
4003
-	uint32_t *data_ptr = *d_ptr;
3972
+	__le32 *data_ptr = *d_ptr;
40043973 
40053974 	q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
40063975 	s_addr = q_hdr->select_addr;
....@@ -4023,13 +3992,13 @@
40233992 
40243993 static void
40253994 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
4026
-	qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3995
+	qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
40273996 {
40283997 	struct qla_hw_data *ha = vha->hw;
40293998 	uint32_t r_addr, r_value;
40303999 	uint32_t i, loop_cnt;
40314000 	struct qla82xx_md_entry_rdrom *rom_hdr;
4032
-	uint32_t *data_ptr = *d_ptr;
4001
+	__le32 *data_ptr = *d_ptr;
40334002 
40344003 	rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
40354004 	r_addr = rom_hdr->read_addr;
....@@ -4049,7 +4018,7 @@
40494018 
40504019 static int
40514020 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4052
-	qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4021
+	qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
40534022 {
40544023 	struct qla_hw_data *ha = vha->hw;
40554024 	uint32_t r_addr, r_value, r_data;
....@@ -4057,7 +4026,7 @@
40574026 	struct qla82xx_md_entry_rdmem *m_hdr;
40584027 	unsigned long flags;
40594028 	int rval = QLA_FUNCTION_FAILED;
4060
-	uint32_t *data_ptr = *d_ptr;
4029
+	__le32 *data_ptr = *d_ptr;
40614030 
40624031 	m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
40634032 	r_addr = m_hdr->read_addr;
....@@ -4150,12 +4119,12 @@
41504119 	int no_entry_hdr = 0;
41514120 	qla82xx_md_entry_hdr_t *entry_hdr;
41524121 	struct qla82xx_md_template_hdr *tmplt_hdr;
4153
-	uint32_t *data_ptr;
4122
+	__le32 *data_ptr;
41544123 	uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
41554124 	int i = 0, rval = QLA_FUNCTION_FAILED;
41564125 
41574126 	tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4158
-	data_ptr = (uint32_t *)ha->md_dump;
4127
+	data_ptr = ha->md_dump;
41594128 
41604129 	if (ha->fw_dumped) {
41614130 		ql_log(ql_log_warn, vha, 0xb037,
....@@ -4164,7 +4133,7 @@
41644133 		goto md_failed;
41654134 	}
41664135 
4167
-	ha->fw_dumped = 0;
4136
+	ha->fw_dumped = false;
41684137 
41694138 	if (!ha->md_tmplt_hdr || !ha->md_dump) {
41704139 		ql_log(ql_log_warn, vha, 0xb038,
....@@ -4222,7 +4191,7 @@
42224191 		goto md_failed;
42234192 	}
42244193 
4225
-	entry_hdr = (qla82xx_md_entry_hdr_t *) \
4194
+	entry_hdr = (qla82xx_md_entry_hdr_t *)
42264195 	    (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
42274196 
42284197 	/* Walk through the entry headers */
....@@ -4329,7 +4298,7 @@
43294298 		data_collected = (uint8_t *)data_ptr -
43304299 		    (uint8_t *)ha->md_dump;
43314300 skip_nxt_entry:
4332
-		entry_hdr = (qla82xx_md_entry_hdr_t *) \
4301
+		entry_hdr = (qla82xx_md_entry_hdr_t *)
43334302 		    (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
43344303 	}
43354304 
....@@ -4344,7 +4313,7 @@
43444313 	ql_log(ql_log_info, vha, 0xb044,
43454314 	    "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
43464315 	    vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4347
-	ha->fw_dumped = 1;
4316
+	ha->fw_dumped = true;
43484317 	qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
43494318 
43504319 md_failed:
....@@ -4464,6 +4433,7 @@
44644433 
44654434 	int rval;
44664435 	struct qla_hw_data *ha = vha->hw;
4436
+
44674437 	qla82xx_idc_lock(ha);
44684438 	rval = qla82xx_mbx_beacon_ctl(vha, 1);
44694439 
....@@ -4484,6 +4454,7 @@
44844454 
44854455 	int rval;
44864456 	struct qla_hw_data *ha = vha->hw;
4457
+
44874458 	qla82xx_idc_lock(ha);
44884459 	rval = qla82xx_mbx_beacon_ctl(vha, 0);
44894460 
....@@ -4499,7 +4470,7 @@
44994470 }
45004471 
45014472 void
4502
-qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
4473
+qla82xx_fw_dump(scsi_qla_host_t *vha)
45034474 {
45044475 	struct qla_hw_data *ha = vha->hw;
45054476