hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da
kernel/drivers/rtc/rtc-zynqmp.c
....@@ -1,19 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
34 *
45 * Copyright (C) 2015 Xilinx, Inc.
5
- *
6
- * This program is free software; you can redistribute it and/or modify it
7
- * under the terms and conditions of the GNU General Public License,
8
- * version 2, as published by the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope it will be useful, but WITHOUT
11
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13
- * more details.
14
- *
15
- * You should have received a copy of the GNU General Public License along with
16
- * this program. If not, see <http://www.gnu.org/licenses/>.
176 *
187 */
198
....@@ -49,14 +38,15 @@
4938
5039 #define RTC_CALIB_DEF 0x198233
5140 #define RTC_CALIB_MASK 0x1FFFFF
52
-#define RTC_SEC_MAX_VAL 0xFFFFFFFF
41
+#define RTC_ALRM_MASK BIT(1)
42
+#define RTC_MSEC 1000
5343
5444 struct xlnx_rtc_dev {
5545 struct rtc_device *rtc;
5646 void __iomem *reg_base;
5747 int alarm_irq;
5848 int sec_irq;
59
- int calibval;
49
+ unsigned int calibval;
6050 };
6151
6252 static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
....@@ -70,9 +60,6 @@
7060 * to get the correct time on read.
7161 */
7262 new_time = rtc_tm_to_time64(tm) + 1;
73
-
74
- if (new_time > RTC_SEC_MAX_VAL)
75
- return -EINVAL;
7663
7764 /*
7865 * Writing into calibration register will clear the Tick Counter and
....@@ -109,7 +96,7 @@
10996 * RTC has updated the CURRENT_TIME with the time written into
11097 * SET_TIME_WRITE register.
11198 */
112
- rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm);
99
+ read_time = readl(xrtcdev->reg_base + RTC_CUR_TM);
113100 } else {
114101 /*
115102 * Time written in SET_TIME_WRITE has not yet updated into
....@@ -119,8 +106,8 @@
119106 * reading.
120107 */
121108 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
122
- rtc_time64_to_tm(read_time, tm);
123109 }
110
+ rtc_time64_to_tm(read_time, tm);
124111
125112 return 0;
126113 }
....@@ -138,11 +125,28 @@
138125 static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
139126 {
140127 struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
128
+ unsigned int status;
129
+ ulong timeout;
141130
142
- if (enabled)
131
+ timeout = jiffies + msecs_to_jiffies(RTC_MSEC);
132
+
133
+ if (enabled) {
134
+ while (1) {
135
+ status = readl(xrtcdev->reg_base + RTC_INT_STS);
136
+ if (!((status & RTC_ALRM_MASK) == RTC_ALRM_MASK))
137
+ break;
138
+
139
+ if (time_after_eq(jiffies, timeout)) {
140
+ dev_err(dev, "Time out occur, while clearing alarm status bit\n");
141
+ return -ETIMEDOUT;
142
+ }
143
+ writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
144
+ }
145
+
143146 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
144
- else
147
+ } else {
145148 writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
149
+ }
146150
147151 return 0;
148152 }
....@@ -153,9 +157,6 @@
153157 unsigned long alarm_time;
154158
155159 alarm_time = rtc_tm_to_time64(&alrm->time);
156
-
157
- if (alarm_time > RTC_SEC_MAX_VAL)
158
- return -EINVAL;
159160
160161 writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
161162
....@@ -201,8 +202,8 @@
201202 if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
202203 return IRQ_NONE;
203204
204
- /* Clear RTC_INT_ALRM interrupt only */
205
- writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
205
+ /* Disable RTC_INT_ALRM interrupt only */
206
+ writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
206207
207208 if (status & RTC_INT_ALRM)
208209 rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
....@@ -213,7 +214,6 @@
213214 static int xlnx_rtc_probe(struct platform_device *pdev)
214215 {
215216 struct xlnx_rtc_dev *xrtcdev;
216
- struct resource *res;
217217 int ret;
218218
219219 xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
....@@ -222,17 +222,20 @@
222222
223223 platform_set_drvdata(pdev, xrtcdev);
224224
225
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
225
+ xrtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
226
+ if (IS_ERR(xrtcdev->rtc))
227
+ return PTR_ERR(xrtcdev->rtc);
226228
227
- xrtcdev->reg_base = devm_ioremap_resource(&pdev->dev, res);
229
+ xrtcdev->rtc->ops = &xlnx_rtc_ops;
230
+ xrtcdev->rtc->range_max = U32_MAX;
231
+
232
+ xrtcdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
228233 if (IS_ERR(xrtcdev->reg_base))
229234 return PTR_ERR(xrtcdev->reg_base);
230235
231236 xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
232
- if (xrtcdev->alarm_irq < 0) {
233
- dev_err(&pdev->dev, "no irq resource\n");
237
+ if (xrtcdev->alarm_irq < 0)
234238 return xrtcdev->alarm_irq;
235
- }
236239 ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
237240 xlnx_rtc_interrupt, 0,
238241 dev_name(&pdev->dev), xrtcdev);
....@@ -242,10 +245,8 @@
242245 }
243246
244247 xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
245
- if (xrtcdev->sec_irq < 0) {
246
- dev_err(&pdev->dev, "no irq resource\n");
248
+ if (xrtcdev->sec_irq < 0)
247249 return xrtcdev->sec_irq;
248
- }
249250 ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
250251 xlnx_rtc_interrupt, 0,
251252 dev_name(&pdev->dev), xrtcdev);
....@@ -263,9 +264,7 @@
263264
264265 device_init_wakeup(&pdev->dev, 1);
265266
266
- xrtcdev->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
267
- &xlnx_rtc_ops, THIS_MODULE);
268
- return PTR_ERR_OR_ZERO(xrtcdev->rtc);
267
+ return rtc_register_device(xrtcdev->rtc);
269268 }
270269
271270 static int xlnx_rtc_remove(struct platform_device *pdev)