add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/rtc/rtc-snvs.c
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@@ -32,6 +32,14 @@
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 #define SNVS_LPPGDR_INIT	0x41736166
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 #define CNTR_TO_SECS_SH		15
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+/* The maximum RTC clock cycles that are allowed to pass between two
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+ * consecutive clock counter register reads. If the values are corrupted a
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+ * bigger difference is expected. The RTC frequency is 32kHz. With 320 cycles
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+ * we end at 10ms which should be enough for most cases. If it once takes
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+ * longer than expected we do a retry.
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+ */
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+#define MAX_RTC_READ_DIFF_CYCLES	320
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+
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 struct snvs_rtc_data {
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 	struct rtc_device *rtc;
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 	struct regmap *regmap;
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@@ -56,6 +64,7 @@
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 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
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 {
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 	u64 read1, read2;
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+	s64 diff;
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 	unsigned int timeout = 100;
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 	/* As expected, the registers might update between the read of the LSB
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@@ -66,7 +75,8 @@
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 	do {
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 		read2 = read1;
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 		read1 = rtc_read_lpsrt(data);
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-	} while (read1 != read2 && --timeout);
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+		diff = read1 - read2;
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+	} while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
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 	if (!timeout)
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 		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
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@@ -78,13 +88,15 @@
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 static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
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 {
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 	u32 count1, count2;
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+	s32 diff;
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 	unsigned int timeout = 100;
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 	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
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 	do {
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 		count2 = count1;
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 		regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
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-	} while (count1 != count2 && --timeout);
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+		diff = count1 - count2;
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+	} while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
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 	if (!timeout) {
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 		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
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 		return -ETIMEDOUT;