hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da
kernel/drivers/pwm/pwm-tegra.c
....@@ -142,8 +142,8 @@
142142 * source clock rate as required_clk_rate, PWM controller will
143143 * be able to configure the requested period.
144144 */
145
- required_clk_rate =
146
- (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
145
+ required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
146
+ period_ns);
147147
148148 err = clk_set_rate(pc->clk, required_clk_rate);
149149 if (err < 0)