add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/pwm/pwm-mtk-disp.c
..
..
@@ -74,6 +74,19 @@
74
74
 	u64 div, rate;
75
75
 	int err;
76
76
 
77
+	err = clk_prepare_enable(mdp->clk_main);
78
+	if (err < 0) {
79
+		dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
80
+		return err;
81
+	}
82
+
83
+	err = clk_prepare_enable(mdp->clk_mm);
84
+	if (err < 0) {
85
+		dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
86
+		clk_disable_unprepare(mdp->clk_main);
87
+		return err;
88
+	}
89
+
77
90
 	/*
78
91
 	 * Find period, high_width and clk_div to suit duty_ns and period_ns.
79
92
 	 * Calculate proper div value to keep period value in the bound.
..
..
@@ -87,8 +100,11 @@
87
100
 	rate = clk_get_rate(mdp->clk_main);
88
101
 	clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >>
89
102
 			  PWM_PERIOD_BIT_WIDTH;
90
-	if (clk_div > PWM_CLKDIV_MAX)
103
+	if (clk_div > PWM_CLKDIV_MAX) {
104
+		clk_disable_unprepare(mdp->clk_mm);
105
+		clk_disable_unprepare(mdp->clk_main);
91
106
 		return -EINVAL;
107
+	}
92
108
 
93
109
 	div = NSEC_PER_SEC * (clk_div + 1);
94
110
 	period = div64_u64(rate * period_ns, div);
..
..
@@ -98,14 +114,17 @@
98
114
 	high_width = div64_u64(rate * duty_ns, div);
99
115
 	value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
100
116
 
101
-	err = clk_enable(mdp->clk_main);
102
-	if (err < 0)
103
-		return err;
104
-
105
-	err = clk_enable(mdp->clk_mm);
106
-	if (err < 0) {
107
-		clk_disable(mdp->clk_main);
108
-		return err;
117
+	if (mdp->data->bls_debug && !mdp->data->has_commit) {
118
+		/*
119
+		 * For MT2701, disable double buffer before writing register
120
+		 * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
121
+		 */
122
+		mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
123
+					 mdp->data->bls_debug_mask,
124
+					 mdp->data->bls_debug_mask);
125
+		mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
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+					 mdp->data->con0_sel,
127
+					 mdp->data->con0_sel);
109
128
 	}
110
129
 
111
130
 	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
..
..
@@ -124,8 +143,8 @@
124
143
 					 0x0);
125
144
 	}
126
145
 
127
-	clk_disable(mdp->clk_mm);
128
-	clk_disable(mdp->clk_main);
146
+	clk_disable_unprepare(mdp->clk_mm);
147
+	clk_disable_unprepare(mdp->clk_main);
129
148
 
130
149
 	return 0;
131
150
 }
..
..
@@ -135,13 +154,16 @@
135
154
 	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
136
155
 	int err;
137
156
 
138
-	err = clk_enable(mdp->clk_main);
139
-	if (err < 0)
140
-		return err;
141
-
142
-	err = clk_enable(mdp->clk_mm);
157
+	err = clk_prepare_enable(mdp->clk_main);
143
158
 	if (err < 0) {
144
-		clk_disable(mdp->clk_main);
159
+		dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
160
+		return err;
161
+	}
162
+
163
+	err = clk_prepare_enable(mdp->clk_mm);
164
+	if (err < 0) {
165
+		dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
166
+		clk_disable_unprepare(mdp->clk_main);
145
167
 		return err;
146
168
 	}
147
169
 
..
..
@@ -158,8 +180,8 @@
158
180
 	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
159
181
 				 0x0);
160
182
 
161
-	clk_disable(mdp->clk_mm);
162
-	clk_disable(mdp->clk_main);
183
+	clk_disable_unprepare(mdp->clk_mm);
184
+	clk_disable_unprepare(mdp->clk_main);
163
185
 }
164
186
 
165
187
 static const struct pwm_ops mtk_disp_pwm_ops = {
..
..
@@ -194,14 +216,6 @@
194
216
 	if (IS_ERR(mdp->clk_mm))
195
217
 		return PTR_ERR(mdp->clk_mm);
196
218
 
197
-	ret = clk_prepare(mdp->clk_main);
198
-	if (ret < 0)
199
-		return ret;
200
-
201
-	ret = clk_prepare(mdp->clk_mm);
202
-	if (ret < 0)
203
-		goto disable_clk_main;
204
-
205
219
 	mdp->chip.dev = &pdev->dev;
206
220
 	mdp->chip.ops = &mtk_disp_pwm_ops;
207
221
 	mdp->chip.base = -1;
..
..
@@ -209,44 +223,22 @@
209
223
 
210
224
 	ret = pwmchip_add(&mdp->chip);
211
225
 	if (ret < 0) {
212
-		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
213
-		goto disable_clk_mm;
226
+		dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
227
+		return ret;
214
228
 	}
215
229
 
216
230
 	platform_set_drvdata(pdev, mdp);
217
231
 
218
-	/*
219
-	 * For MT2701, disable double buffer before writing register
220
-	 * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
221
-	 */
222
-	if (!mdp->data->has_commit) {
223
-		mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
224
-					 mdp->data->bls_debug_mask,
225
-					 mdp->data->bls_debug_mask);
226
-		mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
227
-					 mdp->data->con0_sel,
228
-					 mdp->data->con0_sel);
229
-	}
230
-
231
232
 	return 0;
232
-
233
-disable_clk_mm:
234
-	clk_unprepare(mdp->clk_mm);
235
-disable_clk_main:
236
-	clk_unprepare(mdp->clk_main);
237
-	return ret;
238
233
 }
239
234
 
240
235
 static int mtk_disp_pwm_remove(struct platform_device *pdev)
241
236
 {
242
237
 	struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
243
-	int ret;
244
238
 
245
-	ret = pwmchip_remove(&mdp->chip);
246
-	clk_unprepare(mdp->clk_mm);
247
-	clk_unprepare(mdp->clk_main);
239
+	pwmchip_remove(&mdp->chip);
248
240
 
249
-	return ret;
241
+	return 0;
250
242
 }
251
243
 
252
244
 static const struct mtk_pwm_data mt2701_pwm_data = {