.. | .. |
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51 | 51 | if (duty_cycles > 255) |
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52 | 52 | duty_cycles = 255; |
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53 | 53 | |
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54 | | - val = readl(lpc32xx->base + (pwm->hwpwm << 2)); |
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| 54 | + val = readl(lpc32xx->base); |
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55 | 55 | val &= ~0xFFFF; |
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56 | 56 | val |= (period_cycles << 8) | duty_cycles; |
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57 | | - writel(val, lpc32xx->base + (pwm->hwpwm << 2)); |
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| 57 | + writel(val, lpc32xx->base); |
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58 | 58 | |
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59 | 59 | return 0; |
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60 | 60 | } |
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.. | .. |
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69 | 69 | if (ret) |
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70 | 70 | return ret; |
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71 | 71 | |
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72 | | - val = readl(lpc32xx->base + (pwm->hwpwm << 2)); |
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| 72 | + val = readl(lpc32xx->base); |
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73 | 73 | val |= PWM_ENABLE; |
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74 | | - writel(val, lpc32xx->base + (pwm->hwpwm << 2)); |
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| 74 | + writel(val, lpc32xx->base); |
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75 | 75 | |
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76 | 76 | return 0; |
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77 | 77 | } |
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.. | .. |
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81 | 81 | struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); |
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82 | 82 | u32 val; |
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83 | 83 | |
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84 | | - val = readl(lpc32xx->base + (pwm->hwpwm << 2)); |
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| 84 | + val = readl(lpc32xx->base); |
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85 | 85 | val &= ~PWM_ENABLE; |
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86 | | - writel(val, lpc32xx->base + (pwm->hwpwm << 2)); |
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| 86 | + writel(val, lpc32xx->base); |
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87 | 87 | |
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88 | 88 | clk_disable_unprepare(lpc32xx->clk); |
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89 | 89 | } |
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.. | .. |
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121 | 121 | lpc32xx->chip.base = -1; |
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122 | 122 | |
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123 | 123 | /* If PWM is disabled, configure the output to the default value */ |
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124 | | - val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); |
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| 124 | + val = readl(lpc32xx->base); |
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125 | 125 | val &= ~PWM_PIN_LEVEL; |
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126 | | - writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); |
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| 126 | + writel(val, lpc32xx->base); |
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127 | 127 | |
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128 | 128 | ret = pwmchip_add(&lpc32xx->chip); |
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129 | 129 | if (ret < 0) { |
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