hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da
kernel/drivers/pwm/pwm-lpc32xx.c
....@@ -51,10 +51,10 @@
5151 if (duty_cycles > 255)
5252 duty_cycles = 255;
5353
54
- val = readl(lpc32xx->base + (pwm->hwpwm << 2));
54
+ val = readl(lpc32xx->base);
5555 val &= ~0xFFFF;
5656 val |= (period_cycles << 8) | duty_cycles;
57
- writel(val, lpc32xx->base + (pwm->hwpwm << 2));
57
+ writel(val, lpc32xx->base);
5858
5959 return 0;
6060 }
....@@ -69,9 +69,9 @@
6969 if (ret)
7070 return ret;
7171
72
- val = readl(lpc32xx->base + (pwm->hwpwm << 2));
72
+ val = readl(lpc32xx->base);
7373 val |= PWM_ENABLE;
74
- writel(val, lpc32xx->base + (pwm->hwpwm << 2));
74
+ writel(val, lpc32xx->base);
7575
7676 return 0;
7777 }
....@@ -81,9 +81,9 @@
8181 struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
8282 u32 val;
8383
84
- val = readl(lpc32xx->base + (pwm->hwpwm << 2));
84
+ val = readl(lpc32xx->base);
8585 val &= ~PWM_ENABLE;
86
- writel(val, lpc32xx->base + (pwm->hwpwm << 2));
86
+ writel(val, lpc32xx->base);
8787
8888 clk_disable_unprepare(lpc32xx->clk);
8989 }
....@@ -121,9 +121,9 @@
121121 lpc32xx->chip.base = -1;
122122
123123 /* If PWM is disabled, configure the output to the default value */
124
- val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
124
+ val = readl(lpc32xx->base);
125125 val &= ~PWM_PIN_LEVEL;
126
- writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2));
126
+ writel(val, lpc32xx->base);
127127
128128 ret = pwmchip_add(&lpc32xx->chip);
129129 if (ret < 0) {