~hc/RK356X_SDK_RELEASE.git

..	..	@@ -79,6 +79,10 @@
79	79	#define IRQ_LEVEL_LOW 0x03
80	80	#define IRQ_EDGE_BOTH 0x04
81	81
	82	+#define GRP_CFG_REG 0x300
	83	+
	84	+#define IO_BIAS_MASK GENMASK(3, 0)
	85	+
82	86	#define SUN4I_FUNC_INPUT 0
83	87	#define SUN4I_FUNC_IRQ 6
84	88
..	..	@@ -90,6 +94,24 @@
90	94	#define PINCTRL_SUN4I_A10 BIT(6)
91	95	#define PINCTRL_SUN7I_A20 BIT(7)
92	96	#define PINCTRL_SUN8I_R40 BIT(8)
	97	+#define PINCTRL_SUN8I_V3 BIT(9)
	98	+#define PINCTRL_SUN8I_V3S BIT(10)
	99	+
	100	+#define PIO_POW_MOD_SEL_REG 0x340
	101	+
	102	+enum sunxi_desc_bias_voltage {
	103	+ BIAS_VOLTAGE_NONE,
	104	+ /*
	105	+ * Bias voltage configuration is done through
	106	+ * Pn_GRP_CONFIG registers, as seen on A80 SoC.
	107	+ */
	108	+ BIAS_VOLTAGE_GRP_CONFIG,
	109	+ /*
	110	+ * Bias voltage is set through PIO_POW_MOD_SEL_REG
	111	+ * register, as seen on H6 SoC, for example.
	112	+ */
	113	+ BIAS_VOLTAGE_PIO_POW_MODE_SEL,
	114	+};
93	115
94	116	struct sunxi_desc_function {
95	117	unsigned long variant;
..	..	@@ -113,6 +135,7 @@
113	135	const unsigned int *irq_bank_map;
114	136	bool irq_read_needs_mux;
115	137	bool disable_strict_mode;
	138	+ enum sunxi_desc_bias_voltage io_bias_cfg_variant;
116	139	};
117	140
118	141	struct sunxi_pinctrl_function {
..	..	@@ -126,11 +149,17 @@
126	149	unsigned pin;
127	150	};
128	151
	152	+struct sunxi_pinctrl_regulator {
	153	+ struct regulator *regulator;
	154	+ refcount_t refcount;
	155	+};
	156	+
129	157	struct sunxi_pinctrl {
130	158	void __iomem *membase;
131	159	struct gpio_chip *chip;
132	160	const struct sunxi_pinctrl_desc *desc;
133	161	struct device *dev;
	162	+ struct sunxi_pinctrl_regulator regulators[9];
134	163	struct irq_domain *domain;
135	164	struct sunxi_pinctrl_function *functions;
136	165	unsigned nfunctions;
..	..	@@ -332,6 +361,13 @@
332	361	return irq_num * IRQ_STATUS_IRQ_BITS;
333	362	}
334	363
	364	+static inline u32 sunxi_grp_config_reg(u16 pin)
	365	+{
	366	+ u8 bank = pin / PINS_PER_BANK;
	367	+
	368	+ return GRP_CFG_REG + bank * 0x4;
	369	+}
	370	+
335	371	int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
336	372	const struct sunxi_pinctrl_desc *desc,
337	373	unsigned long variant);