forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da
kernel/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
....@@ -45,13 +45,14 @@
4545 * The pins of a pinmux groups are composed of one or two groups of contiguous
4646 * pins.
4747 * @name: Name of the pin group, used to lookup the group.
48
- * @start_pins: Index of the first pin of the main range of pins belonging to
48
+ * @start_pin: Index of the first pin of the main range of pins belonging to
4949 * the group
5050 * @npins: Number of pins included in the first range
5151 * @reg_mask: Bit mask matching the group in the selection register
52
- * @extra_pins: Index of the first pin of the optional second range of pins
52
+ * @val: Value to write to the registers for a given function
53
+ * @extra_pin: Index of the first pin of the optional second range of pins
5354 * belonging to the group
54
- * @npins: Number of pins included in the second optional range
55
+ * @extra_npins:Number of pins included in the second optional range
5556 * @funcs: A list of pinmux functions that can be selected for this group.
5657 * @pins: List of the pins included in the group
5758 */
....@@ -195,7 +196,7 @@
195196 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
196197 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
197198 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
198
- PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
199
+ PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
199200 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
200201 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
201202 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
....@@ -402,7 +403,10 @@
402403 mask = BIT(offset);
403404 regmap_read(info->regmap, reg, &val);
404405
405
- return !(val & mask);
406
+ if (val & mask)
407
+ return GPIO_LINE_DIRECTION_OUT;
408
+
409
+ return GPIO_LINE_DIRECTION_IN;
406410 }
407411
408412 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
....@@ -721,6 +725,8 @@
721725 struct device_node *np = info->dev->of_node;
722726 struct gpio_chip *gc = &info->gpio_chip;
723727 struct irq_chip *irqchip = &info->irq_chip;
728
+ struct gpio_irq_chip *girq = &gc->irq;
729
+ struct device *dev = &pdev->dev;
724730 struct resource res;
725731 int ret = -ENODEV, i, nr_irq_parent;
726732
....@@ -730,20 +736,22 @@
730736 ret = 0;
731737 break;
732738 }
733
- };
734
- if (ret)
739
+ }
740
+ if (ret) {
741
+ dev_err(dev, "no gpio-controller child node\n");
735742 return ret;
743
+ }
736744
737745 nr_irq_parent = of_irq_count(np);
738746 spin_lock_init(&info->irq_lock);
739747
740748 if (!nr_irq_parent) {
741
- dev_err(&pdev->dev, "Invalid or no IRQ\n");
749
+ dev_err(dev, "invalid or no IRQ\n");
742750 return 0;
743751 }
744752
745753 if (of_address_to_resource(info->dev->of_node, 1, &res)) {
746
- dev_err(info->dev, "cannot find IO resource\n");
754
+ dev_err(dev, "cannot find IO resource\n");
747755 return -ENOENT;
748756 }
749757
....@@ -758,27 +766,27 @@
758766 irqchip->irq_set_type = armada_37xx_irq_set_type;
759767 irqchip->irq_startup = armada_37xx_irq_startup;
760768 irqchip->name = info->data->name;
761
- ret = gpiochip_irqchip_add(gc, irqchip, 0,
762
- handle_edge_irq, IRQ_TYPE_NONE);
763
- if (ret) {
764
- dev_info(&pdev->dev, "could not add irqchip\n");
765
- return ret;
766
- }
767
-
769
+ girq->chip = irqchip;
770
+ girq->parent_handler = armada_37xx_irq_handler;
768771 /*
769772 * Many interrupts are connected to the parent interrupt
770773 * controller. But we do not take advantage of this and use
771774 * the chained irq with all of them.
772775 */
776
+ girq->num_parents = nr_irq_parent;
777
+ girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent,
778
+ sizeof(*girq->parents), GFP_KERNEL);
779
+ if (!girq->parents)
780
+ return -ENOMEM;
773781 for (i = 0; i < nr_irq_parent; i++) {
774782 int irq = irq_of_parse_and_map(np, i);
775783
776
- if (irq < 0)
784
+ if (!irq)
777785 continue;
778
-
779
- gpiochip_set_chained_irqchip(gc, irqchip, irq,
780
- armada_37xx_irq_handler);
786
+ girq->parents[i] = irq;
781787 }
788
+ girq->default_type = IRQ_TYPE_NONE;
789
+ girq->handler = handle_edge_irq;
782790
783791 return 0;
784792 }
....@@ -795,7 +803,7 @@
795803 ret = 0;
796804 break;
797805 }
798
- };
806
+ }
799807 if (ret)
800808 return ret;
801809
....@@ -808,10 +816,10 @@
808816 gc->of_node = np;
809817 gc->label = info->data->name;
810818
811
- ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
819
+ ret = armada_37xx_irqchip_register(pdev, info);
812820 if (ret)
813821 return ret;
814
- ret = armada_37xx_irqchip_register(pdev, info);
822
+ ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
815823 if (ret)
816824 return ret;
817825
....@@ -1106,8 +1114,8 @@
11061114 * to other IO drivers.
11071115 */
11081116 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
1109
- .suspend_late = armada_3700_pinctrl_suspend,
1110
- .resume_early = armada_3700_pinctrl_resume,
1117
+ .suspend_noirq = armada_3700_pinctrl_suspend,
1118
+ .resume_noirq = armada_3700_pinctrl_resume,
11111119 };
11121120
11131121 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)