.. | .. |
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45 | 45 | * The pins of a pinmux groups are composed of one or two groups of contiguous |
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46 | 46 | * pins. |
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47 | 47 | * @name: Name of the pin group, used to lookup the group. |
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48 | | - * @start_pins: Index of the first pin of the main range of pins belonging to |
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| 48 | + * @start_pin: Index of the first pin of the main range of pins belonging to |
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49 | 49 | * the group |
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50 | 50 | * @npins: Number of pins included in the first range |
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51 | 51 | * @reg_mask: Bit mask matching the group in the selection register |
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52 | | - * @extra_pins: Index of the first pin of the optional second range of pins |
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| 52 | + * @val: Value to write to the registers for a given function |
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| 53 | + * @extra_pin: Index of the first pin of the optional second range of pins |
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53 | 54 | * belonging to the group |
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54 | | - * @npins: Number of pins included in the second optional range |
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| 55 | + * @extra_npins:Number of pins included in the second optional range |
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55 | 56 | * @funcs: A list of pinmux functions that can be selected for this group. |
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56 | 57 | * @pins: List of the pins included in the group |
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57 | 58 | */ |
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.. | .. |
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195 | 196 | PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), |
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196 | 197 | PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"), |
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197 | 198 | PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), |
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198 | | - PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), |
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| 199 | + PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ |
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199 | 200 | PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), |
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200 | 201 | PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), |
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201 | 202 | PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), |
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.. | .. |
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402 | 403 | mask = BIT(offset); |
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403 | 404 | regmap_read(info->regmap, reg, &val); |
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404 | 405 | |
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405 | | - return !(val & mask); |
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| 406 | + if (val & mask) |
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| 407 | + return GPIO_LINE_DIRECTION_OUT; |
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| 408 | + |
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| 409 | + return GPIO_LINE_DIRECTION_IN; |
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406 | 410 | } |
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407 | 411 | |
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408 | 412 | static int armada_37xx_gpio_direction_output(struct gpio_chip *chip, |
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.. | .. |
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721 | 725 | struct device_node *np = info->dev->of_node; |
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722 | 726 | struct gpio_chip *gc = &info->gpio_chip; |
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723 | 727 | struct irq_chip *irqchip = &info->irq_chip; |
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| 728 | + struct gpio_irq_chip *girq = &gc->irq; |
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| 729 | + struct device *dev = &pdev->dev; |
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724 | 730 | struct resource res; |
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725 | 731 | int ret = -ENODEV, i, nr_irq_parent; |
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726 | 732 | |
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.. | .. |
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730 | 736 | ret = 0; |
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731 | 737 | break; |
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732 | 738 | } |
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733 | | - }; |
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734 | | - if (ret) |
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| 739 | + } |
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| 740 | + if (ret) { |
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| 741 | + dev_err(dev, "no gpio-controller child node\n"); |
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735 | 742 | return ret; |
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| 743 | + } |
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736 | 744 | |
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737 | 745 | nr_irq_parent = of_irq_count(np); |
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738 | 746 | spin_lock_init(&info->irq_lock); |
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739 | 747 | |
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740 | 748 | if (!nr_irq_parent) { |
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741 | | - dev_err(&pdev->dev, "Invalid or no IRQ\n"); |
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| 749 | + dev_err(dev, "invalid or no IRQ\n"); |
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742 | 750 | return 0; |
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743 | 751 | } |
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744 | 752 | |
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745 | 753 | if (of_address_to_resource(info->dev->of_node, 1, &res)) { |
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746 | | - dev_err(info->dev, "cannot find IO resource\n"); |
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| 754 | + dev_err(dev, "cannot find IO resource\n"); |
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747 | 755 | return -ENOENT; |
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748 | 756 | } |
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749 | 757 | |
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.. | .. |
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758 | 766 | irqchip->irq_set_type = armada_37xx_irq_set_type; |
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759 | 767 | irqchip->irq_startup = armada_37xx_irq_startup; |
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760 | 768 | irqchip->name = info->data->name; |
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761 | | - ret = gpiochip_irqchip_add(gc, irqchip, 0, |
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762 | | - handle_edge_irq, IRQ_TYPE_NONE); |
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763 | | - if (ret) { |
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764 | | - dev_info(&pdev->dev, "could not add irqchip\n"); |
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765 | | - return ret; |
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766 | | - } |
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767 | | - |
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| 769 | + girq->chip = irqchip; |
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| 770 | + girq->parent_handler = armada_37xx_irq_handler; |
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768 | 771 | /* |
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769 | 772 | * Many interrupts are connected to the parent interrupt |
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770 | 773 | * controller. But we do not take advantage of this and use |
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771 | 774 | * the chained irq with all of them. |
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772 | 775 | */ |
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| 776 | + girq->num_parents = nr_irq_parent; |
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| 777 | + girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent, |
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| 778 | + sizeof(*girq->parents), GFP_KERNEL); |
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| 779 | + if (!girq->parents) |
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| 780 | + return -ENOMEM; |
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773 | 781 | for (i = 0; i < nr_irq_parent; i++) { |
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774 | 782 | int irq = irq_of_parse_and_map(np, i); |
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775 | 783 | |
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776 | | - if (irq < 0) |
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| 784 | + if (!irq) |
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777 | 785 | continue; |
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778 | | - |
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779 | | - gpiochip_set_chained_irqchip(gc, irqchip, irq, |
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780 | | - armada_37xx_irq_handler); |
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| 786 | + girq->parents[i] = irq; |
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781 | 787 | } |
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| 788 | + girq->default_type = IRQ_TYPE_NONE; |
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| 789 | + girq->handler = handle_edge_irq; |
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782 | 790 | |
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783 | 791 | return 0; |
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784 | 792 | } |
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.. | .. |
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795 | 803 | ret = 0; |
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796 | 804 | break; |
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797 | 805 | } |
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798 | | - }; |
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| 806 | + } |
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799 | 807 | if (ret) |
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800 | 808 | return ret; |
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801 | 809 | |
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.. | .. |
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808 | 816 | gc->of_node = np; |
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809 | 817 | gc->label = info->data->name; |
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810 | 818 | |
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811 | | - ret = devm_gpiochip_add_data(&pdev->dev, gc, info); |
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| 819 | + ret = armada_37xx_irqchip_register(pdev, info); |
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812 | 820 | if (ret) |
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813 | 821 | return ret; |
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814 | | - ret = armada_37xx_irqchip_register(pdev, info); |
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| 822 | + ret = devm_gpiochip_add_data(&pdev->dev, gc, info); |
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815 | 823 | if (ret) |
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816 | 824 | return ret; |
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817 | 825 | |
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.. | .. |
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1106 | 1114 | * to other IO drivers. |
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1107 | 1115 | */ |
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1108 | 1116 | static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = { |
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1109 | | - .suspend_late = armada_3700_pinctrl_suspend, |
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1110 | | - .resume_early = armada_3700_pinctrl_resume, |
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| 1117 | + .suspend_noirq = armada_3700_pinctrl_suspend, |
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| 1118 | + .resume_noirq = armada_3700_pinctrl_resume, |
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1111 | 1119 | }; |
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1112 | 1120 | |
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1113 | 1121 | #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops) |
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