~hc/RK356X_SDK_RELEASE.git

..	..	@@ -25,6 +25,15 @@
25	25	module_param(max_devices, int, 0644);
26	26	MODULE_PARM_DESC(max_devices, "max number of switchtec device instances");
27	27
	28	+static bool use_dma_mrpc = true;
	29	+module_param(use_dma_mrpc, bool, 0644);
	30	+MODULE_PARM_DESC(use_dma_mrpc,
	31	+ "Enable the use of the DMA MRPC feature");
	32	+
	33	+static int nirqs = 32;
	34	+module_param(nirqs, int, 0644);
	35	+MODULE_PARM_DESC(nirqs, "number of interrupts to allocate (more may be useful for NTB applications)");
	36	+
28	37	static dev_t switchtec_devt;
29	38	static DEFINE_IDA(switchtec_minor_ida);
30	39
..	..	@@ -43,10 +52,11 @@
43	52
44	53	enum mrpc_state state;
45	54
46		- struct completion comp;
	55	+ wait_queue_head_t cmd_comp;
47	56	struct kref kref;
48	57	struct list_head list;
49	58
	59	+ bool cmd_done;
50	60	u32 cmd;
51	61	u32 status;
52	62	u32 return_code;
..	..	@@ -68,7 +78,7 @@
68	78	stuser->stdev = stdev;
69	79	kref_init(&stuser->kref);
70	80	INIT_LIST_HEAD(&stuser->list);
71		- init_completion(&stuser->comp);
	81	+ init_waitqueue_head(&stuser->cmd_comp);
72	82	stuser->event_cnt = atomic_read(&stdev->event_cnt);
73	83
74	84	dev_dbg(&stdev->dev, "%s: %p\n", __func__, stuser);
..	..	@@ -113,6 +123,19 @@
113	123
114	124	static void mrpc_complete_cmd(struct switchtec_dev *stdev);
115	125
	126	+static void flush_wc_buf(struct switchtec_dev *stdev)
	127	+{
	128	+ struct ntb_dbmsg_regs __iomem *mmio_dbmsg;
	129	+
	130	+ /*
	131	+ * odb (outbound doorbell) register is processed by low latency
	132	+ * hardware and w/o side effect
	133	+ */
	134	+ mmio_dbmsg = (void __iomem *)stdev->mmio_ntb +
	135	+ SWITCHTEC_NTB_REG_DBMSG_OFFSET;
	136	+ ioread32(&mmio_dbmsg->odb);
	137	+}
	138	+
116	139	static void mrpc_cmd_submit(struct switchtec_dev *stdev)
117	140	{
118	141	/* requires the mrpc_mutex to already be held when called */
..	..	@@ -128,10 +151,16 @@
128	151	stuser = list_entry(stdev->mrpc_queue.next, struct switchtec_user,
129	152	list);
130	153
	154	+ if (stdev->dma_mrpc) {
	155	+ stdev->dma_mrpc->status = SWITCHTEC_MRPC_STATUS_INPROGRESS;
	156	+ memset(stdev->dma_mrpc->data, 0xFF, SWITCHTEC_MRPC_PAYLOAD_SIZE);
	157	+ }
	158	+
131	159	stuser_set_state(stuser, MRPC_RUNNING);
132	160	stdev->mrpc_busy = 1;
133	161	memcpy_toio(&stdev->mmio_mrpc->input_data,
134	162	stuser->data, stuser->data_len);
	163	+ flush_wc_buf(stdev);
135	164	iowrite32(stuser->cmd, &stdev->mmio_mrpc->cmd);
136	165
137	166	schedule_delayed_work(&stdev->mrpc_timeout,
..	..	@@ -147,7 +176,7 @@
147	176	kref_get(&stuser->kref);
148	177	stuser->read_len = sizeof(stuser->data);
149	178	stuser_set_state(stuser, MRPC_QUEUED);
150		- reinit_completion(&stuser->comp);
	179	+ stuser->cmd_done = false;
151	180	list_add_tail(&stuser->list, &stdev->mrpc_queue);
152	181
153	182	mrpc_cmd_submit(stdev);
..	..	@@ -166,7 +195,11 @@
166	195	stuser = list_entry(stdev->mrpc_queue.next, struct switchtec_user,
167	196	list);
168	197
169		- stuser->status = ioread32(&stdev->mmio_mrpc->status);
	198	+ if (stdev->dma_mrpc)
	199	+ stuser->status = stdev->dma_mrpc->status;
	200	+ else
	201	+ stuser->status = ioread32(&stdev->mmio_mrpc->status);
	202	+
170	203	if (stuser->status == SWITCHTEC_MRPC_STATUS_INPROGRESS)
171	204	return;
172	205
..	..	@@ -176,15 +209,22 @@
176	209	if (stuser->status != SWITCHTEC_MRPC_STATUS_DONE)
177	210	goto out;
178	211
179		- stuser->return_code = ioread32(&stdev->mmio_mrpc->ret_value);
	212	+ if (stdev->dma_mrpc)
	213	+ stuser->return_code = stdev->dma_mrpc->rtn_code;
	214	+ else
	215	+ stuser->return_code = ioread32(&stdev->mmio_mrpc->ret_value);
180	216	if (stuser->return_code != 0)
181	217	goto out;
182	218
183		- memcpy_fromio(stuser->data, &stdev->mmio_mrpc->output_data,
184		- stuser->read_len);
185		-
	219	+ if (stdev->dma_mrpc)
	220	+ memcpy(stuser->data, &stdev->dma_mrpc->data,
	221	+ stuser->read_len);
	222	+ else
	223	+ memcpy_fromio(stuser->data, &stdev->mmio_mrpc->output_data,
	224	+ stuser->read_len);
186	225	out:
187		- complete_all(&stuser->comp);
	226	+ stuser->cmd_done = true;
	227	+ wake_up_interruptible(&stuser->cmd_comp);
188	228	list_del_init(&stuser->list);
189	229	stuser_put(stuser);
190	230	stdev->mrpc_busy = 0;
..	..	@@ -217,7 +257,10 @@
217	257
218	258	mutex_lock(&stdev->mrpc_mutex);
219	259
220		- status = ioread32(&stdev->mmio_mrpc->status);
	260	+ if (stdev->dma_mrpc)
	261	+ status = stdev->dma_mrpc->status;
	262	+ else
	263	+ status = ioread32(&stdev->mmio_mrpc->status);
221	264	if (status == SWITCHTEC_MRPC_STATUS_INPROGRESS) {
222	265	schedule_delayed_work(&stdev->mrpc_timeout,
223	266	msecs_to_jiffies(500));
..	..	@@ -225,7 +268,6 @@
225	268	}
226	269
227	270	mrpc_complete_cmd(stdev);
228		-
229	271	out:
230	272	mutex_unlock(&stdev->mrpc_mutex);
231	273	}
..	..	@@ -277,8 +319,15 @@
277	319	struct device_attribute attr, char buf) \
278	320	{ \
279	321	struct switchtec_dev *stdev = to_stdev(dev); \
280		- return io_string_show(buf, &stdev->mmio_sys_info->field, \
281		- sizeof(stdev->mmio_sys_info->field)); \
	322	+ struct sys_info_regs __iomem *si = stdev->mmio_sys_info; \
	323	+ if (stdev->gen == SWITCHTEC_GEN3) \
	324	+ return io_string_show(buf, &si->gen3.field, \
	325	+ sizeof(si->gen3.field)); \
	326	+ else if (stdev->gen == SWITCHTEC_GEN4) \
	327	+ return io_string_show(buf, &si->gen4.field, \
	328	+ sizeof(si->gen4.field)); \
	329	+ else \
	330	+ return -ENOTSUPP; \
282	331	} \
283	332	\
284	333	static DEVICE_ATTR_RO(field)
..	..	@@ -286,13 +335,31 @@
286	335	DEVICE_ATTR_SYS_INFO_STR(vendor_id);
287	336	DEVICE_ATTR_SYS_INFO_STR(product_id);
288	337	DEVICE_ATTR_SYS_INFO_STR(product_revision);
289		-DEVICE_ATTR_SYS_INFO_STR(component_vendor);
	338	+
	339	+static ssize_t component_vendor_show(struct device *dev,
	340	+ struct device_attribute attr, char buf)
	341	+{
	342	+ struct switchtec_dev *stdev = to_stdev(dev);
	343	+ struct sys_info_regs __iomem *si = stdev->mmio_sys_info;
	344	+
	345	+ /* component_vendor field not supported after gen3 */
	346	+ if (stdev->gen != SWITCHTEC_GEN3)
	347	+ return sprintf(buf, "none\n");
	348	+
	349	+ return io_string_show(buf, &si->gen3.component_vendor,
	350	+ sizeof(si->gen3.component_vendor));
	351	+}
	352	+static DEVICE_ATTR_RO(component_vendor);
290	353
291	354	static ssize_t component_id_show(struct device *dev,
292	355	struct device_attribute attr, char buf)
293	356	{
294	357	struct switchtec_dev *stdev = to_stdev(dev);
295		- int id = ioread16(&stdev->mmio_sys_info->component_id);
	358	+ int id = ioread16(&stdev->mmio_sys_info->gen3.component_id);
	359	+
	360	+ /* component_id field not supported after gen3 */
	361	+ if (stdev->gen != SWITCHTEC_GEN3)
	362	+ return sprintf(buf, "none\n");
296	363
297	364	return sprintf(buf, "PM%04X\n", id);
298	365	}
..	..	@@ -302,7 +369,11 @@
302	369	struct device_attribute attr, char buf)
303	370	{
304	371	struct switchtec_dev *stdev = to_stdev(dev);
305		- int rev = ioread8(&stdev->mmio_sys_info->component_revision);
	372	+ int rev = ioread8(&stdev->mmio_sys_info->gen3.component_revision);
	373	+
	374	+ /* component_revision field not supported after gen3 */
	375	+ if (stdev->gen != SWITCHTEC_GEN3)
	376	+ return sprintf(buf, "255\n");
306	377
307	378	return sprintf(buf, "%d\n", rev);
308	379	}
..	..	@@ -354,7 +425,7 @@
354	425	return PTR_ERR(stuser);
355	426
356	427	filp->private_data = stuser;
357		- nonseekable_open(inode, filp);
	428	+ stream_open(inode, filp);
358	429
359	430	dev_dbg(&stdev->dev, "%s: %p\n", __func__, stuser);
360	431
..	..	@@ -410,6 +481,12 @@
410	481	rc = -EFAULT;
411	482	goto out;
412	483	}
	484	+ if (((MRPC_CMD_ID(stuser->cmd) == MRPC_GAS_WRITE) \|\|
	485	+ (MRPC_CMD_ID(stuser->cmd) == MRPC_GAS_READ)) &&
	486	+ !capable(CAP_SYS_ADMIN)) {
	487	+ rc = -EPERM;
	488	+ goto out;
	489	+ }
413	490
414	491	data += sizeof(stuser->cmd);
415	492	rc = copy_from_user(&stuser->data, data, size - sizeof(stuser->cmd));
..	..	@@ -454,10 +531,11 @@
454	531	mutex_unlock(&stdev->mrpc_mutex);
455	532
456	533	if (filp->f_flags & O_NONBLOCK) {
457		- if (!try_wait_for_completion(&stuser->comp))
	534	+ if (!stuser->cmd_done)
458	535	return -EAGAIN;
459	536	} else {
460		- rc = wait_for_completion_interruptible(&stuser->comp);
	537	+ rc = wait_event_interruptible(stuser->cmd_comp,
	538	+ stuser->cmd_done);
461	539	if (rc < 0)
462	540	return rc;
463	541	}
..	..	@@ -505,7 +583,7 @@
505	583	struct switchtec_dev *stdev = stuser->stdev;
506	584	__poll_t ret = 0;
507	585
508		- poll_wait(filp, &stuser->comp.wait, wait);
	586	+ poll_wait(filp, &stuser->cmd_comp, wait);
509	587	poll_wait(filp, &stdev->event_wq, wait);
510	588
511	589	if (lock_mutex_and_test_alive(stdev))
..	..	@@ -513,7 +591,7 @@
513	591
514	592	mutex_unlock(&stdev->mrpc_mutex);
515	593
516		- if (try_wait_for_completion(&stuser->comp))
	594	+ if (stuser->cmd_done)
517	595	ret \|= EPOLLIN \| EPOLLRDNORM;
518	596
519	597	if (stuser->event_cnt != atomic_read(&stdev->event_cnt))
..	..	@@ -528,8 +606,15 @@
528	606	struct switchtec_ioctl_flash_info info = {0};
529	607	struct flash_info_regs __iomem *fi = stdev->mmio_flash_info;
530	608
531		- info.flash_length = ioread32(&fi->flash_length);
532		- info.num_partitions = SWITCHTEC_IOCTL_NUM_PARTITIONS;
	609	+ if (stdev->gen == SWITCHTEC_GEN3) {
	610	+ info.flash_length = ioread32(&fi->gen3.flash_length);
	611	+ info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN3;
	612	+ } else if (stdev->gen == SWITCHTEC_GEN4) {
	613	+ info.flash_length = ioread32(&fi->gen4.flash_length);
	614	+ info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN4;
	615	+ } else {
	616	+ return -ENOTSUPP;
	617	+ }
533	618
534	619	if (copy_to_user(uinfo, &info, sizeof(info)))
535	620	return -EFAULT;
..	..	@@ -544,75 +629,200 @@
544	629	info->length = ioread32(&pi->length);
545	630	}
546	631
547		-static int ioctl_flash_part_info(struct switchtec_dev *stdev,
548		- struct switchtec_ioctl_flash_part_info __user *uinfo)
	632	+static int flash_part_info_gen3(struct switchtec_dev *stdev,
	633	+ struct switchtec_ioctl_flash_part_info *info)
549	634	{
550		- struct switchtec_ioctl_flash_part_info info = {0};
551		- struct flash_info_regs __iomem *fi = stdev->mmio_flash_info;
552		- struct sys_info_regs __iomem *si = stdev->mmio_sys_info;
	635	+ struct flash_info_regs_gen3 __iomem *fi =
	636	+ &stdev->mmio_flash_info->gen3;
	637	+ struct sys_info_regs_gen3 __iomem *si = &stdev->mmio_sys_info->gen3;
553	638	u32 active_addr = -1;
554	639
555		- if (copy_from_user(&info, uinfo, sizeof(info)))
556		- return -EFAULT;
557		-
558		- switch (info.flash_partition) {
	640	+ switch (info->flash_partition) {
559	641	case SWITCHTEC_IOCTL_PART_CFG0:
560	642	active_addr = ioread32(&fi->active_cfg);
561		- set_fw_info_part(&info, &fi->cfg0);
562		- if (ioread16(&si->cfg_running) == SWITCHTEC_CFG0_RUNNING)
563		- info.active \|= SWITCHTEC_IOCTL_PART_RUNNING;
	643	+ set_fw_info_part(info, &fi->cfg0);
	644	+ if (ioread16(&si->cfg_running) == SWITCHTEC_GEN3_CFG0_RUNNING)
	645	+ info->active \|= SWITCHTEC_IOCTL_PART_RUNNING;
564	646	break;
565	647	case SWITCHTEC_IOCTL_PART_CFG1:
566	648	active_addr = ioread32(&fi->active_cfg);
567		- set_fw_info_part(&info, &fi->cfg1);
568		- if (ioread16(&si->cfg_running) == SWITCHTEC_CFG1_RUNNING)
569		- info.active \|= SWITCHTEC_IOCTL_PART_RUNNING;
	649	+ set_fw_info_part(info, &fi->cfg1);
	650	+ if (ioread16(&si->cfg_running) == SWITCHTEC_GEN3_CFG1_RUNNING)
	651	+ info->active \|= SWITCHTEC_IOCTL_PART_RUNNING;
570	652	break;
571	653	case SWITCHTEC_IOCTL_PART_IMG0:
572	654	active_addr = ioread32(&fi->active_img);
573		- set_fw_info_part(&info, &fi->img0);
574		- if (ioread16(&si->img_running) == SWITCHTEC_IMG0_RUNNING)
575		- info.active \|= SWITCHTEC_IOCTL_PART_RUNNING;
	655	+ set_fw_info_part(info, &fi->img0);
	656	+ if (ioread16(&si->img_running) == SWITCHTEC_GEN3_IMG0_RUNNING)
	657	+ info->active \|= SWITCHTEC_IOCTL_PART_RUNNING;
576	658	break;
577	659	case SWITCHTEC_IOCTL_PART_IMG1:
578	660	active_addr = ioread32(&fi->active_img);
579		- set_fw_info_part(&info, &fi->img1);
580		- if (ioread16(&si->img_running) == SWITCHTEC_IMG1_RUNNING)
581		- info.active \|= SWITCHTEC_IOCTL_PART_RUNNING;
	661	+ set_fw_info_part(info, &fi->img1);
	662	+ if (ioread16(&si->img_running) == SWITCHTEC_GEN3_IMG1_RUNNING)
	663	+ info->active \|= SWITCHTEC_IOCTL_PART_RUNNING;
582	664	break;
583	665	case SWITCHTEC_IOCTL_PART_NVLOG:
584		- set_fw_info_part(&info, &fi->nvlog);
	666	+ set_fw_info_part(info, &fi->nvlog);
585	667	break;
586	668	case SWITCHTEC_IOCTL_PART_VENDOR0:
587		- set_fw_info_part(&info, &fi->vendor[0]);
	669	+ set_fw_info_part(info, &fi->vendor[0]);
588	670	break;
589	671	case SWITCHTEC_IOCTL_PART_VENDOR1:
590		- set_fw_info_part(&info, &fi->vendor[1]);
	672	+ set_fw_info_part(info, &fi->vendor[1]);
591	673	break;
592	674	case SWITCHTEC_IOCTL_PART_VENDOR2:
593		- set_fw_info_part(&info, &fi->vendor[2]);
	675	+ set_fw_info_part(info, &fi->vendor[2]);
594	676	break;
595	677	case SWITCHTEC_IOCTL_PART_VENDOR3:
596		- set_fw_info_part(&info, &fi->vendor[3]);
	678	+ set_fw_info_part(info, &fi->vendor[3]);
597	679	break;
598	680	case SWITCHTEC_IOCTL_PART_VENDOR4:
599		- set_fw_info_part(&info, &fi->vendor[4]);
	681	+ set_fw_info_part(info, &fi->vendor[4]);
600	682	break;
601	683	case SWITCHTEC_IOCTL_PART_VENDOR5:
602		- set_fw_info_part(&info, &fi->vendor[5]);
	684	+ set_fw_info_part(info, &fi->vendor[5]);
603	685	break;
604	686	case SWITCHTEC_IOCTL_PART_VENDOR6:
605		- set_fw_info_part(&info, &fi->vendor[6]);
	687	+ set_fw_info_part(info, &fi->vendor[6]);
606	688	break;
607	689	case SWITCHTEC_IOCTL_PART_VENDOR7:
608		- set_fw_info_part(&info, &fi->vendor[7]);
	690	+ set_fw_info_part(info, &fi->vendor[7]);
609	691	break;
610	692	default:
611	693	return -EINVAL;
612	694	}
613	695
614		- if (info.address == active_addr)
615		- info.active \|= SWITCHTEC_IOCTL_PART_ACTIVE;
	696	+ if (info->address == active_addr)
	697	+ info->active \|= SWITCHTEC_IOCTL_PART_ACTIVE;
	698	+
	699	+ return 0;
	700	+}
	701	+
	702	+static int flash_part_info_gen4(struct switchtec_dev *stdev,
	703	+ struct switchtec_ioctl_flash_part_info *info)
	704	+{
	705	+ struct flash_info_regs_gen4 __iomem *fi = &stdev->mmio_flash_info->gen4;
	706	+ struct sys_info_regs_gen4 __iomem *si = &stdev->mmio_sys_info->gen4;
	707	+ struct active_partition_info_gen4 __iomem *af = &fi->active_flag;
	708	+
	709	+ switch (info->flash_partition) {
	710	+ case SWITCHTEC_IOCTL_PART_MAP_0:
	711	+ set_fw_info_part(info, &fi->map0);
	712	+ break;
	713	+ case SWITCHTEC_IOCTL_PART_MAP_1:
	714	+ set_fw_info_part(info, &fi->map1);
	715	+ break;
	716	+ case SWITCHTEC_IOCTL_PART_KEY_0:
	717	+ set_fw_info_part(info, &fi->key0);
	718	+ if (ioread8(&af->key) == SWITCHTEC_GEN4_KEY0_ACTIVE)
	719	+ info->active \|= SWITCHTEC_IOCTL_PART_ACTIVE;
	720	+ if (ioread16(&si->key_running) == SWITCHTEC_GEN4_KEY0_RUNNING)
	721	+ info->active \|= SWITCHTEC_IOCTL_PART_RUNNING;
	722	+ break;
	723	+ case SWITCHTEC_IOCTL_PART_KEY_1:
	724	+ set_fw_info_part(info, &fi->key1);
	725	+ if (ioread8(&af->key) == SWITCHTEC_GEN4_KEY1_ACTIVE)
	726	+ info->active \|= SWITCHTEC_IOCTL_PART_ACTIVE;
	727	+ if (ioread16(&si->key_running) == SWITCHTEC_GEN4_KEY1_RUNNING)
	728	+ info->active \|= SWITCHTEC_IOCTL_PART_RUNNING;
	729	+ break;
	730	+ case SWITCHTEC_IOCTL_PART_BL2_0:
	731	+ set_fw_info_part(info, &fi->bl2_0);
	732	+ if (ioread8(&af->bl2) == SWITCHTEC_GEN4_BL2_0_ACTIVE)
	733	+ info->active \|= SWITCHTEC_IOCTL_PART_ACTIVE;
	734	+ if (ioread16(&si->bl2_running) == SWITCHTEC_GEN4_BL2_0_RUNNING)
	735	+ info->active \|= SWITCHTEC_IOCTL_PART_RUNNING;
	736	+ break;
	737	+ case SWITCHTEC_IOCTL_PART_BL2_1:
	738	+ set_fw_info_part(info, &fi->bl2_1);
	739	+ if (ioread8(&af->bl2) == SWITCHTEC_GEN4_BL2_1_ACTIVE)
	740	+ info->active \|= SWITCHTEC_IOCTL_PART_ACTIVE;
	741	+ if (ioread16(&si->bl2_running) == SWITCHTEC_GEN4_BL2_1_RUNNING)
	742	+ info->active \|= SWITCHTEC_IOCTL_PART_RUNNING;
	743	+ break;
	744	+ case SWITCHTEC_IOCTL_PART_CFG0:
	745	+ set_fw_info_part(info, &fi->cfg0);
	746	+ if (ioread8(&af->cfg) == SWITCHTEC_GEN4_CFG0_ACTIVE)
	747	+ info->active \|= SWITCHTEC_IOCTL_PART_ACTIVE;
	748	+ if (ioread16(&si->cfg_running) == SWITCHTEC_GEN4_CFG0_RUNNING)
	749	+ info->active \|= SWITCHTEC_IOCTL_PART_RUNNING;
	750	+ break;
	751	+ case SWITCHTEC_IOCTL_PART_CFG1:
	752	+ set_fw_info_part(info, &fi->cfg1);
	753	+ if (ioread8(&af->cfg) == SWITCHTEC_GEN4_CFG1_ACTIVE)
	754	+ info->active \|= SWITCHTEC_IOCTL_PART_ACTIVE;
	755	+ if (ioread16(&si->cfg_running) == SWITCHTEC_GEN4_CFG1_RUNNING)
	756	+ info->active \|= SWITCHTEC_IOCTL_PART_RUNNING;
	757	+ break;
	758	+ case SWITCHTEC_IOCTL_PART_IMG0:
	759	+ set_fw_info_part(info, &fi->img0);
	760	+ if (ioread8(&af->img) == SWITCHTEC_GEN4_IMG0_ACTIVE)
	761	+ info->active \|= SWITCHTEC_IOCTL_PART_ACTIVE;
	762	+ if (ioread16(&si->img_running) == SWITCHTEC_GEN4_IMG0_RUNNING)
	763	+ info->active \|= SWITCHTEC_IOCTL_PART_RUNNING;
	764	+ break;
	765	+ case SWITCHTEC_IOCTL_PART_IMG1:
	766	+ set_fw_info_part(info, &fi->img1);
	767	+ if (ioread8(&af->img) == SWITCHTEC_GEN4_IMG1_ACTIVE)
	768	+ info->active \|= SWITCHTEC_IOCTL_PART_ACTIVE;
	769	+ if (ioread16(&si->img_running) == SWITCHTEC_GEN4_IMG1_RUNNING)
	770	+ info->active \|= SWITCHTEC_IOCTL_PART_RUNNING;
	771	+ break;
	772	+ case SWITCHTEC_IOCTL_PART_NVLOG:
	773	+ set_fw_info_part(info, &fi->nvlog);
	774	+ break;
	775	+ case SWITCHTEC_IOCTL_PART_VENDOR0:
	776	+ set_fw_info_part(info, &fi->vendor[0]);
	777	+ break;
	778	+ case SWITCHTEC_IOCTL_PART_VENDOR1:
	779	+ set_fw_info_part(info, &fi->vendor[1]);
	780	+ break;
	781	+ case SWITCHTEC_IOCTL_PART_VENDOR2:
	782	+ set_fw_info_part(info, &fi->vendor[2]);
	783	+ break;
	784	+ case SWITCHTEC_IOCTL_PART_VENDOR3:
	785	+ set_fw_info_part(info, &fi->vendor[3]);
	786	+ break;
	787	+ case SWITCHTEC_IOCTL_PART_VENDOR4:
	788	+ set_fw_info_part(info, &fi->vendor[4]);
	789	+ break;
	790	+ case SWITCHTEC_IOCTL_PART_VENDOR5:
	791	+ set_fw_info_part(info, &fi->vendor[5]);
	792	+ break;
	793	+ case SWITCHTEC_IOCTL_PART_VENDOR6:
	794	+ set_fw_info_part(info, &fi->vendor[6]);
	795	+ break;
	796	+ case SWITCHTEC_IOCTL_PART_VENDOR7:
	797	+ set_fw_info_part(info, &fi->vendor[7]);
	798	+ break;
	799	+ default:
	800	+ return -EINVAL;
	801	+ }
	802	+
	803	+ return 0;
	804	+}
	805	+
	806	+static int ioctl_flash_part_info(struct switchtec_dev *stdev,
	807	+ struct switchtec_ioctl_flash_part_info __user *uinfo)
	808	+{
	809	+ int ret;
	810	+ struct switchtec_ioctl_flash_part_info info = {0};
	811	+
	812	+ if (copy_from_user(&info, uinfo, sizeof(info)))
	813	+ return -EFAULT;
	814	+
	815	+ if (stdev->gen == SWITCHTEC_GEN3) {
	816	+ ret = flash_part_info_gen3(stdev, &info);
	817	+ if (ret)
	818	+ return ret;
	819	+ } else if (stdev->gen == SWITCHTEC_GEN4) {
	820	+ ret = flash_part_info_gen4(stdev, &info);
	821	+ if (ret)
	822	+ return ret;
	823	+ } else {
	824	+ return -ENOTSUPP;
	825	+ }
616	826
617	827	if (copy_to_user(uinfo, &info, sizeof(info)))
618	828	return -EFAULT;
..	..	@@ -622,36 +832,42 @@
622	832
623	833	static int ioctl_event_summary(struct switchtec_dev *stdev,
624	834	struct switchtec_user *stuser,
625		- struct switchtec_ioctl_event_summary __user *usum)
	835	+ struct switchtec_ioctl_event_summary __user *usum,
	836	+ size_t size)
626	837	{
627		- struct switchtec_ioctl_event_summary s = {0};
	838	+ struct switchtec_ioctl_event_summary *s;
628	839	int i;
629	840	u32 reg;
	841	+ int ret = 0;
630	842
631		- s.global = ioread32(&stdev->mmio_sw_event->global_summary);
632		- s.part_bitmap = readq(&stdev->mmio_sw_event->part_event_bitmap);
633		- s.local_part = ioread32(&stdev->mmio_part_cfg->part_event_summary);
	843	+ s = kzalloc(sizeof(*s), GFP_KERNEL);
	844	+ if (!s)
	845	+ return -ENOMEM;
	846	+
	847	+ s->global = ioread32(&stdev->mmio_sw_event->global_summary);
	848	+ s->part_bitmap = ioread64(&stdev->mmio_sw_event->part_event_bitmap);
	849	+ s->local_part = ioread32(&stdev->mmio_part_cfg->part_event_summary);
634	850
635	851	for (i = 0; i < stdev->partition_count; i++) {
636	852	reg = ioread32(&stdev->mmio_part_cfg_all[i].part_event_summary);
637		- s.part[i] = reg;
	853	+ s->part[i] = reg;
638	854	}
639	855
640		- for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) {
641		- reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id);
642		- if (reg != PCI_VENDOR_ID_MICROSEMI)
643		- break;
644		-
	856	+ for (i = 0; i < stdev->pff_csr_count; i++) {
645	857	reg = ioread32(&stdev->mmio_pff_csr[i].pff_event_summary);
646		- s.pff[i] = reg;
	858	+ s->pff[i] = reg;
647	859	}
648	860
649		- if (copy_to_user(usum, &s, sizeof(s)))
650		- return -EFAULT;
	861	+ if (copy_to_user(usum, s, size)) {
	862	+ ret = -EFAULT;
	863	+ goto error_case;
	864	+ }
651	865
652	866	stuser->event_cnt = atomic_read(&stdev->event_cnt);
653	867
654		- return 0;
	868	+error_case:
	869	+ kfree(s);
	870	+ return ret;
655	871	}
656	872
657	873	static u32 __iomem global_ev_reg(struct switchtec_dev stdev,
..	..	@@ -701,10 +917,13 @@
701	917	EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP, mrpc_comp_hdr),
702	918	EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP_ASYNC, mrpc_comp_async_hdr),
703	919	EV_PAR(SWITCHTEC_IOCTL_EVENT_DYN_PART_BIND_COMP, dyn_binding_hdr),
	920	+ EV_PAR(SWITCHTEC_IOCTL_EVENT_INTERCOMM_REQ_NOTIFY,
	921	+ intercomm_notify_hdr),
704	922	EV_PFF(SWITCHTEC_IOCTL_EVENT_AER_IN_P2P, aer_in_p2p_hdr),
705	923	EV_PFF(SWITCHTEC_IOCTL_EVENT_AER_IN_VEP, aer_in_vep_hdr),
706	924	EV_PFF(SWITCHTEC_IOCTL_EVENT_DPC, dpc_hdr),
707	925	EV_PFF(SWITCHTEC_IOCTL_EVENT_CTS, cts_hdr),
	926	+ EV_PFF(SWITCHTEC_IOCTL_EVENT_UEC, uec_hdr),
708	927	EV_PFF(SWITCHTEC_IOCTL_EVENT_HOTPLUG, hotplug_hdr),
709	928	EV_PFF(SWITCHTEC_IOCTL_EVENT_IER, ier_hdr),
710	929	EV_PFF(SWITCHTEC_IOCTL_EVENT_THRESH, threshold_hdr),
..	..	@@ -721,7 +940,7 @@
721	940	size_t off;
722	941
723	942	if (event_id < 0 \|\| event_id >= SWITCHTEC_IOCTL_MAX_EVENTS)
724		- return ERR_PTR(-EINVAL);
	943	+ return (u32 __iomem *)ERR_PTR(-EINVAL);
725	944
726	945	off = event_regs[event_id].offset;
727	946
..	..	@@ -729,10 +948,10 @@
729	948	if (index == SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX)
730	949	index = stdev->partition;
731	950	else if (index < 0 \|\| index >= stdev->partition_count)
732		- return ERR_PTR(-EINVAL);
	951	+ return (u32 __iomem *)ERR_PTR(-EINVAL);
733	952	} else if (event_regs[event_id].map_reg == pff_ev_reg) {
734	953	if (index < 0 \|\| index >= stdev->pff_csr_count)
735		- return ERR_PTR(-EINVAL);
	954	+ return (u32 __iomem *)ERR_PTR(-EINVAL);
736	955	}
737	956
738	957	return event_regs[event_id].map_reg(stdev, off, index);
..	..	@@ -838,11 +1057,11 @@
838	1057	}
839	1058
840	1059	static int ioctl_pff_to_port(struct switchtec_dev *stdev,
841		- struct switchtec_ioctl_pff_port *up)
	1060	+ struct switchtec_ioctl_pff_port __user *up)
842	1061	{
843	1062	int i, part;
844	1063	u32 reg;
845		- struct part_cfg_regs *pcfg;
	1064	+ struct part_cfg_regs __iomem *pcfg;
846	1065	struct switchtec_ioctl_pff_port p;
847	1066
848	1067	if (copy_from_user(&p, up, sizeof(p)))
..	..	@@ -885,10 +1104,10 @@
885	1104	}
886	1105
887	1106	static int ioctl_port_to_pff(struct switchtec_dev *stdev,
888		- struct switchtec_ioctl_pff_port *up)
	1107	+ struct switchtec_ioctl_pff_port __user *up)
889	1108	{
890	1109	struct switchtec_ioctl_pff_port p;
891		- struct part_cfg_regs *pcfg;
	1110	+ struct part_cfg_regs __iomem *pcfg;
892	1111
893	1112	if (copy_from_user(&p, up, sizeof(p)))
894	1113	return -EFAULT;
..	..	@@ -941,8 +1160,9 @@
941	1160	case SWITCHTEC_IOCTL_FLASH_PART_INFO:
942	1161	rc = ioctl_flash_part_info(stdev, argp);
943	1162	break;
944		- case SWITCHTEC_IOCTL_EVENT_SUMMARY:
945		- rc = ioctl_event_summary(stdev, stuser, argp);
	1163	+ case SWITCHTEC_IOCTL_EVENT_SUMMARY_LEGACY:
	1164	+ rc = ioctl_event_summary(stdev, stuser, argp,
	1165	+ sizeof(struct switchtec_ioctl_event_summary_legacy));
946	1166	break;
947	1167	case SWITCHTEC_IOCTL_EVENT_CTL:
948	1168	rc = ioctl_event_ctl(stdev, argp);
..	..	@@ -952,6 +1172,10 @@
952	1172	break;
953	1173	case SWITCHTEC_IOCTL_PORT_TO_PFF:
954	1174	rc = ioctl_port_to_pff(stdev, argp);
	1175	+ break;
	1176	+ case SWITCHTEC_IOCTL_EVENT_SUMMARY:
	1177	+ rc = ioctl_event_summary(stdev, stuser, argp,
	1178	+ sizeof(struct switchtec_ioctl_event_summary));
955	1179	break;
956	1180	default:
957	1181	rc = -ENOTTY;
..	..	@@ -970,7 +1194,7 @@
970	1194	.read = switchtec_dev_read,
971	1195	.poll = switchtec_dev_poll,
972	1196	.unlocked_ioctl = switchtec_dev_ioctl,
973		- .compat_ioctl = switchtec_dev_ioctl,
	1197	+ .compat_ioctl = compat_ptr_ioctl,
974	1198	};
975	1199
976	1200	static void link_event_work(struct work_struct *work)
..	..	@@ -1016,10 +1240,24 @@
1016	1240	}
1017	1241	}
1018	1242
	1243	+static void enable_dma_mrpc(struct switchtec_dev *stdev)
	1244	+{
	1245	+ writeq(stdev->dma_mrpc_dma_addr, &stdev->mmio_mrpc->dma_addr);
	1246	+ flush_wc_buf(stdev);
	1247	+ iowrite32(SWITCHTEC_DMA_MRPC_EN, &stdev->mmio_mrpc->dma_en);
	1248	+}
	1249	+
1019	1250	static void stdev_release(struct device *dev)
1020	1251	{
1021	1252	struct switchtec_dev *stdev = to_stdev(dev);
1022	1253
	1254	+ if (stdev->dma_mrpc) {
	1255	+ iowrite32(0, &stdev->mmio_mrpc->dma_en);
	1256	+ flush_wc_buf(stdev);
	1257	+ writeq(0, &stdev->mmio_mrpc->dma_addr);
	1258	+ dma_free_coherent(&stdev->pdev->dev, sizeof(*stdev->dma_mrpc),
	1259	+ stdev->dma_mrpc, stdev->dma_mrpc_dma_addr);
	1260	+ }
1023	1261	kfree(stdev);
1024	1262	}
1025	1263
..	..	@@ -1037,7 +1275,8 @@
1037	1275
1038	1276	/* Wake up and kill any users waiting on an MRPC request */
1039	1277	list_for_each_entry_safe(stuser, tmpuser, &stdev->mrpc_queue, list) {
1040		- complete_all(&stuser->comp);
	1278	+ stuser->cmd_done = true;
	1279	+ wake_up_interruptible(&stuser->cmd_comp);
1041	1280	list_del_init(&stuser->list);
1042	1281	stuser_put(stuser);
1043	1282	}
..	..	@@ -1112,10 +1351,6 @@
1112	1351	if (!(hdr & SWITCHTEC_EVENT_OCCURRED && hdr & SWITCHTEC_EVENT_EN_IRQ))
1113	1352	return 0;
1114	1353
1115		- if (eid == SWITCHTEC_IOCTL_EVENT_LINK_STATE \|\|
1116		- eid == SWITCHTEC_IOCTL_EVENT_MRPC_COMP)
1117		- return 0;
1118		-
1119	1354	dev_dbg(&stdev->dev, "%s: %d %d %x\n", __func__, eid, idx, hdr);
1120	1355	hdr &= ~(SWITCHTEC_EVENT_EN_IRQ \| SWITCHTEC_EVENT_OCCURRED);
1121	1356	iowrite32(hdr, hdr_reg);
..	..	@@ -1162,8 +1397,13 @@
1162	1397
1163	1398	check_link_state_events(stdev);
1164	1399
1165		- for (eid = 0; eid < SWITCHTEC_IOCTL_MAX_EVENTS; eid++)
	1400	+ for (eid = 0; eid < SWITCHTEC_IOCTL_MAX_EVENTS; eid++) {
	1401	+ if (eid == SWITCHTEC_IOCTL_EVENT_LINK_STATE \|\|
	1402	+ eid == SWITCHTEC_IOCTL_EVENT_MRPC_COMP)
	1403	+ continue;
	1404	+
1166	1405	event_count += mask_all_events(stdev, eid);
	1406	+ }
1167	1407
1168	1408	if (event_count) {
1169	1409	atomic_inc(&stdev->event_cnt);
..	..	@@ -1176,13 +1416,34 @@
1176	1416	return ret;
1177	1417	}
1178	1418
	1419	+
	1420	+static irqreturn_t switchtec_dma_mrpc_isr(int irq, void *dev)
	1421	+{
	1422	+ struct switchtec_dev *stdev = dev;
	1423	+ irqreturn_t ret = IRQ_NONE;
	1424	+
	1425	+ iowrite32(SWITCHTEC_EVENT_CLEAR \|
	1426	+ SWITCHTEC_EVENT_EN_IRQ,
	1427	+ &stdev->mmio_part_cfg->mrpc_comp_hdr);
	1428	+ schedule_work(&stdev->mrpc_work);
	1429	+
	1430	+ ret = IRQ_HANDLED;
	1431	+ return ret;
	1432	+}
	1433	+
1179	1434	static int switchtec_init_isr(struct switchtec_dev *stdev)
1180	1435	{
1181	1436	int nvecs;
1182	1437	int event_irq;
	1438	+ int dma_mrpc_irq;
	1439	+ int rc;
1183	1440
1184		- nvecs = pci_alloc_irq_vectors(stdev->pdev, 1, 4,
1185		- PCI_IRQ_MSIX \| PCI_IRQ_MSI);
	1441	+ if (nirqs < 4)
	1442	+ nirqs = 4;
	1443	+
	1444	+ nvecs = pci_alloc_irq_vectors(stdev->pdev, 1, nirqs,
	1445	+ PCI_IRQ_MSIX \| PCI_IRQ_MSI \|
	1446	+ PCI_IRQ_VIRTUAL);
1186	1447	if (nvecs < 0)
1187	1448	return nvecs;
1188	1449
..	..	@@ -1194,16 +1455,36 @@
1194	1455	if (event_irq < 0)
1195	1456	return event_irq;
1196	1457
1197		- return devm_request_irq(&stdev->pdev->dev, event_irq,
	1458	+ rc = devm_request_irq(&stdev->pdev->dev, event_irq,
1198	1459	switchtec_event_isr, 0,
1199	1460	KBUILD_MODNAME, stdev);
	1461	+
	1462	+ if (rc)
	1463	+ return rc;
	1464	+
	1465	+ if (!stdev->dma_mrpc)
	1466	+ return rc;
	1467	+
	1468	+ dma_mrpc_irq = ioread32(&stdev->mmio_mrpc->dma_vector);
	1469	+ if (dma_mrpc_irq < 0 \|\| dma_mrpc_irq >= nvecs)
	1470	+ return -EFAULT;
	1471	+
	1472	+ dma_mrpc_irq = pci_irq_vector(stdev->pdev, dma_mrpc_irq);
	1473	+ if (dma_mrpc_irq < 0)
	1474	+ return dma_mrpc_irq;
	1475	+
	1476	+ rc = devm_request_irq(&stdev->pdev->dev, dma_mrpc_irq,
	1477	+ switchtec_dma_mrpc_isr, 0,
	1478	+ KBUILD_MODNAME, stdev);
	1479	+
	1480	+ return rc;
1200	1481	}
1201	1482
1202	1483	static void init_pff(struct switchtec_dev *stdev)
1203	1484	{
1204	1485	int i;
1205	1486	u32 reg;
1206		- struct part_cfg_regs *pcfg = stdev->mmio_part_cfg;
	1487	+ struct part_cfg_regs __iomem *pcfg = stdev->mmio_part_cfg;
1207	1488
1208	1489	for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) {
1209	1490	reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id);
..	..	@@ -1214,16 +1495,16 @@
1214	1495	stdev->pff_csr_count = i;
1215	1496
1216	1497	reg = ioread32(&pcfg->usp_pff_inst_id);
1217		- if (reg < SWITCHTEC_MAX_PFF_CSR)
	1498	+ if (reg < stdev->pff_csr_count)
1218	1499	stdev->pff_local[reg] = 1;
1219	1500
1220	1501	reg = ioread32(&pcfg->vep_pff_inst_id);
1221		- if (reg < SWITCHTEC_MAX_PFF_CSR)
	1502	+ if (reg < stdev->pff_csr_count)
1222	1503	stdev->pff_local[reg] = 1;
1223	1504
1224	1505	for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {
1225	1506	reg = ioread32(&pcfg->dsp_pff_inst_id[i]);
1226		- if (reg < SWITCHTEC_MAX_PFF_CSR)
	1507	+ if (reg < stdev->pff_csr_count)
1227	1508	stdev->pff_local[reg] = 1;
1228	1509	}
1229	1510	}
..	..	@@ -1232,24 +1513,52 @@
1232	1513	struct pci_dev *pdev)
1233	1514	{
1234	1515	int rc;
	1516	+ void __iomem *map;
	1517	+ unsigned long res_start, res_len;
	1518	+ u32 __iomem *part_id;
1235	1519
1236	1520	rc = pcim_enable_device(pdev);
1237	1521	if (rc)
1238	1522	return rc;
1239	1523
1240		- rc = pcim_iomap_regions(pdev, 0x1, KBUILD_MODNAME);
	1524	+ rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1241	1525	if (rc)
1242	1526	return rc;
1243	1527
1244	1528	pci_set_master(pdev);
1245	1529
1246		- stdev->mmio = pcim_iomap_table(pdev)[0];
1247		- stdev->mmio_mrpc = stdev->mmio + SWITCHTEC_GAS_MRPC_OFFSET;
	1530	+ res_start = pci_resource_start(pdev, 0);
	1531	+ res_len = pci_resource_len(pdev, 0);
	1532	+
	1533	+ if (!devm_request_mem_region(&pdev->dev, res_start,
	1534	+ res_len, KBUILD_MODNAME))
	1535	+ return -EBUSY;
	1536	+
	1537	+ stdev->mmio_mrpc = devm_ioremap_wc(&pdev->dev, res_start,
	1538	+ SWITCHTEC_GAS_TOP_CFG_OFFSET);
	1539	+ if (!stdev->mmio_mrpc)
	1540	+ return -ENOMEM;
	1541	+
	1542	+ map = devm_ioremap(&pdev->dev,
	1543	+ res_start + SWITCHTEC_GAS_TOP_CFG_OFFSET,
	1544	+ res_len - SWITCHTEC_GAS_TOP_CFG_OFFSET);
	1545	+ if (!map)
	1546	+ return -ENOMEM;
	1547	+
	1548	+ stdev->mmio = map - SWITCHTEC_GAS_TOP_CFG_OFFSET;
1248	1549	stdev->mmio_sw_event = stdev->mmio + SWITCHTEC_GAS_SW_EVENT_OFFSET;
1249	1550	stdev->mmio_sys_info = stdev->mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;
1250	1551	stdev->mmio_flash_info = stdev->mmio + SWITCHTEC_GAS_FLASH_INFO_OFFSET;
1251	1552	stdev->mmio_ntb = stdev->mmio + SWITCHTEC_GAS_NTB_OFFSET;
1252		- stdev->partition = ioread8(&stdev->mmio_sys_info->partition_id);
	1553	+
	1554	+ if (stdev->gen == SWITCHTEC_GEN3)
	1555	+ part_id = &stdev->mmio_sys_info->gen3.partition_id;
	1556	+ else if (stdev->gen == SWITCHTEC_GEN4)
	1557	+ part_id = &stdev->mmio_sys_info->gen4.partition_id;
	1558	+ else
	1559	+ return -ENOTSUPP;
	1560	+
	1561	+ stdev->partition = ioread8(part_id);
1253	1562	stdev->partition_count = ioread8(&stdev->mmio_ntb->partition_count);
1254	1563	stdev->mmio_part_cfg_all = stdev->mmio + SWITCHTEC_GAS_PART_CFG_OFFSET;
1255	1564	stdev->mmio_part_cfg = &stdev->mmio_part_cfg_all[stdev->partition];
..	..	@@ -1261,6 +1570,19 @@
1261	1570	init_pff(stdev);
1262	1571
1263	1572	pci_set_drvdata(pdev, stdev);
	1573	+
	1574	+ if (!use_dma_mrpc)
	1575	+ return 0;
	1576	+
	1577	+ if (ioread32(&stdev->mmio_mrpc->dma_ver) == 0)
	1578	+ return 0;
	1579	+
	1580	+ stdev->dma_mrpc = dma_alloc_coherent(&stdev->pdev->dev,
	1581	+ sizeof(*stdev->dma_mrpc),
	1582	+ &stdev->dma_mrpc_dma_addr,
	1583	+ GFP_KERNEL);
	1584	+ if (stdev->dma_mrpc == NULL)
	1585	+ return -ENOMEM;
1264	1586
1265	1587	return 0;
1266	1588	}
..	..	@@ -1278,6 +1600,8 @@
1278	1600	if (IS_ERR(stdev))
1279	1601	return PTR_ERR(stdev);
1280	1602
	1603	+ stdev->gen = id->driver_data;
	1604	+
1281	1605	rc = switchtec_init_pci(stdev, pdev);
1282	1606	if (rc)
1283	1607	goto err_put;
..	..	@@ -1292,6 +1616,9 @@
1292	1616	SWITCHTEC_EVENT_EN_IRQ,
1293	1617	&stdev->mmio_part_cfg->mrpc_comp_hdr);
1294	1618	enable_link_state_events(stdev);
	1619	+
	1620	+ if (stdev->dma_mrpc)
	1621	+ enable_dma_mrpc(stdev);
1295	1622
1296	1623	rc = cdev_device_add(&stdev->cdev, &stdev->dev);
1297	1624	if (rc)
..	..	@@ -1318,12 +1645,11 @@
1318	1645	cdev_device_del(&stdev->cdev, &stdev->dev);
1319	1646	ida_simple_remove(&switchtec_minor_ida, MINOR(stdev->dev.devt));
1320	1647	dev_info(&stdev->dev, "unregistered.\n");
1321		-
1322	1648	stdev_kill(stdev);
1323	1649	put_device(&stdev->dev);
1324	1650	}
1325	1651
1326		-#define SWITCHTEC_PCI_DEVICE(device_id) \
	1652	+#define SWITCHTEC_PCI_DEVICE(device_id, gen) \
1327	1653	{ \
1328	1654	.vendor = PCI_VENDOR_ID_MICROSEMI, \
1329	1655	.device = device_id, \
..	..	@@ -1331,6 +1657,7 @@
1331	1657	.subdevice = PCI_ANY_ID, \
1332	1658	.class = (PCI_CLASS_MEMORY_OTHER << 8), \
1333	1659	.class_mask = 0xFFFFFFFF, \
	1660	+ .driver_data = gen, \
1334	1661	}, \
1335	1662	{ \
1336	1663	.vendor = PCI_VENDOR_ID_MICROSEMI, \
..	..	@@ -1339,39 +1666,58 @@
1339	1666	.subdevice = PCI_ANY_ID, \
1340	1667	.class = (PCI_CLASS_BRIDGE_OTHER << 8), \
1341	1668	.class_mask = 0xFFFFFFFF, \
	1669	+ .driver_data = gen, \
1342	1670	}
1343	1671
1344	1672	static const struct pci_device_id switchtec_pci_tbl[] = {
1345		- SWITCHTEC_PCI_DEVICE(0x8531), //PFX 24xG3
1346		- SWITCHTEC_PCI_DEVICE(0x8532), //PFX 32xG3
1347		- SWITCHTEC_PCI_DEVICE(0x8533), //PFX 48xG3
1348		- SWITCHTEC_PCI_DEVICE(0x8534), //PFX 64xG3
1349		- SWITCHTEC_PCI_DEVICE(0x8535), //PFX 80xG3
1350		- SWITCHTEC_PCI_DEVICE(0x8536), //PFX 96xG3
1351		- SWITCHTEC_PCI_DEVICE(0x8541), //PSX 24xG3
1352		- SWITCHTEC_PCI_DEVICE(0x8542), //PSX 32xG3
1353		- SWITCHTEC_PCI_DEVICE(0x8543), //PSX 48xG3
1354		- SWITCHTEC_PCI_DEVICE(0x8544), //PSX 64xG3
1355		- SWITCHTEC_PCI_DEVICE(0x8545), //PSX 80xG3
1356		- SWITCHTEC_PCI_DEVICE(0x8546), //PSX 96xG3
1357		- SWITCHTEC_PCI_DEVICE(0x8551), //PAX 24XG3
1358		- SWITCHTEC_PCI_DEVICE(0x8552), //PAX 32XG3
1359		- SWITCHTEC_PCI_DEVICE(0x8553), //PAX 48XG3
1360		- SWITCHTEC_PCI_DEVICE(0x8554), //PAX 64XG3
1361		- SWITCHTEC_PCI_DEVICE(0x8555), //PAX 80XG3
1362		- SWITCHTEC_PCI_DEVICE(0x8556), //PAX 96XG3
1363		- SWITCHTEC_PCI_DEVICE(0x8561), //PFXL 24XG3
1364		- SWITCHTEC_PCI_DEVICE(0x8562), //PFXL 32XG3
1365		- SWITCHTEC_PCI_DEVICE(0x8563), //PFXL 48XG3
1366		- SWITCHTEC_PCI_DEVICE(0x8564), //PFXL 64XG3
1367		- SWITCHTEC_PCI_DEVICE(0x8565), //PFXL 80XG3
1368		- SWITCHTEC_PCI_DEVICE(0x8566), //PFXL 96XG3
1369		- SWITCHTEC_PCI_DEVICE(0x8571), //PFXI 24XG3
1370		- SWITCHTEC_PCI_DEVICE(0x8572), //PFXI 32XG3
1371		- SWITCHTEC_PCI_DEVICE(0x8573), //PFXI 48XG3
1372		- SWITCHTEC_PCI_DEVICE(0x8574), //PFXI 64XG3
1373		- SWITCHTEC_PCI_DEVICE(0x8575), //PFXI 80XG3
1374		- SWITCHTEC_PCI_DEVICE(0x8576), //PFXI 96XG3
	1673	+ SWITCHTEC_PCI_DEVICE(0x8531, SWITCHTEC_GEN3), //PFX 24xG3
	1674	+ SWITCHTEC_PCI_DEVICE(0x8532, SWITCHTEC_GEN3), //PFX 32xG3
	1675	+ SWITCHTEC_PCI_DEVICE(0x8533, SWITCHTEC_GEN3), //PFX 48xG3
	1676	+ SWITCHTEC_PCI_DEVICE(0x8534, SWITCHTEC_GEN3), //PFX 64xG3
	1677	+ SWITCHTEC_PCI_DEVICE(0x8535, SWITCHTEC_GEN3), //PFX 80xG3
	1678	+ SWITCHTEC_PCI_DEVICE(0x8536, SWITCHTEC_GEN3), //PFX 96xG3
	1679	+ SWITCHTEC_PCI_DEVICE(0x8541, SWITCHTEC_GEN3), //PSX 24xG3
	1680	+ SWITCHTEC_PCI_DEVICE(0x8542, SWITCHTEC_GEN3), //PSX 32xG3
	1681	+ SWITCHTEC_PCI_DEVICE(0x8543, SWITCHTEC_GEN3), //PSX 48xG3
	1682	+ SWITCHTEC_PCI_DEVICE(0x8544, SWITCHTEC_GEN3), //PSX 64xG3
	1683	+ SWITCHTEC_PCI_DEVICE(0x8545, SWITCHTEC_GEN3), //PSX 80xG3
	1684	+ SWITCHTEC_PCI_DEVICE(0x8546, SWITCHTEC_GEN3), //PSX 96xG3
	1685	+ SWITCHTEC_PCI_DEVICE(0x8551, SWITCHTEC_GEN3), //PAX 24XG3
	1686	+ SWITCHTEC_PCI_DEVICE(0x8552, SWITCHTEC_GEN3), //PAX 32XG3
	1687	+ SWITCHTEC_PCI_DEVICE(0x8553, SWITCHTEC_GEN3), //PAX 48XG3
	1688	+ SWITCHTEC_PCI_DEVICE(0x8554, SWITCHTEC_GEN3), //PAX 64XG3
	1689	+ SWITCHTEC_PCI_DEVICE(0x8555, SWITCHTEC_GEN3), //PAX 80XG3
	1690	+ SWITCHTEC_PCI_DEVICE(0x8556, SWITCHTEC_GEN3), //PAX 96XG3
	1691	+ SWITCHTEC_PCI_DEVICE(0x8561, SWITCHTEC_GEN3), //PFXL 24XG3
	1692	+ SWITCHTEC_PCI_DEVICE(0x8562, SWITCHTEC_GEN3), //PFXL 32XG3
	1693	+ SWITCHTEC_PCI_DEVICE(0x8563, SWITCHTEC_GEN3), //PFXL 48XG3
	1694	+ SWITCHTEC_PCI_DEVICE(0x8564, SWITCHTEC_GEN3), //PFXL 64XG3
	1695	+ SWITCHTEC_PCI_DEVICE(0x8565, SWITCHTEC_GEN3), //PFXL 80XG3
	1696	+ SWITCHTEC_PCI_DEVICE(0x8566, SWITCHTEC_GEN3), //PFXL 96XG3
	1697	+ SWITCHTEC_PCI_DEVICE(0x8571, SWITCHTEC_GEN3), //PFXI 24XG3
	1698	+ SWITCHTEC_PCI_DEVICE(0x8572, SWITCHTEC_GEN3), //PFXI 32XG3
	1699	+ SWITCHTEC_PCI_DEVICE(0x8573, SWITCHTEC_GEN3), //PFXI 48XG3
	1700	+ SWITCHTEC_PCI_DEVICE(0x8574, SWITCHTEC_GEN3), //PFXI 64XG3
	1701	+ SWITCHTEC_PCI_DEVICE(0x8575, SWITCHTEC_GEN3), //PFXI 80XG3
	1702	+ SWITCHTEC_PCI_DEVICE(0x8576, SWITCHTEC_GEN3), //PFXI 96XG3
	1703	+ SWITCHTEC_PCI_DEVICE(0x4000, SWITCHTEC_GEN4), //PFX 100XG4
	1704	+ SWITCHTEC_PCI_DEVICE(0x4084, SWITCHTEC_GEN4), //PFX 84XG4
	1705	+ SWITCHTEC_PCI_DEVICE(0x4068, SWITCHTEC_GEN4), //PFX 68XG4
	1706	+ SWITCHTEC_PCI_DEVICE(0x4052, SWITCHTEC_GEN4), //PFX 52XG4
	1707	+ SWITCHTEC_PCI_DEVICE(0x4036, SWITCHTEC_GEN4), //PFX 36XG4
	1708	+ SWITCHTEC_PCI_DEVICE(0x4028, SWITCHTEC_GEN4), //PFX 28XG4
	1709	+ SWITCHTEC_PCI_DEVICE(0x4100, SWITCHTEC_GEN4), //PSX 100XG4
	1710	+ SWITCHTEC_PCI_DEVICE(0x4184, SWITCHTEC_GEN4), //PSX 84XG4
	1711	+ SWITCHTEC_PCI_DEVICE(0x4168, SWITCHTEC_GEN4), //PSX 68XG4
	1712	+ SWITCHTEC_PCI_DEVICE(0x4152, SWITCHTEC_GEN4), //PSX 52XG4
	1713	+ SWITCHTEC_PCI_DEVICE(0x4136, SWITCHTEC_GEN4), //PSX 36XG4
	1714	+ SWITCHTEC_PCI_DEVICE(0x4128, SWITCHTEC_GEN4), //PSX 28XG4
	1715	+ SWITCHTEC_PCI_DEVICE(0x4200, SWITCHTEC_GEN4), //PAX 100XG4
	1716	+ SWITCHTEC_PCI_DEVICE(0x4284, SWITCHTEC_GEN4), //PAX 84XG4
	1717	+ SWITCHTEC_PCI_DEVICE(0x4268, SWITCHTEC_GEN4), //PAX 68XG4
	1718	+ SWITCHTEC_PCI_DEVICE(0x4252, SWITCHTEC_GEN4), //PAX 52XG4
	1719	+ SWITCHTEC_PCI_DEVICE(0x4236, SWITCHTEC_GEN4), //PAX 36XG4
	1720	+ SWITCHTEC_PCI_DEVICE(0x4228, SWITCHTEC_GEN4), //PAX 28XG4
1375	1721	{0}
1376	1722	};
1377	1723	MODULE_DEVICE_TABLE(pci, switchtec_pci_tbl);