.. | .. |
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10 | 10 | */ |
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11 | 11 | #include <linux/interrupt.h> |
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12 | 12 | #include <linux/init.h> |
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13 | | -#include <linux/mfd/syscon.h> |
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14 | | -#include <linux/of_address.h> |
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15 | | -#include <linux/of_pci.h> |
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16 | 13 | #include <linux/platform_device.h> |
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17 | | -#include <linux/of_device.h> |
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18 | 14 | #include <linux/pci.h> |
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19 | 15 | #include <linux/pci-acpi.h> |
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20 | 16 | #include <linux/pci-ecam.h> |
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21 | | -#include <linux/regmap.h> |
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22 | 17 | #include "../../pci.h" |
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23 | 18 | |
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24 | 19 | #if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)) |
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.. | .. |
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104 | 99 | return 0; |
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105 | 100 | } |
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106 | 101 | |
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107 | | -struct pci_ecam_ops hisi_pcie_ops = { |
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| 102 | +const struct pci_ecam_ops hisi_pcie_ops = { |
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108 | 103 | .bus_shift = 20, |
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109 | 104 | .init = hisi_pcie_init, |
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110 | 105 | .pci_ops = { |
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.. | .. |
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117 | 112 | #endif |
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118 | 113 | |
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119 | 114 | #ifdef CONFIG_PCI_HISI |
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120 | | - |
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121 | | -#include "pcie-designware.h" |
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122 | | - |
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123 | | -#define PCIE_SUBCTRL_SYS_STATE4_REG 0x6818 |
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124 | | -#define PCIE_HIP06_CTRL_OFF 0x1000 |
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125 | | -#define PCIE_SYS_STATE4 (PCIE_HIP06_CTRL_OFF + 0x31c) |
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126 | | -#define PCIE_LTSSM_LINKUP_STATE 0x11 |
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127 | | -#define PCIE_LTSSM_STATE_MASK 0x3F |
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128 | | - |
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129 | | -#define to_hisi_pcie(x) dev_get_drvdata((x)->dev) |
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130 | | - |
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131 | | -struct hisi_pcie; |
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132 | | - |
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133 | | -struct pcie_soc_ops { |
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134 | | - int (*hisi_pcie_link_up)(struct hisi_pcie *hisi_pcie); |
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135 | | -}; |
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136 | | - |
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137 | | -struct hisi_pcie { |
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138 | | - struct dw_pcie *pci; |
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139 | | - struct regmap *subctrl; |
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140 | | - u32 port_id; |
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141 | | - const struct pcie_soc_ops *soc_ops; |
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142 | | -}; |
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143 | | - |
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144 | | -/* HipXX PCIe host only supports 32-bit config access */ |
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145 | | -static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size, |
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146 | | - u32 *val) |
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147 | | -{ |
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148 | | - u32 reg; |
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149 | | - u32 reg_val; |
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150 | | - void *walker = ®_val; |
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151 | | - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
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152 | | - |
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153 | | - walker += (where & 0x3); |
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154 | | - reg = where & ~0x3; |
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155 | | - reg_val = dw_pcie_readl_dbi(pci, reg); |
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156 | | - |
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157 | | - if (size == 1) |
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158 | | - *val = *(u8 __force *) walker; |
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159 | | - else if (size == 2) |
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160 | | - *val = *(u16 __force *) walker; |
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161 | | - else if (size == 4) |
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162 | | - *val = reg_val; |
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163 | | - else |
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164 | | - return PCIBIOS_BAD_REGISTER_NUMBER; |
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165 | | - |
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166 | | - return PCIBIOS_SUCCESSFUL; |
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167 | | -} |
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168 | | - |
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169 | | -/* HipXX PCIe host only supports 32-bit config access */ |
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170 | | -static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size, |
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171 | | - u32 val) |
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172 | | -{ |
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173 | | - u32 reg_val; |
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174 | | - u32 reg; |
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175 | | - void *walker = ®_val; |
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176 | | - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
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177 | | - |
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178 | | - walker += (where & 0x3); |
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179 | | - reg = where & ~0x3; |
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180 | | - if (size == 4) |
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181 | | - dw_pcie_writel_dbi(pci, reg, val); |
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182 | | - else if (size == 2) { |
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183 | | - reg_val = dw_pcie_readl_dbi(pci, reg); |
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184 | | - *(u16 __force *) walker = val; |
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185 | | - dw_pcie_writel_dbi(pci, reg, reg_val); |
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186 | | - } else if (size == 1) { |
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187 | | - reg_val = dw_pcie_readl_dbi(pci, reg); |
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188 | | - *(u8 __force *) walker = val; |
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189 | | - dw_pcie_writel_dbi(pci, reg, reg_val); |
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190 | | - } else |
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191 | | - return PCIBIOS_BAD_REGISTER_NUMBER; |
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192 | | - |
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193 | | - return PCIBIOS_SUCCESSFUL; |
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194 | | -} |
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195 | | - |
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196 | | -static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie) |
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197 | | -{ |
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198 | | - u32 val; |
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199 | | - |
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200 | | - regmap_read(hisi_pcie->subctrl, PCIE_SUBCTRL_SYS_STATE4_REG + |
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201 | | - 0x100 * hisi_pcie->port_id, &val); |
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202 | | - |
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203 | | - return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); |
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204 | | -} |
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205 | | - |
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206 | | -static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie) |
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207 | | -{ |
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208 | | - struct dw_pcie *pci = hisi_pcie->pci; |
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209 | | - u32 val; |
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210 | | - |
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211 | | - val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4); |
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212 | | - |
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213 | | - return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); |
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214 | | -} |
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215 | | - |
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216 | | -static int hisi_pcie_link_up(struct dw_pcie *pci) |
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217 | | -{ |
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218 | | - struct hisi_pcie *hisi_pcie = to_hisi_pcie(pci); |
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219 | | - |
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220 | | - return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie); |
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221 | | -} |
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222 | | - |
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223 | | -static const struct dw_pcie_host_ops hisi_pcie_host_ops = { |
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224 | | - .rd_own_conf = hisi_pcie_cfg_read, |
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225 | | - .wr_own_conf = hisi_pcie_cfg_write, |
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226 | | -}; |
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227 | | - |
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228 | | -static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie, |
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229 | | - struct platform_device *pdev) |
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230 | | -{ |
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231 | | - struct dw_pcie *pci = hisi_pcie->pci; |
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232 | | - struct pcie_port *pp = &pci->pp; |
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233 | | - struct device *dev = &pdev->dev; |
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234 | | - int ret; |
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235 | | - u32 port_id; |
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236 | | - |
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237 | | - if (of_property_read_u32(dev->of_node, "port-id", &port_id)) { |
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238 | | - dev_err(dev, "failed to read port-id\n"); |
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239 | | - return -EINVAL; |
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240 | | - } |
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241 | | - if (port_id > 3) { |
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242 | | - dev_err(dev, "Invalid port-id: %d\n", port_id); |
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243 | | - return -EINVAL; |
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244 | | - } |
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245 | | - hisi_pcie->port_id = port_id; |
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246 | | - |
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247 | | - pp->ops = &hisi_pcie_host_ops; |
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248 | | - |
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249 | | - ret = dw_pcie_host_init(pp); |
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250 | | - if (ret) { |
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251 | | - dev_err(dev, "failed to initialize host\n"); |
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252 | | - return ret; |
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253 | | - } |
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254 | | - |
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255 | | - return 0; |
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256 | | -} |
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257 | | - |
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258 | | -static const struct dw_pcie_ops dw_pcie_ops = { |
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259 | | - .link_up = hisi_pcie_link_up, |
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260 | | -}; |
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261 | | - |
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262 | | -static int hisi_pcie_probe(struct platform_device *pdev) |
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263 | | -{ |
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264 | | - struct device *dev = &pdev->dev; |
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265 | | - struct dw_pcie *pci; |
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266 | | - struct hisi_pcie *hisi_pcie; |
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267 | | - struct resource *reg; |
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268 | | - int ret; |
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269 | | - |
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270 | | - hisi_pcie = devm_kzalloc(dev, sizeof(*hisi_pcie), GFP_KERNEL); |
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271 | | - if (!hisi_pcie) |
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272 | | - return -ENOMEM; |
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273 | | - |
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274 | | - pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); |
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275 | | - if (!pci) |
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276 | | - return -ENOMEM; |
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277 | | - |
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278 | | - pci->dev = dev; |
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279 | | - pci->ops = &dw_pcie_ops; |
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280 | | - |
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281 | | - hisi_pcie->pci = pci; |
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282 | | - |
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283 | | - hisi_pcie->soc_ops = of_device_get_match_data(dev); |
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284 | | - |
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285 | | - hisi_pcie->subctrl = |
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286 | | - syscon_regmap_lookup_by_compatible("hisilicon,pcie-sas-subctrl"); |
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287 | | - if (IS_ERR(hisi_pcie->subctrl)) { |
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288 | | - dev_err(dev, "cannot get subctrl base\n"); |
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289 | | - return PTR_ERR(hisi_pcie->subctrl); |
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290 | | - } |
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291 | | - |
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292 | | - reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi"); |
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293 | | - pci->dbi_base = devm_pci_remap_cfg_resource(dev, reg); |
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294 | | - if (IS_ERR(pci->dbi_base)) |
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295 | | - return PTR_ERR(pci->dbi_base); |
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296 | | - platform_set_drvdata(pdev, hisi_pcie); |
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297 | | - |
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298 | | - ret = hisi_add_pcie_port(hisi_pcie, pdev); |
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299 | | - if (ret) |
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300 | | - return ret; |
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301 | | - |
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302 | | - return 0; |
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303 | | -} |
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304 | | - |
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305 | | -static struct pcie_soc_ops hip05_ops = { |
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306 | | - &hisi_pcie_link_up_hip05 |
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307 | | -}; |
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308 | | - |
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309 | | -static struct pcie_soc_ops hip06_ops = { |
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310 | | - &hisi_pcie_link_up_hip06 |
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311 | | -}; |
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312 | | - |
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313 | | -static const struct of_device_id hisi_pcie_of_match[] = { |
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314 | | - { |
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315 | | - .compatible = "hisilicon,hip05-pcie", |
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316 | | - .data = (void *) &hip05_ops, |
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317 | | - }, |
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318 | | - { |
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319 | | - .compatible = "hisilicon,hip06-pcie", |
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320 | | - .data = (void *) &hip06_ops, |
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321 | | - }, |
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322 | | - {}, |
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323 | | -}; |
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324 | | - |
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325 | | -static struct platform_driver hisi_pcie_driver = { |
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326 | | - .probe = hisi_pcie_probe, |
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327 | | - .driver = { |
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328 | | - .name = "hisi-pcie", |
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329 | | - .of_match_table = hisi_pcie_of_match, |
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330 | | - .suppress_bind_attrs = true, |
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331 | | - }, |
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332 | | -}; |
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333 | | -builtin_platform_driver(hisi_pcie_driver); |
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334 | | - |
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335 | | -static int hisi_pcie_almost_ecam_probe(struct platform_device *pdev) |
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336 | | -{ |
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337 | | - struct device *dev = &pdev->dev; |
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338 | | - struct pci_ecam_ops *ops; |
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339 | | - |
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340 | | - ops = (struct pci_ecam_ops *)of_device_get_match_data(dev); |
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341 | | - return pci_host_common_probe(pdev, ops); |
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342 | | -} |
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343 | 115 | |
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344 | 116 | static int hisi_pcie_platform_init(struct pci_config_window *cfg) |
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345 | 117 | { |
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.. | .. |
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362 | 134 | return 0; |
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363 | 135 | } |
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364 | 136 | |
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365 | | -struct pci_ecam_ops hisi_pcie_platform_ops = { |
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| 137 | +static const struct pci_ecam_ops hisi_pcie_platform_ops = { |
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366 | 138 | .bus_shift = 20, |
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367 | 139 | .init = hisi_pcie_platform_init, |
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368 | 140 | .pci_ops = { |
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.. | .. |
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375 | 147 | static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = { |
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376 | 148 | { |
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377 | 149 | .compatible = "hisilicon,hip06-pcie-ecam", |
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378 | | - .data = (void *) &hisi_pcie_platform_ops, |
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| 150 | + .data = &hisi_pcie_platform_ops, |
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379 | 151 | }, |
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380 | 152 | { |
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381 | 153 | .compatible = "hisilicon,hip07-pcie-ecam", |
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382 | | - .data = (void *) &hisi_pcie_platform_ops, |
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| 154 | + .data = &hisi_pcie_platform_ops, |
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383 | 155 | }, |
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384 | 156 | {}, |
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385 | 157 | }; |
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386 | 158 | |
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387 | 159 | static struct platform_driver hisi_pcie_almost_ecam_driver = { |
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388 | | - .probe = hisi_pcie_almost_ecam_probe, |
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| 160 | + .probe = pci_host_common_probe, |
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389 | 161 | .driver = { |
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390 | 162 | .name = "hisi-pcie-almost-ecam", |
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391 | 163 | .of_match_table = hisi_pcie_almost_ecam_of_match, |
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