forked from ~ljy/RK356X_SDK_RELEASE

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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/pci/controller/dwc/pcie-designware.c
....@@ -3,23 +3,18 @@
33  * Synopsys DesignWare PCIe host controller driver
44  *
55  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6
- *		http://www.samsung.com
6
+ *		https://www.samsung.com
77  *
88  * Author: Jingoo Han <jg1.han@samsung.com>
99  */
1010 
1111 #include <linux/delay.h>
1212 #include <linux/of.h>
13
+#include <linux/of_platform.h>
1314 #include <linux/types.h>
1415 
1516 #include "../../pci.h"
1617 #include "pcie-designware.h"
17
-
18
-/* PCIe Port Logic registers */
19
-#define PLR_OFFSET			0x700
20
-#define PCIE_PHY_DEBUG_R1		(PLR_OFFSET + 0x2c)
21
-#define PCIE_PHY_DEBUG_R1_LINK_UP	(0x1 << 4)
22
-#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING	(0x1 << 29)
2318 
2419 /*
2520  * These interfaces resemble the pci_find_*capability() interfaces, but these
....@@ -60,9 +55,50 @@
6055 }
6156 EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
6257 
58
+static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
59
+					    u8 cap)
60
+{
61
+	u32 header;
62
+	int ttl;
63
+	int pos = PCI_CFG_SPACE_SIZE;
64
+
65
+	/* minimum 8 bytes per capability */
66
+	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
67
+
68
+	if (start)
69
+		pos = start;
70
+
71
+	header = dw_pcie_readl_dbi(pci, pos);
72
+	/*
73
+	 * If we have no capabilities, this is indicated by cap ID,
74
+	 * cap version and next pointer all being 0.
75
+	 */
76
+	if (header == 0)
77
+		return 0;
78
+
79
+	while (ttl-- > 0) {
80
+		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
81
+			return pos;
82
+
83
+		pos = PCI_EXT_CAP_NEXT(header);
84
+		if (pos < PCI_CFG_SPACE_SIZE)
85
+			break;
86
+
87
+		header = dw_pcie_readl_dbi(pci, pos);
88
+	}
89
+
90
+	return 0;
91
+}
92
+
93
+u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
94
+{
95
+	return dw_pcie_find_next_ext_capability(pci, 0, cap);
96
+}
97
+EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
98
+
6399 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
64100 {
65
-	if ((uintptr_t)addr & (size - 1)) {
101
+	if (!IS_ALIGNED((uintptr_t)addr, size)) {
66102 		*val = 0;
67103 		return PCIBIOS_BAD_REGISTER_NUMBER;
68104 	}
....@@ -80,10 +116,11 @@
80116 
81117 	return PCIBIOS_SUCCESSFUL;
82118 }
119
+EXPORT_SYMBOL_GPL(dw_pcie_read);
83120 
84121 int dw_pcie_write(void __iomem *addr, int size, u32 val)
85122 {
86
-	if ((uintptr_t)addr & (size - 1))
123
+	if (!IS_ALIGNED((uintptr_t)addr, size))
87124 		return PCIBIOS_BAD_REGISTER_NUMBER;
88125 
89126 	if (size == 4)
....@@ -97,43 +134,87 @@
97134 
98135 	return PCIBIOS_SUCCESSFUL;
99136 }
137
+EXPORT_SYMBOL_GPL(dw_pcie_write);
100138 
101
-u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
102
-		       size_t size)
139
+u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
103140 {
104141 	int ret;
105142 	u32 val;
106143 
107144 	if (pci->ops->read_dbi)
108
-		return pci->ops->read_dbi(pci, base, reg, size);
145
+		return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
109146 
110
-	ret = dw_pcie_read(base + reg, size, &val);
147
+	ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
111148 	if (ret)
112149 		dev_err(pci->dev, "Read DBI address failed\n");
113150 
114151 	return val;
115152 }
153
+EXPORT_SYMBOL_GPL(dw_pcie_read_dbi);
116154 
117
-void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
118
-			 size_t size, u32 val)
155
+void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
119156 {
120157 	int ret;
121158 
122159 	if (pci->ops->write_dbi) {
123
-		pci->ops->write_dbi(pci, base, reg, size, val);
160
+		pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
124161 		return;
125162 	}
126163 
127
-	ret = dw_pcie_write(base + reg, size, val);
164
+	ret = dw_pcie_write(pci->dbi_base + reg, size, val);
128165 	if (ret)
129166 		dev_err(pci->dev, "Write DBI address failed\n");
167
+}
168
+EXPORT_SYMBOL_GPL(dw_pcie_write_dbi);
169
+
170
+void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
171
+{
172
+	int ret;
173
+
174
+	if (pci->ops->write_dbi2) {
175
+		pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
176
+		return;
177
+	}
178
+
179
+	ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
180
+	if (ret)
181
+		dev_err(pci->dev, "write DBI address failed\n");
182
+}
183
+
184
+static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg)
185
+{
186
+	int ret;
187
+	u32 val;
188
+
189
+	if (pci->ops->read_dbi)
190
+		return pci->ops->read_dbi(pci, pci->atu_base, reg, 4);
191
+
192
+	ret = dw_pcie_read(pci->atu_base + reg, 4, &val);
193
+	if (ret)
194
+		dev_err(pci->dev, "Read ATU address failed\n");
195
+
196
+	return val;
197
+}
198
+
199
+static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)
200
+{
201
+	int ret;
202
+
203
+	if (pci->ops->write_dbi) {
204
+		pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val);
205
+		return;
206
+	}
207
+
208
+	ret = dw_pcie_write(pci->atu_base + reg, 4, val);
209
+	if (ret)
210
+		dev_err(pci->dev, "Write ATU address failed\n");
130211 }
131212 
132213 static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
133214 {
134215 	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
135216 
136
-	return dw_pcie_readl_dbi(pci, offset + reg);
217
+	return dw_pcie_readl_atu(pci, offset + reg);
137218 }
138219 
139220 static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
....@@ -141,27 +222,31 @@
141222 {
142223 	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
143224 
144
-	dw_pcie_writel_dbi(pci, offset + reg, val);
225
+	dw_pcie_writel_atu(pci, offset + reg, val);
145226 }
146227 
147
-static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
148
-					     int type, u64 cpu_addr,
149
-					     u64 pci_addr, u32 size)
228
+static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
229
+					     int index, int type,
230
+					     u64 cpu_addr, u64 pci_addr,
231
+					     u32 size)
150232 {
151233 	u32 retries, val;
234
+	u64 limit_addr = cpu_addr + size - 1;
152235 
153236 	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
154237 				 lower_32_bits(cpu_addr));
155238 	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
156239 				 upper_32_bits(cpu_addr));
157
-	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
158
-				 lower_32_bits(cpu_addr + size - 1));
240
+	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT,
241
+				 lower_32_bits(limit_addr));
242
+	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
243
+				 upper_32_bits(limit_addr));
159244 	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
160245 				 lower_32_bits(pci_addr));
161246 	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
162247 				 upper_32_bits(pci_addr));
163248 	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
164
-				 type);
249
+				 type | PCIE_ATU_FUNC_NUM(func_no));
165250 	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
166251 				 PCIE_ATU_ENABLE);
167252 
....@@ -180,17 +265,18 @@
180265 	dev_err(pci->dev, "Outbound iATU is not being enabled\n");
181266 }
182267 
183
-void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
184
-			       u64 cpu_addr, u64 pci_addr, u32 size)
268
+static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
269
+					int index, int type, u64 cpu_addr,
270
+					u64 pci_addr, u32 size)
185271 {
186272 	u32 retries, val;
187273 
188274 	if (pci->ops->cpu_addr_fixup)
189275 		cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
190276 
191
-	if (pci->iatu_unroll_enabled) {
192
-		dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
193
-						 pci_addr, size);
277
+	if (pci->iatu_unroll_enabled & DWC_IATU_UNROLL_EN) {
278
+		dw_pcie_prog_outbound_atu_unroll(pci, func_no, index, type,
279
+						 cpu_addr, pci_addr, size);
194280 		return;
195281 	}
196282 
....@@ -206,7 +292,8 @@
206292 			   lower_32_bits(pci_addr));
207293 	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
208294 			   upper_32_bits(pci_addr));
209
-	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
295
+	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
296
+			   PCIE_ATU_FUNC_NUM(func_no));
210297 	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
211298 
212299 	/*
....@@ -223,11 +310,26 @@
223310 	dev_err(pci->dev, "Outbound iATU is not being enabled\n");
224311 }
225312 
313
+void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
314
+			       u64 cpu_addr, u64 pci_addr, u32 size)
315
+{
316
+	__dw_pcie_prog_outbound_atu(pci, 0, index, type,
317
+				    cpu_addr, pci_addr, size);
318
+}
319
+
320
+void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
321
+				  int type, u64 cpu_addr, u64 pci_addr,
322
+				  u32 size)
323
+{
324
+	__dw_pcie_prog_outbound_atu(pci, func_no, index, type,
325
+				    cpu_addr, pci_addr, size);
326
+}
327
+
226328 static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
227329 {
228330 	u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
229331 
230
-	return dw_pcie_readl_dbi(pci, offset + reg);
332
+	return dw_pcie_readl_atu(pci, offset + reg);
231333 }
232334 
233335 static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
....@@ -235,11 +337,11 @@
235337 {
236338 	u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
237339 
238
-	dw_pcie_writel_dbi(pci, offset + reg, val);
340
+	dw_pcie_writel_atu(pci, offset + reg, val);
239341 }
240342 
241
-static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
242
-					   int bar, u64 cpu_addr,
343
+static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
344
+					   int index, int bar, u64 cpu_addr,
243345 					   enum dw_pcie_as_type as_type)
244346 {
245347 	int type;
....@@ -261,8 +363,10 @@
261363 		return -EINVAL;
262364 	}
263365 
264
-	dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type);
366
+	dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type |
367
+				 PCIE_ATU_FUNC_NUM(func_no));
265368 	dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
369
+				 PCIE_ATU_FUNC_NUM_MATCH_EN |
266370 				 PCIE_ATU_ENABLE |
267371 				 PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
268372 
....@@ -283,14 +387,15 @@
283387 	return -EBUSY;
284388 }
285389 
286
-int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
287
-			     u64 cpu_addr, enum dw_pcie_as_type as_type)
390
+int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
391
+			     int bar, u64 cpu_addr,
392
+			     enum dw_pcie_as_type as_type)
288393 {
289394 	int type;
290395 	u32 retries, val;
291396 
292
-	if (pci->iatu_unroll_enabled)
293
-		return dw_pcie_prog_inbound_atu_unroll(pci, index, bar,
397
+	if (pci->iatu_unroll_enabled & DWC_IATU_UNROLL_EN)
398
+		return dw_pcie_prog_inbound_atu_unroll(pci, func_no, index, bar,
294399 						       cpu_addr, as_type);
295400 
296401 	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
....@@ -309,9 +414,11 @@
309414 		return -EINVAL;
310415 	}
311416 
312
-	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
313
-	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE
314
-			   | PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
417
+	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
418
+			   PCIE_ATU_FUNC_NUM(func_no));
419
+	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE |
420
+			   PCIE_ATU_FUNC_NUM_MATCH_EN |
421
+			   PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
315422 
316423 	/*
317424 	 * Make sure ATU enable takes effect before any subsequent config
....@@ -332,7 +439,7 @@
332439 void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
333440 			 enum dw_pcie_region_type type)
334441 {
335
-	int region;
442
+	u32 region;
336443 
337444 	switch (type) {
338445 	case DW_PCIE_REGION_INBOUND:
....@@ -345,8 +452,18 @@
345452 		return;
346453 	}
347454 
348
-	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
349
-	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE);
455
+	if (pci->iatu_unroll_enabled) {
456
+		if (region == PCIE_ATU_REGION_INBOUND) {
457
+			dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
458
+						 ~(u32)PCIE_ATU_ENABLE);
459
+		} else {
460
+			dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
461
+						 ~(u32)PCIE_ATU_ENABLE);
462
+		}
463
+	} else {
464
+		dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
465
+		dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE);
466
+	}
350467 }
351468 
352469 int dw_pcie_wait_for_link(struct dw_pcie *pci)
....@@ -362,10 +479,11 @@
362479 		usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
363480 	}
364481 
365
-	dev_err(pci->dev, "Phy link never came up\n");
482
+	dev_info(pci->dev, "Phy link never came up\n");
366483 
367484 	return -ETIMEDOUT;
368485 }
486
+EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link);
369487 
370488 int dw_pcie_link_up(struct dw_pcie *pci)
371489 {
....@@ -374,10 +492,21 @@
374492 	if (pci->ops->link_up)
375493 		return pci->ops->link_up(pci);
376494 
377
-	val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
378
-	return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
379
-		(!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
495
+	val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
496
+	return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
497
+		(!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
380498 }
499
+EXPORT_SYMBOL_GPL(dw_pcie_link_up);
500
+
501
+void dw_pcie_upconfig_setup(struct dw_pcie *pci)
502
+{
503
+	u32 val;
504
+
505
+	val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
506
+	val |= PORT_MLTI_UPCFG_SUPPORT;
507
+	dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
508
+}
509
+EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
381510 
382511 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
383512 {
....@@ -415,25 +544,79 @@
415544 
416545 }
417546 
547
+static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
548
+{
549
+	u32 val;
550
+
551
+	val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
552
+	if (val == 0xffffffff)
553
+		return 1;
554
+
555
+	return 0;
556
+}
557
+
418558 void dw_pcie_setup(struct dw_pcie *pci)
419559 {
420
-	int ret;
421560 	u32 val;
422
-	u32 lanes;
423561 	struct device *dev = pci->dev;
424562 	struct device_node *np = dev->of_node;
563
+	struct platform_device *pdev = to_platform_device(dev);
564
+
565
+	if (pci->version >= 0x480A || (!pci->version &&
566
+				       dw_pcie_iatu_unroll_enabled(pci))) {
567
+		pci->iatu_unroll_enabled |= DWC_IATU_UNROLL_EN;
568
+		if (!pci->atu_base)
569
+			pci->atu_base =
570
+			    devm_platform_ioremap_resource_byname(pdev, "atu");
571
+		if (IS_ERR(pci->atu_base))
572
+			pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
573
+	}
574
+	dev_dbg(pci->dev, "iATU unroll: %s\n",
575
+		pci->iatu_unroll_enabled & DWC_IATU_UNROLL_EN ?
576
+		"enabled" : "disabled");
425577 
426578 	if (pci->link_gen > 0)
427579 		dw_pcie_link_set_max_speed(pci, pci->link_gen);
428580 
429
-	ret = of_property_read_u32(np, "num-lanes", &lanes);
430
-	if (ret)
431
-		lanes = 0;
581
+	/* Configure Gen1 N_FTS */
582
+	if (pci->n_fts[0]) {
583
+		val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
584
+		val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK);
585
+		val |= PORT_AFR_N_FTS(pci->n_fts[0]);
586
+		val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]);
587
+		dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
588
+	}
589
+
590
+	/* Configure Gen2+ N_FTS */
591
+	if (pci->n_fts[1]) {
592
+		val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
593
+		val &= ~PORT_LOGIC_N_FTS_MASK;
594
+		val |= pci->n_fts[1];
595
+		dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
596
+	}
597
+
598
+	val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
599
+	val &= ~PORT_LINK_FAST_LINK_MODE;
600
+	val |= PORT_LINK_DLL_LINK_EN;
601
+	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
602
+
603
+	if (of_property_read_bool(np, "snps,enable-cdm-check")) {
604
+		val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
605
+		val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
606
+		       PCIE_PL_CHK_REG_CHK_REG_START;
607
+		dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
608
+	}
609
+
610
+	of_property_read_u32(np, "num-lanes", &pci->num_lanes);
611
+	if (!pci->num_lanes) {
612
+		dev_dbg(pci->dev, "Using h/w default number of lanes\n");
613
+		return;
614
+	}
432615 
433616 	/* Set the number of lanes */
434
-	val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
617
+	val &= ~PORT_LINK_FAST_LINK_MODE;
435618 	val &= ~PORT_LINK_MODE_MASK;
436
-	switch (lanes) {
619
+	switch (pci->num_lanes) {
437620 	case 1:
438621 		val |= PORT_LINK_MODE_1_LANES;
439622 		break;
....@@ -447,7 +630,7 @@
447630 		val |= PORT_LINK_MODE_8_LANES;
448631 		break;
449632 	default:
450
-		dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
633
+		dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
451634 		return;
452635 	}
453636 	dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
....@@ -455,7 +638,7 @@
455638 	/* Set link width speed control register */
456639 	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
457640 	val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
458
-	switch (lanes) {
641
+	switch (pci->num_lanes) {
459642 	case 1:
460643 		val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
461644 		break;