.. | .. |
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7 | 7 | bool |
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8 | 8 | |
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9 | 9 | config PCIE_DW_HOST |
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10 | | - bool |
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| 10 | + bool |
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11 | 11 | depends on PCI_MSI_IRQ_DOMAIN |
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12 | | - select PCIE_DW |
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| 12 | + select PCIE_DW |
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13 | 13 | |
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14 | 14 | config PCIE_DW_EP |
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15 | 15 | bool |
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.. | .. |
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26 | 26 | depends on OF && HAS_IOMEM && TI_PIPE3 |
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27 | 27 | select PCIE_DW_HOST |
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28 | 28 | select PCI_DRA7XX |
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29 | | - default y |
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| 29 | + default y if SOC_DRA7XX |
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30 | 30 | help |
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31 | 31 | Enables support for the PCIe controller in the DRA7xx SoC to work in |
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32 | 32 | host mode. There are two instances of PCIe controller in DRA7xx. |
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.. | .. |
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83 | 83 | selected. |
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84 | 84 | |
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85 | 85 | config PCIE_DW_ROCKCHIP |
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86 | | - bool "Rockchip DesignWare PCIe controller" |
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| 86 | + tristate "Rockchip DesignWare PCIe controller" |
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87 | 87 | select PCIE_DW |
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88 | 88 | select PCIE_DW_HOST |
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89 | 89 | depends on ARCH_ROCKCHIP |
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90 | 90 | depends on OF |
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91 | 91 | help |
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92 | 92 | Enables support for the DW PCIe controller in the Rockchip SoC. |
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| 93 | + |
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| 94 | +config PCIE_RK_THREADED_INIT |
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| 95 | + bool "Threaded initialize Rockchip DW based PCIe controller" |
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| 96 | + depends on PCIE_DW_ROCKCHIP |
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| 97 | + default y |
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| 98 | + help |
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| 99 | + Enables threaded initialize Rockchip DW based PCIe controller. |
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93 | 100 | |
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94 | 101 | config PCIE_DW_DMATEST |
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95 | 102 | bool "DesignWare PCIe DMA test" |
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.. | .. |
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106 | 113 | help |
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107 | 114 | Enables support for the DW PCIe controller in the Rockchip SoC. |
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108 | 115 | |
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109 | | -config PCIE_RK_THREADED_INIT |
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110 | | - bool "Threaded initialize Rockchip DW based PCIe controller" |
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111 | | - depends on PCIE_DW_ROCKCHIP |
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112 | | - default y |
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113 | | - help |
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114 | | - Enables threaded initialize Rockchip DW based PCIe controller. |
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115 | | - |
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116 | 116 | config PCI_EXYNOS |
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117 | 117 | bool "Samsung Exynos PCIe controller" |
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118 | 118 | depends on SOC_EXYNOS5440 || COMPILE_TEST |
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.. | .. |
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120 | 120 | select PCIE_DW_HOST |
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121 | 121 | |
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122 | 122 | config PCI_IMX6 |
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123 | | - bool "Freescale i.MX6 PCIe controller" |
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124 | | - depends on SOC_IMX6Q || (ARM && COMPILE_TEST) |
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| 123 | + bool "Freescale i.MX6/7/8 PCIe controller" |
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| 124 | + depends on ARCH_MXC || COMPILE_TEST |
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125 | 125 | depends on PCI_MSI_IRQ_DOMAIN |
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126 | 126 | select PCIE_DW_HOST |
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127 | 127 | |
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.. | .. |
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134 | 134 | Say Y here if you want PCIe support on SPEAr13XX SoCs. |
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135 | 135 | |
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136 | 136 | config PCI_KEYSTONE |
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137 | | - bool "TI Keystone PCIe controller" |
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138 | | - depends on ARCH_KEYSTONE || (ARM && COMPILE_TEST) |
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| 137 | + bool |
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| 138 | + |
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| 139 | +config PCI_KEYSTONE_HOST |
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| 140 | + bool "PCI Keystone Host Mode" |
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| 141 | + depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) |
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139 | 142 | depends on PCI_MSI_IRQ_DOMAIN |
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140 | 143 | select PCIE_DW_HOST |
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| 144 | + select PCI_KEYSTONE |
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141 | 145 | help |
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142 | | - Say Y here if you want to enable PCI controller support on Keystone |
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143 | | - SoCs. The PCI controller on Keystone is based on DesignWare hardware |
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144 | | - and therefore the driver re-uses the DesignWare core functions to |
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145 | | - implement the driver. |
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| 146 | + Enables support for the PCIe controller in the Keystone SoC to |
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| 147 | + work in host mode. The PCI controller on Keystone is based on |
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| 148 | + DesignWare hardware and therefore the driver re-uses the |
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| 149 | + DesignWare core functions to implement the driver. |
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| 150 | + |
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| 151 | +config PCI_KEYSTONE_EP |
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| 152 | + bool "PCI Keystone Endpoint Mode" |
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| 153 | + depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) |
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| 154 | + depends on PCI_ENDPOINT |
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| 155 | + select PCIE_DW_EP |
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| 156 | + select PCI_KEYSTONE |
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| 157 | + help |
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| 158 | + Enables support for the PCIe controller in the Keystone SoC to |
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| 159 | + work in endpoint mode. The PCI controller on Keystone is based |
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| 160 | + on DesignWare hardware and therefore the driver re-uses the |
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| 161 | + DesignWare core functions to implement the driver. |
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146 | 162 | |
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147 | 163 | config PCI_LAYERSCAPE |
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148 | | - bool "Freescale Layerscape PCIe controller" |
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| 164 | + bool "Freescale Layerscape PCIe controller - Host mode" |
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149 | 165 | depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) |
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150 | 166 | depends on PCI_MSI_IRQ_DOMAIN |
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151 | 167 | select MFD_SYSCON |
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152 | 168 | select PCIE_DW_HOST |
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153 | 169 | help |
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154 | | - Say Y here if you want PCIe controller support on Layerscape SoCs. |
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| 170 | + Say Y here if you want to enable PCIe controller support on Layerscape |
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| 171 | + SoCs to work in Host mode. |
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| 172 | + This controller can work either as EP or RC. The RCW[HOST_AGT_PEX] |
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| 173 | + determines which PCIe controller works in EP mode and which PCIe |
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| 174 | + controller works in RC mode. |
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| 175 | + |
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| 176 | +config PCI_LAYERSCAPE_EP |
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| 177 | + bool "Freescale Layerscape PCIe controller - Endpoint mode" |
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| 178 | + depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) |
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| 179 | + depends on PCI_ENDPOINT |
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| 180 | + select PCIE_DW_EP |
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| 181 | + help |
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| 182 | + Say Y here if you want to enable PCIe controller support on Layerscape |
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| 183 | + SoCs to work in Endpoint mode. |
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| 184 | + This controller can work either as EP or RC. The RCW[HOST_AGT_PEX] |
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| 185 | + determines which PCIe controller works in EP mode and which PCIe |
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| 186 | + controller works in RC mode. |
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155 | 187 | |
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156 | 188 | config PCI_HISI |
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157 | 189 | depends on OF && (ARM64 || COMPILE_TEST) |
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.. | .. |
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207 | 239 | Enables support for the PCIe controller in the ARTPEC-6 SoC to work in |
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208 | 240 | endpoint mode. This uses the DesignWare core. |
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209 | 241 | |
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| 242 | +config PCIE_INTEL_GW |
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| 243 | + bool "Intel Gateway PCIe host controller support" |
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| 244 | + depends on OF && (X86 || COMPILE_TEST) |
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| 245 | + depends on PCI_MSI_IRQ_DOMAIN |
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| 246 | + select PCIE_DW_HOST |
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| 247 | + help |
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| 248 | + Say 'Y' here to enable PCIe Host controller support on Intel |
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| 249 | + Gateway SoCs. |
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| 250 | + The PCIe controller uses the DesignWare core plus Intel-specific |
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| 251 | + hardware wrappers. |
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| 252 | + |
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210 | 253 | config PCIE_KIRIN |
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211 | 254 | depends on OF && (ARM64 || COMPILE_TEST) |
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212 | 255 | bool "HiSilicon Kirin series SoCs PCIe controllers" |
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.. | .. |
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222 | 265 | depends on PCI_MSI_IRQ_DOMAIN |
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223 | 266 | select PCIE_DW_HOST |
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224 | 267 | help |
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225 | | - Say Y here if you want PCIe controller support on HiSilicon STB SoCs |
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| 268 | + Say Y here if you want PCIe controller support on HiSilicon STB SoCs |
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| 269 | + |
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| 270 | +config PCI_MESON |
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| 271 | + tristate "MESON PCIe controller" |
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| 272 | + depends on PCI_MSI_IRQ_DOMAIN |
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| 273 | + default m if ARCH_MESON |
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| 274 | + select PCIE_DW_HOST |
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| 275 | + help |
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| 276 | + Say Y here if you want to enable PCI controller support on Amlogic |
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| 277 | + SoCs. The PCI controller on Amlogic is based on DesignWare hardware |
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| 278 | + and therefore the driver re-uses the DesignWare core functions to |
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| 279 | + implement the driver. |
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| 280 | + |
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| 281 | +config PCIE_TEGRA194 |
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| 282 | + tristate |
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| 283 | + |
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| 284 | +config PCIE_TEGRA194_HOST |
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| 285 | + tristate "NVIDIA Tegra194 (and later) PCIe controller - Host Mode" |
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| 286 | + depends on ARCH_TEGRA_194_SOC || COMPILE_TEST |
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| 287 | + depends on PCI_MSI_IRQ_DOMAIN |
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| 288 | + select PCIE_DW_HOST |
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| 289 | + select PHY_TEGRA194_P2U |
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| 290 | + select PCIE_TEGRA194 |
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| 291 | + help |
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| 292 | + Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to |
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| 293 | + work in host mode. There are two instances of PCIe controllers in |
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| 294 | + Tegra194. This controller can work either as EP or RC. In order to |
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| 295 | + enable host-specific features PCIE_TEGRA194_HOST must be selected and |
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| 296 | + in order to enable device-specific features PCIE_TEGRA194_EP must be |
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| 297 | + selected. This uses the DesignWare core. |
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| 298 | + |
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| 299 | +config PCIE_TEGRA194_EP |
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| 300 | + tristate "NVIDIA Tegra194 (and later) PCIe controller - Endpoint Mode" |
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| 301 | + depends on ARCH_TEGRA_194_SOC || COMPILE_TEST |
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| 302 | + depends on PCI_ENDPOINT |
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| 303 | + select PCIE_DW_EP |
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| 304 | + select PHY_TEGRA194_P2U |
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| 305 | + select PCIE_TEGRA194 |
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| 306 | + help |
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| 307 | + Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to |
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| 308 | + work in host mode. There are two instances of PCIe controllers in |
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| 309 | + Tegra194. This controller can work either as EP or RC. In order to |
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| 310 | + enable host-specific features PCIE_TEGRA194_HOST must be selected and |
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| 311 | + in order to enable device-specific features PCIE_TEGRA194_EP must be |
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| 312 | + selected. This uses the DesignWare core. |
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| 313 | + |
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| 314 | +config PCIE_UNIPHIER |
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| 315 | + bool "Socionext UniPhier PCIe host controllers" |
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| 316 | + depends on ARCH_UNIPHIER || COMPILE_TEST |
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| 317 | + depends on OF && HAS_IOMEM |
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| 318 | + depends on PCI_MSI_IRQ_DOMAIN |
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| 319 | + select PCIE_DW_HOST |
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| 320 | + help |
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| 321 | + Say Y here if you want PCIe host controller support on UniPhier SoCs. |
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| 322 | + This driver supports LD20 and PXs3 SoCs. |
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| 323 | + |
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| 324 | +config PCIE_UNIPHIER_EP |
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| 325 | + bool "Socionext UniPhier PCIe endpoint controllers" |
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| 326 | + depends on ARCH_UNIPHIER || COMPILE_TEST |
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| 327 | + depends on OF && HAS_IOMEM |
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| 328 | + depends on PCI_ENDPOINT |
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| 329 | + select PCIE_DW_EP |
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| 330 | + help |
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| 331 | + Say Y here if you want PCIe endpoint controller support on |
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| 332 | + UniPhier SoCs. This driver supports Pro5 SoC. |
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| 333 | + |
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| 334 | +config PCIE_AL |
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| 335 | + bool "Amazon Annapurna Labs PCIe controller" |
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| 336 | + depends on OF && (ARM64 || COMPILE_TEST) |
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| 337 | + depends on PCI_MSI_IRQ_DOMAIN |
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| 338 | + select PCIE_DW_HOST |
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| 339 | + help |
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| 340 | + Say Y here to enable support of the Amazon's Annapurna Labs PCIe |
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| 341 | + controller IP on Amazon SoCs. The PCIe controller uses the DesignWare |
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| 342 | + core plus Annapurna Labs proprietary hardware wrappers. This is |
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| 343 | + required only for DT-based platforms. ACPI platforms with the |
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| 344 | + Annapurna Labs PCIe controller don't need to enable this. |
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226 | 345 | |
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227 | 346 | endmenu |
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