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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h
....@@ -1,27 +1,6 @@
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-/******************************************************************************
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- *
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- * Copyright(c) 2009-2012  Realtek Corporation.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of version 2 of the GNU General Public License as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * The full GNU General Public License is included in this distribution in the
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- * file called LICENSE.
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- *
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- * Contact Information:
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- * wlanfae <wlanfae@realtek.com>
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- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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- * Hsinchu 300, Taiwan.
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- *
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- * Larry Finger <Larry.Finger@lwfinger.net>
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- *
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- *****************************************************************************/
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/* Copyright(c) 2009-2012  Realtek Corporation.*/
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+
254 #ifndef __REALTEK_92S_REG_H__
265 #define __REALTEK_92S_REG_H__
276 
....@@ -190,7 +169,7 @@
190169 #define	BCNTCFG					0x01E0
191170 #define	CWRR					0x01E2
192171 #define	ACMAVG					0x01E4
193
-#define	AcmHwCtrl				0x01E7
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+#define	ACMHWCTRL				0x01E7
194173 #define	VO_ADMTM				0x01E8
195174 #define	VI_ADMTM				0x01EC
196175 #define	BE_ADMTM				0x01F0
....@@ -256,7 +235,7 @@
256235 #define	INTA_MASK				0x0300
257236 #define	ISR					0x0308
258237 
259
-/* 13. Test Mode and Debug Control Registers */
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+/* 13. Test mode and Debug Control Registers */
260239 #define	DBG_PORT_SWITCH				0x003A
261240 #define	BIST					0x0310
262241 #define	DBS					0x0314
....@@ -346,9 +325,9 @@
346325 #define	SYS_SWHW_SEL				BIT(14)
347326 #define	SYS_FWHW_SEL				BIT(15)
348327 
349
-#define	CmdEEPROM_En				BIT(5)
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-#define	CmdEERPOMSEL				BIT(4)
351
-#define	Cmd9346CR_9356SEL			BIT(4)
328
+#define	CMDEEPROM_EN				BIT(5)
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+#define	CMDEERPOMSEL				BIT(4)
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+#define	CMD9346CR_9356SEL			BIT(4)
352331 
353332 #define	AFE_MBEN				BIT(1)
354333 #define	AFE_BGEN				BIT(0)
....@@ -369,9 +348,9 @@
369348 
370349 #define	APLL_EN					BIT(0)
371350 
372
-#define	AFR_CardBEn				BIT(0)
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+#define	AFR_CARDBEN				BIT(0)
373352 #define	AFR_CLKRUN_SEL				BIT(1)
374
-#define	AFR_FuncRegEn				BIT(2)
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+#define	AFR_FUNCREGEN				BIT(2)
375354 
376355 #define	APSDOFF_STATUS				BIT(15)
377356 #define	APSDOFF					BIT(14)
....@@ -387,13 +366,13 @@
387366 #define	HCI_RXDMA_EN				BIT(3)
388367 #define	HCI_TXDMA_EN				BIT(2)
389368 
390
-#define	StopHCCA				BIT(6)
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-#define	StopHigh				BIT(5)
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-#define	StopMgt					BIT(4)
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-#define	StopVO					BIT(3)
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-#define	StopVI					BIT(2)
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-#define	StopBE					BIT(1)
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-#define	StopBK					BIT(0)
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+#define	STOPHCCA				BIT(6)
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+#define	STOPHIGH				BIT(5)
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+#define	STOPMGT					BIT(4)
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+#define	STOPVO					BIT(3)
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+#define	STOPVI					BIT(2)
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+#define	STOPBE					BIT(1)
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+#define	STOPBK					BIT(0)
397376 
398377 #define	LBK_NORMAL				0x00
399378 #define	LBK_MAC_LB				(BIT(0) | BIT(1) | BIT(3))
....@@ -405,7 +384,7 @@
405384 #define	TXDMAPRE2FULL				BIT(23)
406385 #define	DISCW					BIT(20)
407386 #define	TCRICV					BIT(19)
408
-#define	CfendForm				BIT(17)
387
+#define	cfendform				BIT(17)
409388 #define	TCRCRC					BIT(16)
410389 #define	FAKE_IMEM_EN				BIT(15)
411390 #define	TSFRST					BIT(9)
....@@ -530,7 +509,7 @@
530509 #define	RRSR_MCS5				BIT(17)
531510 #define	RRSR_MCS6				BIT(18)
532511 #define	RRSR_MCS7				BIT(19)
533
-#define	BRSR_AckShortPmb			BIT(23)
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+#define	BRSR_ACKSHORTPMB			BIT(23)
534513 
535514 #define	RATR_1M					0x00000001
536515 #define	RATR_2M					0x00000002
....@@ -581,13 +560,13 @@
581560 #define	AC_PARAM_ECW_MIN_OFFSET			8
582561 #define	AC_PARAM_AIFS_OFFSET			0
583562 
584
-#define	AcmHw_HwEn				BIT(0)
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-#define	AcmHw_BeqEn				BIT(1)
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-#define	AcmHw_ViqEn				BIT(2)
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-#define	AcmHw_VoqEn				BIT(3)
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-#define	AcmHw_BeqStatus				BIT(4)
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-#define	AcmHw_ViqStatus				BIT(5)
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-#define	AcmHw_VoqStatus				BIT(6)
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+#define	ACMHW_HWEN				BIT(0)
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+#define	ACMHW_BEQEN				BIT(1)
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+#define	ACMHW_VIQEN				BIT(2)
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+#define	ACMHW_VOQEN				BIT(3)
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+#define	ACMHW_BEQSTATUS				BIT(4)
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+#define	ACMHW_VIQSTATUS				BIT(5)
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+#define	ACMHW_VOQSTATUS				BIT(6)
591570 
592571 #define	RETRY_LIMIT_SHORT_SHIFT			8
593572 #define	RETRY_LIMIT_LONG_SHIFT			0
....@@ -845,7 +824,7 @@
845824 #define TCR_SAT					BIT(24)
846825 #define RCR_MXDMA_OFFSET			8
847826 #define RCR_FIFO_OFFSET				13
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-#define RCR_OnlyErlPkt				BIT(31)
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+#define RCR_ONLYERLPKT				BIT(31)
849828 #define CWR					0xDC
850829 #define RETRYCTR				0xDE
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